CN106847892B - Thin film transistor, preparation method thereof, array substrate and display device - Google Patents
Thin film transistor, preparation method thereof, array substrate and display device Download PDFInfo
- Publication number
- CN106847892B CN106847892B CN201710131890.3A CN201710131890A CN106847892B CN 106847892 B CN106847892 B CN 106847892B CN 201710131890 A CN201710131890 A CN 201710131890A CN 106847892 B CN106847892 B CN 106847892B
- Authority
- CN
- China
- Prior art keywords
- layer
- ohmic contact
- metal layer
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 79
- 239000000758 substrate Substances 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title description 10
- 239000002184 metal Substances 0.000 claims abstract description 138
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 59
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 230000000694 effects Effects 0.000 abstract description 8
- 238000005530 etching Methods 0.000 description 24
- 238000000151 deposition Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004380 ashing Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6731—Top-gate only TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6746—Amorphous silicon
Landscapes
- Thin Film Transistor (AREA)
Abstract
本申请实施例提供了一种薄膜晶体管及其制备方法、阵列基板、显示装置，用以使得有源层与薄膜晶体管中的源极金属层和漏极金属层通过欧姆接触层连接，从而降低有源层与源极金属层和漏极金属层之间的欧姆接触电阻，提高薄膜晶体管中有源层与源极金属层和漏极金属层之间的欧姆接触效果，进而可以提高薄膜晶体管的工作稳定性。本申请实施例提供的一种薄膜晶体管，包括：源极金属层，在源极金属层之上的第一绝缘层，在第一绝缘层之上的漏极金属层；有源层和欧姆接触层，有源层通过欧姆接触层与源极金属层和漏极金属层相连；欧姆接触层包括第一欧姆接触层和第二欧姆接触层，第一欧姆接触层包括位于第一绝缘层两侧第一部分区域和第二部分区域。
The embodiments of the present application provide a thin film transistor and a method for fabricating the same, an array substrate, and a display device, so that the active layer is connected to the source metal layer and the drain metal layer in the thin film transistor through an ohmic contact layer, thereby reducing the active layer. The ohmic contact resistance between the source layer and the source metal layer and the drain metal layer improves the ohmic contact effect between the active layer and the source metal layer and the drain metal layer in the thin film transistor, thereby improving the operation of the thin film transistor stability. A thin film transistor provided by an embodiment of the present application includes: a source metal layer, a first insulating layer on the source metal layer, a drain metal layer on the first insulating layer; an active layer and an ohmic contact layer, the active layer is connected with the source metal layer and the drain metal layer through the ohmic contact layer; the ohmic contact layer includes a first ohmic contact layer and a second ohmic contact layer, and the first ohmic contact layer includes two sides of the first insulating layer. The first partial area and the second partial area.
Description
Technical Field
The application relates to the technical field of communication, in particular to a thin film transistor, a preparation method of the thin film transistor, an array substrate and a display device.
Background
Currently, high resolution display products are becoming the mainstream trend of the market, and the requirement for the pixel aperture ratio of the liquid crystal display panel is becoming higher and higher to realize the high resolution display of the liquid crystal display panel, so that the size reduction of a Thin Film Transistor (TFT) becomes more and more critical. In the related art, there is a vertical type TFT structure that can greatly reduce the size of a TFT, as shown in fig. 1, the vertical type TFT structure including: the pixel electrode includes a glass substrate 1, a buffer layer 2, a pixel layer 3, a source metal layer 4, a first insulating layer 5, a drain metal layer 6, an oxide (IGZO) layer 7, a second insulating layer 8, and a gate metal layer 9, wherein the oxide (IGZO) layer 7 belongs to an active layer. Although the vertical-type TFT structure shown in fig. 1 can greatly reduce the size of the TFT, the vertical-type TFT structure is currently only suitable for an oxide TFT, and an amorphous silicon TFT in which amorphous silicon is used as an active layer has poor ohmic contact due to direct contact between the active layer and a source metal layer and a drain metal layer, resulting in poor stability of the amorphous silicon TFT.
Disclosure of Invention
The embodiment of the application provides a thin film transistor and a preparation method thereof, an array substrate and a display device, which are used for enabling an active layer to be connected with a source electrode metal layer and a drain electrode metal layer in the thin film transistor through ohmic contact layers, so that ohmic contact resistance between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer is reduced, ohmic contact effects between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer in the thin film transistor are improved, and further the working stability of the thin film transistor can be improved.
The embodiment of the application provides a thin film transistor, including: a source metal layer, a first insulating layer over the source metal layer, a drain metal layer over the first insulating layer; the thin film transistor further includes: the active layer is connected with the source electrode metal layer and the drain electrode metal layer through the ohmic contact layer; wherein the ohmic contact layer comprises a first ohmic contact layer and a second ohmic contact layer, and the first ohmic contact layer comprises a first partial region and a second partial region which are positioned at two sides of the first insulating layer.
According to the thin film transistor provided by the embodiment of the application, the ohmic contact layer is arranged, so that the source electrode layer is connected with the source electrode metal layer and the drain electrode metal layer through the ohmic contact layer, namely the active layer is not in direct contact with the source electrode metal layer and the drain electrode metal layer, the ohmic contact resistance between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer in the thin film transistor is reduced, the ohmic contact effect between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer is improved, and the working stability of the vertical amorphous silicon thin film transistor can be improved.
Preferably, the second ohmic contact layer is located between the first insulating layer and the drain metal layer.
Preferably, the active layer includes a first partial active layer and a second partial active layer respectively located at two sides of the first insulating layer, the first partial active layer is located between the first partial region of the first ohmic contact layer and the second ohmic contact layer, and the second partial active layer is located between the second partial region of the first ohmic contact layer and the second ohmic contact layer.
Preferably, the active layer includes amorphous silicon, and/or the first and second ohmic contact layers include electron-type-doped amorphous silicon.
Preferably, the thin film transistor further includes:
a second insulating layer over the active layer;
a gate metal layer over the second insulating layer.
The array substrate provided by the embodiment of the application comprises the thin film transistor provided by the embodiment of the application.
The display device provided by the embodiment of the application comprises the array substrate provided by the embodiment of the application.
The preparation method of the thin film transistor provided by the embodiment of the application comprises the following steps: a first insulating layer is arranged on the source metal layer; providing a drain metal layer over the first insulating layer; the method further comprises the following steps: an active layer and an ohmic contact layer are arranged, and the active layer is connected with the source metal layer and the drain metal layer through the ohmic contact layer; wherein the ohmic contact layer comprises a first ohmic contact layer and a second ohmic contact layer, and the first ohmic contact layer comprises a first partial region and a second partial region which are positioned at two sides of the first insulating layer.
Preferably, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow.
Preferably, the active layer is formed after the ohmic contact layer and the drain metal layer are formed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a vertical oxide TFT in the prior art;
fig. 2 is a schematic structural diagram of a first thin film transistor provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of a second thin film transistor provided in the embodiment of the present application;
fig. 4 is a schematic structural diagram of a third thin film transistor provided in the embodiment of the present application;
fig. 5 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart of a first method for manufacturing the thin film transistor shown in fig. 4 according to an embodiment of the present disclosure;
fig. 7 is a schematic flowchart of a second method for manufacturing the thin film transistor shown in fig. 4 according to an embodiment of the present disclosure.
Detailed Description
The embodiment of the application provides a thin film transistor, an array substrate, a display panel, a display device and a preparation method, which are used for enabling a source electrode metal layer and a drain electrode metal layer in an active layer and the thin film transistor to be connected through an ohmic contact layer, so that ohmic contact resistance between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer is reduced, ohmic contact effects between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer in the thin film transistor are improved, and further working stability of the thin film transistor can be improved.
A thin film transistor provided in an embodiment of the present application, as shown in fig. 2, includes: a source metal layer 4, a first insulating layer 5 on the source metal layer 4, a drain metal layer 6 on the first insulating layer 5; an active layer 12 and an ohmic contact layer 16, a second insulating layer 8 on the active layer 12, and a gate metal layer 9 on the second insulating layer 8, wherein the active layer 12 is connected to the source metal layer 4 and the drain metal layer 6 through the ohmic contact layer 16, the ohmic contact layer 16 includes a first ohmic contact layer 10 and a second ohmic contact layer 11, and the first ohmic contact layer 10 includes a first partial region 17 and a second partial region 18 on both sides of the first insulating layer 5.
According to the thin film transistor provided by the embodiment of the application, the ohmic contact layer is arranged, so that the source electrode layer is connected with the source electrode metal layer and the drain electrode metal layer through the ohmic contact layer, namely the active layer is not in direct contact with the source electrode metal layer and the drain electrode metal layer, the ohmic contact resistance between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer is reduced, the ohmic contact effect between the active layer and the source electrode metal layer and between the active layer and the drain electrode metal layer is improved, and the working stability of the thin film transistor can be improved.
In the thin film transistor shown in fig. 2, the second ohmic contact layer 11 is located between the first insulating layer 5 and the drain metal layer 6, that is, there is an overlapping portion of the second ohmic contact layer and the first insulating layer in the projection direction in the vertical direction, and the second ohmic contact layer may be a continuous whole layer that is located between the first insulating layer and the drain metal layer, or may be a discontinuous layer that is located between the first insulating layer and the drain metal layer, as shown in fig. 3, in which the second ohmic contact layer 11 is divided into two partial regions that are located between the first insulating layer 5 and the drain metal layer 6. The cross section of the first insulating layer may be a trapezoid as shown in fig. 2 and 3 or a rectangle, and the present application will be described by taking the example in which the cross section of the first insulating layer is a trapezoid.
In the thin film transistor as shown in fig. 2, the active layer includes a first partial active layer 19 and a second partial active layer 20 respectively located at both sides of the first insulating layer, the first partial active layer 19 is located between the first partial region 17 of the first ohmic contact layer 10 and the second ohmic contact layer 11, and the second partial active layer 20 is located between the second partial region 18 of the first ohmic contact layer 10 and the second ohmic contact layer 11.
Preferably, the active layer includes amorphous silicon (a-Si).
Preferably, the first and second ohmic contact layers include electron-type doped amorphous silicon (n + a-Si).
Taking the case where the first and second active layers 19 and 20 are all the a-Si layers 15, the first ohmic contact layer, and the second ohmic contact layer is n + a-Si as an example, the thin film transistor structure provided in the embodiment of the present application is as shown in fig. 4, the second n + a-Si layer 14 is located between the first insulating layer 5 and the drain metal layer 6, and the a-Si layer 15 is in contact with the first n + a-Si layer 13 and the second n + a-Si layer 14 on both sides of the first insulating layer 5.
It should be noted that, in the thin film transistor shown in fig. 2, 3, and 4 provided in the embodiments of the present application, the active layer is not in contact with the source metal layer and the drain metal layer, but only when the active layer is in contact with the source metal layer and the drain metal layer through the ohmic contact layer, the ohmic contact resistance between the active layer and the source metal layer and the drain metal layer may be reduced, so as to improve the ohmic contact effect between the active layer and the source metal layer and the drain metal layer. Therefore, in practical cases, the active layer may be partially in contact with the source metal layer and the drain metal layer while the active layer is in contact with the source metal layer and the drain metal layer through the ohmic contact layer, that is, while the active layer is in good ohmic contact with the source metal layer and the drain metal layer.
The array substrate provided by the embodiment of the application comprises the thin film transistor provided by the embodiment of the application.
The display device provided by the embodiment of the application comprises the array substrate provided by the embodiment of the application.
For example, the display device provided in the embodiments of the present application may be a liquid crystal display panel, an Organic Light-Emitting Diode (OLED) display panel, or the like, or may be a device such as a mobile phone, a television, a computer, or the like.
Corresponding to the thin film transistor provided in the embodiment of the present application, the embodiment of the present application further provides a method for manufacturing a thin film transistor, as shown in fig. 5, the method includes:
s501, arranging a first insulating layer on the source metal layer;
s502, arranging a drain metal layer on the first insulating layer;
s503, an active layer and an ohmic contact layer are arranged, and the active layer is connected with the source metal layer and the drain metal layer through the ohmic contact layer;
wherein the ohmic contact layer comprises a first ohmic contact layer and a second ohmic contact layer, and the first ohmic contact layer comprises a first partial region and a second partial region which are positioned at two sides of the first insulating layer.
The thin film transistor preparation method provided by the embodiment of the application,
preferably, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow.
According to the thin film transistor manufacturing method provided by the embodiment of the application, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow, so that the thin film transistor manufacturing steps can be simplified, and the thin film transistor manufacturing process flow can be reduced.
Preferably, the active layer is formed after the ohmic contact layer and the drain metal layer are formed.
It should be noted that, if the active layer is disposed before the ohmic contact layer and the drain metal layer are formed, the active layer may be etched in the subsequent etching process of the ohmic contact layer and the drain metal layer, which may result in over-etching the active layer and affect the operation stability of the thin film transistor. According to the thin film transistor manufacturing method provided by the embodiment of the application, the active layer is arranged behind the first ohmic contact layer, the second ohmic contact layer and the drain electrode metal layer, so that the poor working stability of the thin film transistor caused by over-etching of the active layer is avoided.
The following describes a method for manufacturing a thin film transistor provided in the embodiments of the present application, taking the manufacturing of the thin film transistor structure shown in fig. 4 as an example.
Preferably, the thin film transistor further comprises a glass substrate.
In a first mode, as shown in fig. 6, the method for manufacturing a thin film transistor specifically includes the following steps:
s601, depositing a source electrode metal layer on the glass substrate 1, and etching to form a source electrode metal layer 4 after exposure;
s602, depositing a first insulating layer on the source metal layer 4, and etching to form a first insulating layer 5 after exposure;
s603, depositing an n + a-Si layer, and etching to form a first n + a-Si layer 13 and a second n + a-Si layer 14 after exposure; the second n + a-Si layer 14 is positioned on the first insulating layer 5, and the first n + a-Si layers 13 are positioned on two sides of the first insulating layer 5 and positioned on the source metal layer 4;
s604, depositing a drain metal layer on the second n + a-Si layer 14, and etching to form a drain metal layer 6 after exposure;
s605, depositing an a-Si layer after the step S604, and etching to form an a-Si layer 15 after exposure; the a-Si layer 15 is in contact with the first n + a-Si layer 13 and the second n + a-Si layer 14 on both sides of the first insulating layer 5;
s606, arranging a second insulating layer 8 on the a-Si layer 15, and etching a through hole (not shown in the figure) on the second insulating layer;
and S607, depositing a gate metal layer on the second insulating layer 8, and etching to form a gate metal layer 9 after exposure.
In a second mode, as shown in fig. 7, the method for manufacturing a thin film transistor specifically includes the following steps:
s701, depositing a source metal layer on the glass substrate 1, and etching to form a source metal layer 4 after exposure;
s702, depositing a first insulating layer on the source metal layer 4, and etching to form a first insulating layer 5 after exposure;
s703, depositing an n + a-Si layer, depositing a drain metal layer on the n + a-Si layer, etching the metal layer and the n + a-Si layer by adopting a half-transparent mask (HTM) to form a first n + a-Si layer 13 and a second n + a-Si layer 14, and further etching the metal layer by adopting photoresist ashing to form a drain metal layer 6; the second n + a-Si layer 14 is positioned on the first insulating layer 5, the drain metal layer 6 is positioned on the second n + a-Si layer 14, and the first n + a-Si layers 13 are positioned on both sides of the first insulating layer 5 and on the source metal layer 4;
s704, depositing an a-Si layer, and etching to form an a-Si layer 15 after exposure; the a-Si layer 15 is in contact with the first n + a-Si layer 13 and the second n + a-Si layer 14 on both sides of the first insulating layer 5;
s705, arranging a second insulating layer 8 on the a-Si layer 15, and etching a via hole (not shown in the figure) on the second insulating layer;
and S706, depositing a gate metal layer on the second insulating layer 8, and etching to form a gate metal layer 9 after exposure.
By adopting the two preparation methods of the thin film transistor provided by the embodiment of the application, the first n + a-Si layer and the second n + a-Si layer are arranged between the a-Si layer and the source metal layer and between the a-Si layer and the drain metal layer, so that the ohmic contact resistance between the a-Si layer and the source metal layer and between the a-Si layer and the drain metal layer can be reduced, and the ohmic contact effect between the a-Si layer and the source metal layer and between the a-Si layer and the drain metal layer can be improved. Meanwhile, in the two thin film transistor preparation modes, the first n + a-Si layer and the second n + a-Si layer are arranged on the same layer and are formed in the same process flow, so that the steps for preparing the thin film transistor are simplified. And the a-Si layer is etched after the n + a-Si layer and the drain electrode metal layer are etched, so that the etching time and the etching rate of the a-Si layer can be controlled, and the working stability of the TFT (thin film transistor) caused by over-etching the a-Si layer is not deteriorated.
It should be noted that, the two ways of manufacturing the thin film transistor provided in the embodiments of the present application are different only in the etching sequence of each layer of the thin film transistor during the manufacturing process of the thin film transistor, but the thin film transistor shown in fig. 4 can be formed, and the two different ways of manufacturing the thin film transistor have no influence on the performance of the thin film transistor. In addition, compared with the first mode, the thin film transistor preparation method provided by the second mode adopts the semi-permeable mask process to etch the drain metal layer and the n + a-Si layer, so that a mask (mask) can be reduced, the production cost is reduced, the one-step exposure process is reduced, the process time is shortened, and the productivity can be increased.
To sum up, according to the thin film transistor, the array substrate, the display panel, the display device and the method for manufacturing the thin film transistor provided by the embodiment of the present application, by providing the ohmic contact layer, the source layer is connected to the source metal layer and the drain metal layer through the ohmic contact layer, that is, the active layer is not in complete direct contact with the source metal layer and the drain metal layer, so that ohmic contact resistance between the active layer and the source metal layer and the drain metal layer is reduced, ohmic contact effect between the active layer and the source metal layer and between the active layer and the drain metal layer is improved, and thus the working stability of the thin film transistor can be improved. In addition, according to the thin film transistor manufacturing method provided by the embodiment of the application, the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow, so that the steps of manufacturing the thin film transistor are simplified. In addition, as the active layer is etched after the ohmic contact layer and the drain electrode metal layer, the etching time and the etching rate of the active layer can be controlled, and the stability of the thin film transistor caused by over-etching the active layer is not deteriorated.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (7)
1. A thin film transistor, comprising: a source metal layer, a first insulating layer over the source metal layer, a drain metal layer over the first insulating layer, wherein the thin film transistor further comprises: the active layer is connected with the source electrode metal layer and the drain electrode metal layer through the ohmic contact layer; the first ohmic contact layer comprises a first partial area and a second partial area which are positioned on two sides of the first insulating layer;
the second ohmic contact layer is positioned between the first insulating layer and the drain metal layer;
the thin film transistor further includes:
a second insulating layer over the active layer;
a gate metal layer over the second insulating layer;
the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow.
2. The thin film transistor of claim 1, wherein the active layer comprises a first partial active layer and a second partial active layer respectively disposed on both sides of the first insulating layer, the first partial active layer being disposed between the first partial region of the first ohmic contact layer and the second ohmic contact layer, and the second partial active layer being disposed between the second partial region of the first ohmic contact layer and the second ohmic contact layer.
3. The thin film transistor of claim 1, wherein the active layer comprises amorphous silicon, and/or the first and second ohmic contact layers comprise electron-type doped amorphous silicon.
4. An array substrate comprising the thin film transistor according to any one of claims 1 to 3.
5. A display device comprising the array substrate according to claim 4.
6. A method for preparing a thin film transistor comprises the following steps: a first insulating layer is arranged on the source metal layer; providing a drain metal layer over the first insulating layer, wherein the method further comprises: an active layer and an ohmic contact layer are arranged, and the active layer is connected with the source metal layer and the drain metal layer through the ohmic contact layer; the first ohmic contact layer comprises a first partial area and a second partial area which are positioned on two sides of the first insulating layer; the second ohmic contact layer is positioned between the first insulating layer and the drain metal layer;
the method further includes the steps of forming a second insulating layer over the active layer and forming a gate electrode over the second insulating layer;
the first ohmic contact layer and the second ohmic contact layer are formed in the same process flow.
7. The method of manufacturing a thin film transistor according to claim 6, wherein the active layer is formed after the ohmic contact layer and the drain metal layer are formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710131890.3A CN106847892B (en) | 2017-03-07 | 2017-03-07 | Thin film transistor, preparation method thereof, array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710131890.3A CN106847892B (en) | 2017-03-07 | 2017-03-07 | Thin film transistor, preparation method thereof, array substrate and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106847892A CN106847892A (en) | 2017-06-13 |
| CN106847892B true CN106847892B (en) | 2020-03-31 |
Family
ID=59137356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710131890.3A Active CN106847892B (en) | 2017-03-07 | 2017-03-07 | Thin film transistor, preparation method thereof, array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106847892B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114373772B (en) * | 2021-12-29 | 2024-10-01 | 长沙惠科光电有限公司 | Array substrate, preparation method thereof and display panel |
| CN116230720A (en) * | 2022-12-08 | 2023-06-06 | 武汉华星光电技术有限公司 | Display panel and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397721A (en) * | 1993-01-29 | 1995-03-14 | Goldstar Electron Co., Ltd. | Method for fabricating vertical thin film transistor |
| CN101097871A (en) * | 2007-07-05 | 2008-01-02 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
-
2017
- 2017-03-07 CN CN201710131890.3A patent/CN106847892B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397721A (en) * | 1993-01-29 | 1995-03-14 | Goldstar Electron Co., Ltd. | Method for fabricating vertical thin film transistor |
| CN101097871A (en) * | 2007-07-05 | 2008-01-02 | 友达光电股份有限公司 | Thin film transistor, pixel structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106847892A (en) | 2017-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11257849B2 (en) | Display panel and method for fabricating the same | |
| CN105097675B (en) | Array base palte and preparation method thereof | |
| US8952384B2 (en) | TFT, mask for manufacturing the TFT, array substrate and display device | |
| CN107068770B (en) | thin film transistor, preparation method thereof, array substrate and display panel | |
| US20160276376A1 (en) | Array substrate, method for fabricating the same, and display device | |
| US9530800B2 (en) | Array substrate, display panel and method for preparing array substrate | |
| US11139316B2 (en) | LTPS array substrate and method for manufacturing same | |
| CN105514120B (en) | A kind of double grid tft array substrate and its manufacturing method and display device | |
| CN203871327U (en) | Array substrate and display device | |
| CN104900655A (en) | Array substrate and preparation method thereof, and display device | |
| WO2016173027A1 (en) | Thin film transistor array substrate and manufacturing method therefor | |
| US20180212061A1 (en) | Dual gate oxide thin-film transistor and manufacturing method for the same | |
| WO2020082623A1 (en) | Thin film transistor and fabrication method therefor | |
| CN111710725A (en) | Double gate electrode metal oxide thin film transistor and preparation method thereof | |
| WO2021031532A1 (en) | Touch array substrate and preparation method thereof | |
| US20160358944A1 (en) | Oxide Semiconductor TFT Array Substrate and Method for Manufacturing the Same | |
| CN106847892B (en) | Thin film transistor, preparation method thereof, array substrate and display device | |
| WO2016011755A1 (en) | Thin film transistor and preparation method therefor, display substrate, and display apparatus | |
| CN104810375B (en) | A kind of array substrate and preparation method thereof and a kind of display device | |
| CN108447916B (en) | Thin film transistor and preparation method thereof, array substrate, display device | |
| CN106206615B (en) | Manufacturing method of array substrate | |
| CN106898654B (en) | A kind of thin film transistor and its preparation method, array substrate, display device | |
| CN110504164B (en) | Thin film transistor, method of manufacturing the same, and display device | |
| CN103794556A (en) | Array substrate, manufacturing method thereof and liquid crystal display device | |
| CN107634034A (en) | Method for manufacturing active array switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |