CN106847810A - Modified GTO structures, control method and preparation method that BJT is aided in - Google Patents

Abstract

The invention discloses a BJT-assisted improved GTO structure, control method and preparation method. The improved GTO device adopts a monolithic integration method to connect an auxiliary bipolar junction transistor BJT in parallel on the gate turn-off thyristor GTO, The parallel GTO and BJT share electrodes, and the electrodes include cathode, anode and gate; the control method controls the GTO structure to conduct in the BJT working mode according to the positive bias voltage applied between the anode and the cathode of the device, or the BJT The working mode opened together with GTO is turned on; the preparation method adds ion implantation in the current GTO or BJT process flow, and is compatible with the current GTO and BJT preparation process. The invention can satisfy switching between the low-current working mode and the high-current working mode, is beneficial to reduce the power loss of the device, and effectively improves the switching speed of the original GTO, and is suitable for power electronic systems with large load changes.

Description

BJT-assisted improved GTO structure, control method and preparation method

technical field

The invention relates to the technical field of semiconductors, in particular to a BJT-assisted improved GTO structure, a control method and a preparation method.

Background technique

After more than 30 years of development, modern power electronics technology has become an independent and increasingly mature important subject involving a wide range of fields. It plays a vital role in the transformation of traditional industries and the development of high-tech industries. Its application fields cover various industrial sectors of the national economy, and it is one of the important key technologies in the 21st century. Power electronic devices are an important foundation of power electronics technology and the core components of power electronics technology for power conversion and control. After decades of development, power electronic devices have gradually matured, especially the development of Si-based power electronic devices has reached the theoretical limit of Si materials, in order to develop higher performance power electronic devices.

At present, SiC and GaN are generally used as substitute materials for Si in the world to obtain higher performance power electronic devices. However, although SiC and GaN materials have wider band gaps and are more suitable for high-voltage devices, the intrinsic carrier concentration is low and the built-in potential is high, resulting in a low forward voltage drop of a single PN junction. Large, up to 2.8V. GTO is widely used in high-voltage and high-current high-power systems. Its half-cell structure is shown in Figure 2 and its volt-ampere characteristic curve is shown in Figure 4. However, the forward conduction voltage drop of GTO is relatively large, especially for wide-bandgap GTO devices. Its turn-on voltage reaches 2.8V, which makes the forward conduction loss of the power device larger. BJT is usually used in small and medium power systems, and has the advantages of fast switching speed. The gain of BJT is limited. When conducting a large current, a large base injection current is required, resulting in large driving loss. Its semi-cellular structure is shown in Figure 1 and volts See Figure 3 for the safety characteristic curve. Therefore, there are no devices in the existing power electronic devices that are suitable for both small currents and large currents in a wide application range, and cannot adapt to systems with large load changes.

Contents of the invention

Aiming at the defects in the prior art, the present invention provides a BJT-assisted improved GTO structure, control method and preparation method, which has low power consumption and fast switching speed, and can meet the requirements of low-current operation mode (BJT mode) and high-current operation. Switching between modes (GTO mode), on the one hand, helps to reduce the power loss of the device, and on the other hand, effectively improves the switching speed of the original GTO, so the device is suitable for power electronic systems with large load changes.

In order to solve the above technical problems, the present invention provides the following technical solutions:

On the one hand, the present invention provides a BJT-assisted improved GTO structure. The GTO device is a semiconductor device that integrates a gate turn-off thyristor GTO and a bipolar junction transistor BJT in parallel through a monolithic integration process;

The parallel GTO and BJT share electrodes, and the electrodes include cathode, anode and gate.

Further, the GTO is a P-type gate turn-off thyristor, the BJT is a PNP-type bipolar junction transistor, and the P-type GTO and the PNP-type BJT are connected in parallel.

Further, the device composed of parallel P-type GTO and PNP-type BJT includes:

P-type collector region, N-type base region, P-type drift region, N-type emitter region and P-type emitter region connected in sequence;

And the P-type collector region is the anode of the device, the N-type base region includes the gate of the GTO structure, and both the N-type emitter region and the P-type emitter region are the cathode of the device.

Further, the GTO is an N-type gate turn-off thyristor, the BJT is an NPN bipolar junction transistor, and the N-type GTO and the NPN BJT are connected in parallel.

Further, the device composed of N-type GTO and NPN-type BJT in parallel includes:

N-type emitter region, P-type base region, N-type drift region, P-type collector region and N-type collector region connected in sequence;

In addition, the N-type emitter region is the cathode of the device, the P-type base region includes the gate of the device, and both the P-type collector region and the N-type collector region are anodes of the device.

On the one hand, the present invention provides a kind of control method of described GTO structure, it is characterized in that, described control method comprises:

According to the change of the positive bias voltage applied between the anode and the cathode of the device, the device is controlled to be turned on in the working mode of the BJT, or in the working mode in which the BJT and the GTO are both turned on.

Further, according to the change of the positive bias voltage applied between the anode and the cathode of the device, the device is controlled to be turned on in the working mode of the BJT, or in the working mode in which the BJT and the GTO are jointly turned on Conduct conduction, including:

Step 1. Applying a positive bias voltage between the anode and the cathode of the device, so that the device is in a forward blocking state;

Step 2. Applying a positive bias voltage between the gate and the cathode and the forward bias voltage is lower than the turn-on voltage of the GTO, the BJT starts the working mode, so that the device is turned on in the working mode of the BJT;

Step 3. When the current flowing through the device increases so that the positive bias voltage across the anode and cathode of the device is equal to or higher than the turn-on voltage of the GTO, the GTO turns on the working mode, and simultaneously with the BJT Work.

Further, the method also includes:

A reverse bias voltage is applied between the gate and cathode of the device, and the gate current flowing through the device is a negative current, so that the device is turned off.

On the other hand, the present invention provides a kind of preparation method of described GTO structure, it is characterized in that, described preparation method comprises:

To make a new type of power semiconductor device, in the existing gate turn-off thyristor GTO or bipolar junction transistor BJT power semiconductor device preparation process, add a step in the back part of the impurity implantation of the opposite type of impurity to the back of the current device , forming a new power semiconductor device structure.

Further, in the preparation of a BJT-assisted improved GTO structure, in the preparation process of the existing gate turn-off thyristor GTO or bipolar junction transistor BJT power semiconductor device, an additional step is added to the back part of the implantation and the back of the current device. The process steps of impurity of the opposite type to form a BJT-assisted improved GTO structure, including:

Step A. Pretreating the wafer, and etching multiple times on the wafer after pretreatment to form a front pattern;

Step B. performing multiple ion implantations on the front side of the wafer to obtain gate contact windows and terminal structures;

Step C. If the current semiconductor is a BJT, implant impurities of the opposite type to the original doping type on the back of the BJT, so that GTO is formed in the original BJT structure; if the current semiconductor is GTO, implant and Impurities of the opposite type to the original doping type make BJT form in the original GTO structure;

Step D. Annealing and activating the implanted ions, and completing sacrificial oxidation, metal contact process, surface passivation process and metal interconnection process, and forming the final metal electrode.

It can be seen from the above-mentioned technical scheme that a BJT-assisted improved GTO structure, control method and preparation method described in the present invention, the BJT-assisted improved GTO structure is a gate turn-off thyristor GTO and A bipolar junction transistor (BJT) integrated semiconductor device; parallel GTOs and BJTs share electrodes, and the electrodes include cathodes, anodes and gates. The present invention can satisfy switching between the low-current working mode (BJT mode) and the high-current working mode (GTO mode), on the one hand, it is beneficial to reduce the power loss of the device, and on the other hand, it effectively improves the switching performance of the original GTO. speed, so this device is very suitable for power electronic systems with large load changes.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a half-cell structure diagram of a traditional BJT structure in the prior art;

Fig. 2 is a half-cell structure diagram of a traditional GTO structure in the prior art;

FIG. 3 is a graph showing the volt-ampere characteristics of a SiC BJT with a traditional structure in the prior art;

Fig. 4 is the volt-ampere characteristic curve diagram of the SiC GTO of traditional structure in the prior art;

5 is a schematic structural view of a BJT-assisted improved GTO structure in Embodiment 1 of the present invention;

Fig. 6 is a schematic structural view of the first embodiment of the BJT-assisted improved GTO structure in Example 2 of the present invention;

Fig. 7 is a schematic structural diagram of a second specific implementation of the BJT-assisted improved GTO structure in Example 3 of the present invention;

Fig. 8 is an equivalent structure diagram of a BJT-assisted improved GTO structure in an application example of the device of the present invention;

9 is an equivalent circuit diagram of a BJT-assisted improved GTO structure in an application example of the device of the present invention;

Fig. 10 is a volt-ampere characteristic curve diagram of a BJT-assisted improved GTO structure in an application example of the device of the present invention;

FIG. 11 is a schematic structural view of a specific implementation of the control method of the BJT-assisted improved GTO structure in Embodiment 4 of the present invention;

FIG. 12 is a structural schematic diagram of a specific implementation method of the preparation method of the BJT-assisted improved GTO structure in Example 5 of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Embodiment 1 of the present invention provides a BJT-assisted improved GTO structure. Referring to Fig. 5, the BJT-assisted improved GTO structure BJT-assisted improved GTO structure specifically includes the following contents:

GTO device is a semiconductor device that integrates gate turn-off thyristor GTO and bipolar junction transistor BJT in parallel through process monolithic integration;

The GTO and the BJT are connected in parallel, and after the parallel connection, the GTO and the BJT share electrodes, and the electrodes include a cathode Cathode, an anode Anode and a gate electrode Gate.

In the above description, when the forward bias voltage loaded in the BJT-assisted improved GTO structure is lower than the GTO turn-on voltage, the BJT is forward-conducting and the GTO is in the forward blocking mode. When the set voltage is equal to or higher than the turn-on voltage, the GTO and BJT are in the forward conduction state at the same time. From the perspective of the cell, the improved GTO structure assisted by the BJT can be regarded as partly injected on the back of the BJT and the original back of the BJT. Doping impurities of the opposite type to form GTO in the original BJT structure; or it can also be seen as introducing BJT structure by doping on the basis of GTO structure

It can be seen from the above description that the embodiment of the present invention integrates a gate turn-off thyristor GTO and a bipolar junction transistor BJT in a BJT-assisted improved GTO structure, and the BJT-assisted improved GTO structure can work at a small current In BJT mode, the GTO and BJT are simultaneously turned on at high current, which effectively improves the application range of the device, and through feedback control, the device can automatically change the working mode by tracking the change of the load.

The embodiment of the present invention provides the first specific implementation manner of the above-mentioned BJT-assisted improved GTO structure. Referring to Figure 6, the BJT-assisted improved GTO structure specifically includes the following:

The P-type GTO and PNP-type BJT are connected in parallel, and the improved GTO structure assisted by the BJT is sequentially connected to a P-type collector region, an N-type base region, a P-type drift region, an N-type emitter region and a P-type emitter region.

In the above description, the GTO is a P-type gate turn-off thyristor, the BJT is a PNP-type bipolar junction transistor; and the P-type collector region is the anode of the device, and the N-type base region includes the The gate electrode of the device, the N-type emitter region and the P-type emitter region are all cathodes of the device.

It can be seen from the above description that the embodiments of the present invention provide a specific structure of the BJT-assisted improved GTO structure, which can effectively improve the working efficiency of the device.

Embodiments of the present invention provide a second specific implementation manner of the above-mentioned BJT-assisted improved GTO structure. Referring to Figure 7, the BJT-assisted improved GTO structure specifically includes the following:

N-type GTO and NPN-type BJT are connected in parallel, and the improved GTO structure assisted by the BJT is sequentially connected with N-type emitter region, P-type base region, N-type drift region, P-type collector region and N-type collector region.

In the above description, the GTO is an N-type gate turn-off thyristor, the BJT is an NPN bipolar junction transistor, and the N-type emitter region is the cathode of the device, and the P-type base region includes the device The gate electrode, the P-type collector region and the N-type collector region are all anodes of the device.

It can be seen from the above description that the embodiments of the present invention provide another specific structure of the BJT-assisted improved GTO structure, which makes the way to realize the device highly diverse and highly applicable.

In order to further illustrate this solution, the present invention also provides a specific application example of a BJT-assisted improved GTO structure used for multi-variable loads. Referring to Figures 8 to 10, the specific content of the BJT-assisted improved GTO structure is as follows:

The BJT-assisted improved GTO structure can be seen structurally as a P-type GTO and a PNP-type BJT connected in parallel, and the GTO and BJT share all electrodes (P-type structure BJT-assisted improved GTO structure); or It can be regarded as an N-type GTO and an NPN-type BJT connected in parallel, and the GTO and BJT share all electrodes (an improved GTO structure assisted by an N-type structure BJT). Taking the improved GTO structure assisted by N-type structure BJT as an example, the structure from top to bottom includes cathode metal, N-type emitter region, gate metal, P-type base region, N-type drift region, P-type collector region, N-type Collector area, anode metal.

It can be seen from the above description that the application example of the present invention effectively improves the applicable scope of the device.

An embodiment of the present invention provides a specific implementation manner of the control method for the above-mentioned BJT-assisted improved GTO structure. Referring to Figure 11, the control method specifically includes the following content:

According to the change of the positive bias voltage applied between the anode and the cathode of the device, the device is controlled to be turned on in the working mode of the BJT, or in the working mode in which the BJT and the GTO are jointly turned on, specifically Proceed as follows:

Step 100: Applying a positive bias voltage between the anode and the cathode of the device, so that the device is in a forward blocking state.

Step 200: applying a positive bias voltage between the gate and the cathode, and the forward bias voltage is lower than the turn-on voltage of the GTO, and the BJT is turned on in the working mode, so that the device is turned on in the working mode of the BJT.

Step 300: When the current flowing through the device increases so that the positive bias voltage across the anode and cathode of the device is equal to or higher than the turn-on voltage of the GTO, the GTO turns on the working mode, and simultaneously with the BJT Work.

Step 400: Apply a reverse bias voltage between the gate and cathode of the device, and the gate current flowing through the device is a negative current, so that the device is turned off.

It can be seen from the above description that the embodiment of the present invention provides a control method for the BJT-assisted improved GTO structure, so that the BJT-assisted improved GTO structure can work in BJT mode when the current is small, and work in the BJT mode when the current is high. The simultaneous conduction mode of GTO and BJT effectively improves the application range of the device.

In order to further illustrate this solution, the present invention also provides a specific application example of the above-mentioned device control method, and the specific content of the control method is as follows:

Taking the improved GTO structure assisted by the N-type structure BJT as an example, the working principle of the improved GTO structure assisted by the structure BJT is as follows:

Turn-on process: First, add a positive bias between the anode and the cathode, that is, when U _AK > 0, the PN junction between the P-type base region and the N-type drift region is in a reverse bias state, which bears the external bias voltage, and the emitter region Without providing electrons, the entire device is not conducting and is in a forward blocking state. At this time, a forward voltage is applied between the gate and the cathode, that is, U _GK >0, and the minority carrier injection effect brought about by the forward bias of the PN junction between the N-type emitter and the P-type base makes the electrons in the N-type emitter pass through This PN junction enters the P-type base region. As the electrons go deep into the P-type base region, part of the electrons recombine with the holes in the P-type base region, and the holes lost due to recombination are replenished by the gate injection current. Usually the thickness of the P-type base region is small, and most of the electrons will reach the PN junction formed by the N-type drift region and the P-type base region, where the electrons will be captured by the electric field and transported to the N-type drift region, so that the entire device is BJT mode conduction. If the device is turned on in BJT mode, the current flowing through the device continues to increase, and the voltage drop across the anode and cathode of the device increases accordingly. When the current reaches a certain critical value, the voltage drop across the anode and cathode of the device reaches GTO The turn-on voltage of the P-type collector region and the PN junction in the N-type drift region will lead to forward conduction, and a large number of holes in the P-type collector region will flood into the N-type drift region, forming a conductance modulation effect in the drift region, and flowing through the entire The current of the device increases rapidly, and at this time, the device works in the mode of GTO and BJT working simultaneously.

Turn-off process: apply a reverse voltage between the gate and cathode, that is, U _GK <0, at this time, the PN junction between the N-type emitter region and the P-type base is reverse-biased, and the minority carrier injection effect in the P-type base region At the same time, the remaining carriers recombine or are extracted from the gate, forming a negative current at the gate. At the same time, the PN junction between the P-type base region and the N-type drift region returns to the state of bearing the external reverse bias voltage, and the device is turned off. broken.

It can be seen from the above description that the application example of the present invention takes the improved GTO structure assisted by N-type structure BJT as an example, and provides the working principle and control process of the improved GTO structure assisted by the structure BJT, which effectively improves the scope of application of the device. And through feedback control, the device can automatically change the working mode by tracking the change of the load.

An embodiment of the method for preparing the above-mentioned BJT-assisted improved GTO structure is provided in an embodiment of the present invention. Referring to Figure 12, the preparation method specifically includes the following contents:

To make a new type of power semiconductor device, in the existing gate turn-off thyristor GTO or bipolar junction transistor BJT power semiconductor device preparation process, add a step in the back part of the impurity implantation of the opposite type of impurity to the back of the current device , to form a new power semiconductor device structure, the specific steps are as follows:

Step A00: Pretreating the wafer, and performing multiple etchings on the wafer after the pretreatment to form front-side patterns.

Step B00: performing multiple ion implantations on the front side of the wafer to obtain gate contact windows and terminal structures.

Step C00: If the current semiconductor is a BJT, implant impurities of the opposite type to the original doping type on the back of the BJT, so that GTO is formed in the original BJT structure; if the current semiconductor is GTO, implant and Impurities of the opposite type to the original doping form the BJT in the original GTO structure.

Step D00: Annealing and activating the implanted ions, and completing sacrificial oxidation, metal contact process, surface passivation process and metal interconnection process, and forming the final metal electrode.

It can be seen from the above description that the embodiment of the present invention provides a method for preparing a BJT-assisted improved GTO structure, so that the GTO structure can work in the BJT mode when the current is small, and work in the GTO and BJT simultaneously when the current is large. The common mode effectively improves the scope of application of the device.

In order to further illustrate this solution, the present invention also provides a specific application example of the above-mentioned device preparation method, and the specific content of the control method is as follows:

The preparation method of the BJT-assisted improved GTO structure is basically compatible with the preparation process of GTO or BJT, and only needs to add a step of ion implantation in the preparation process of GTO or BJT, specifically with the compatible NPN type BJT preparation process For example: when preparing a BJT-assisted improved GTO structure, it is only necessary to add a step after the ion implantation in the base region in the BJT preparation process, perform a step of ion implantation in the back part area, and then perform annealing activation, and other process steps can be Directly follow the process flow of BJT.

S1. Wafer preparation, taking a commercially prepared BJT wafer as an example.

S2. Use acetone to perform organic ultrasonic cleaning for 10 minutes, then use concentrated sulfuric acid to clean the surface, then use the RCA standard wafer cleaning method to clean the wafer, and finally soak in 10% hydrofluoric acid solution for 5 minutes to remove the oxide film on the wafer surface .

S3. Forming the mesa of the N-type emission region: first, deposit a layer of metal or other materials on the surface of the wafer as a mask barrier layer, and then perform photolithographic transfer through the first mask to obtain the pattern of the N-type emission region, and then Etch away the excess mask blocking material and remove the photoresist to obtain the mask pattern, then use RIE or ICP equipment or other methods to etch the semiconductor material to form the pattern of the N-type emitter region on the wafer, and at the same time form Alignment mark L0, finally remove the mask stop layer and clean the wafer.

S4. Forming the P-type base region mesa: first, deposit a layer of metal or other materials on the wafer surface as a mask barrier layer, and then transfer the pattern of the P-type base region through the second mask plate photolithography, and then engrave Etch away the excess mask blocking material and remove the photoresist to obtain the mask pattern, then use RIE or ICP equipment or other methods to etch the semiconductor material to form the pattern of the P-type base region on the wafer, and the pattern is aligned The L0 layer is contrast marked, and finally the mask barrier is removed and the wafer is cleaned.

S5. Perform ion implantation in the P-type base region: first, deposit a layer of metal or other materials on the surface of the wafer as an ion implantation barrier, and then obtain the P-type base region through photolithographic transfer of the third mask. The window pattern of ion implantation, and then etch off the excess mask blocking material to form an ion implantation blocking window, and then perform ion implantation under suitable conditions to increase the doping concentration of the gate contact area, facilitate the formation of ohmic contacts and reduce the Contact resistance.

S6. Perform ion implantation in the terminal area: first, deposit a layer of metal or other materials on the surface of the wafer as an ion implantation barrier, and then obtain the ion implantation window pattern of the terminal structure through photolithography transfer of the fourth mask, and then Etch away the excess mask barrier material to form an ion implantation barrier window, and then perform ion implantation under suitable conditions to form a GR terminal structure, effectively improve the withstand voltage capability of the device, and finally remove all barrier layer materials on the wafer surface and clean the wafer.

S7. After the front ion implantation is completed, redeposit a layer of SiO2 and AlN or a carbon film on the front side as a protective layer during high temperature annealing of the surface.

S8. Ion implantation on the back side: first, deposit a layer of metal or other materials on the back side of the wafer as an ion implantation barrier layer, and then obtain the ion implantation window pattern of the back structure through photolithography transfer of the fifth mask, and then engrave Etch away the excess mask barrier material to form an ion implantation barrier window, then perform ion implantation under suitable conditions to form the doping distribution required for the structure, and finally remove all barrier layer materials on the wafer surface and clean the wafer;

S9. After the back ion implantation is completed, redeposit a layer of SiO2 and AlN or a carbon film on the back as a protective layer during high-temperature annealing of the surface.

S10 , performing high-temperature annealing after ion implantation, so as to activate and redistribute the ions implanted into the semiconductor material. After the annealing is completed, remove the protective layer and clean the wafer.

S11. Deposit a layer of SiO2 on the front surface of the wafer as sacrificial oxidation, and then deposit a passivation layer.

S12. Forming the front P-type ohmic contact: firstly, the front P-type ohmic contact window pattern is obtained through photolithographic transfer of the sixth mask, and then the redundant sacrificial oxide layer and passivation layer are etched away to form the P-type ohmic contact window. Next, contact metal is deposited on the surface of the wafer, and then the photoresist and excess metal are removed through a stripping process, and then the wafer is cleaned and dried, and metallization annealing is performed under appropriate conditions to form a P-type ohmic contact.

S13. Forming the front N-type ohmic contact: first, obtain the front N-type ohmic contact window pattern through photolithographic transfer of the seventh mask, and then etch away the redundant sacrificial oxide layer and passivation layer to form the N-type ohmic contact window. Next, contact metal is deposited on the surface of the wafer, and then the photoresist and excess metal are removed through a stripping process, and then the wafer is cleaned and dried, and metallization annealing is performed under appropriate conditions to form an N-type ohmic contact.

S14. Forming a back ohmic contact: forming a back ohmic contact by depositing a contact metal on the back of the wafer and performing metallization annealing.

S15. Form the interlayer isolation of the gate and cathode on the front side: first deposit a thicker interlayer dielectric, such as BPSG, etc. on the front side, and then obtain the layer between the front gate and cathode through photolithographic transfer of the eighth mask The interlayer dielectric pattern is then etched away to form the interlayer dielectric pattern between the gate and the cathode.

S16. Form the metal interconnection of the gate and cathode on the front side: first deposit a thick layer of metal on the front side, such as Al or Ag, etc., and then obtain the front gate and cathode through photolithographic transfer of the ninth mask The electrode pattern, and then the gate and cathode electrodes are separated by etching to form the outermost metal electrode of the device, and finally the photoresist is removed and the surface of the device is cleaned to complete the process.

In terms of structure, the BJT-assisted improved GTO structure can be regarded as the parallel connection of GTO and BJT. Taking the N-type structure BJT-assisted improved GTO structure as an example, the structure includes cathode metal, N-type emitter, Gate metal, P-type base region, N-type drift region, P-type collector region, N-type collector region, anode metal. For Si devices, the forward conduction voltage drop of the PN junction is 0.7V, and for SiC devices, the forward conduction voltage drop of the PN junction reaches 2.8V. These voltage drops generated by the forward conduction of the PN junction will be cause additional losses. This new structure combines the advantages of BJT and GTO. At a lower forward bias voltage, the device is normally turned on and works in the BJT mode, which reduces the large conduction loss caused by the large forward voltage drop of GTO. , and at the same time, when the forward bias voltage is large, the device is fully turned on, working in the mode of GTO and BJT working at the same time, providing a path for the flow of large current. , when the structure is prepared, its terminal structure has diversity, for example, the terminal structure used can be JTE, FLR, FP, etc. or a combination of different terminal structures.

The present invention can control the device to work in the BJT mode or the mode in which GTO and BJT work simultaneously by controlling the input current of the gate, which can not only reduce the loss of the system, but also make the system work under light load and heavy load conditions through feedback control Flexible switching makes this device ideal for systems with changing loads. In addition, the preparation method of the new structure only needs to add a one-step ion implantation process to the existing mature GTO or BJT process flow, so it is compatible with the current GTO or BJT process.

It can be seen from the above description that the application example of the present invention provides a method for preparing a BJT-assisted improved GTO structure. The preparation is fast and accurate, and the cost is saved.

The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be described in the foregoing embodiments Modifications are made to the recorded technical solutions, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. the modified GTO structures that a kind of BJT is aided in, it is characterised in that modified GTO devices are by single chip integrated mode Gate turn off thyristor GTO and bipolar junction transistor BJT are carried out into integrated semiconductor devices in parallel；

GTO in parallel and BJT shared electrodes, and the electrode includes negative electrode, anode and gate pole.

2. the modified GTO structures that BJT according to claim 1 is aided in, it is characterised in that the GTO is that p-type gate pole is closed Disconnected IGCT, the BJT is positive-negative-positive bipolar junction transistor, and p-type GTO is in parallel with positive-negative-positive BJT.

3. GTO structures according to claim 2, it is characterised in that the institute being made up of p-type GTO in parallel and positive-negative-positive BJT Stating device includes：

P-type collecting zone, N-type base, P drift area, N-type launch site and the p-type launch site being sequentially connected；

And p-type collecting zone is the anode of the device, N-type base includes the gate pole of the GTO structures, N-type launch site and p-type Launch site is the negative electrode of the device.

4. GTO structures according to claim 1, it is characterised in that the GTO is N-type gate turn off thyristor, described BJT is bipolar npn junction transistor, and N-type GTO is in parallel with NPN type BJT.

5. GTO structures according to claim 4, it is characterised in that the institute being made up of N-type GTO in parallel and NPN type BJT Stating device includes：

N-type launch site, p-type base, N-type drift region, p-type collecting zone and the N-type collecting zone being sequentially connected；

And N-type launch site is the negative electrode of the device, p-type base includes the gate pole of the device, p-type collecting zone and N-type collection Electric area is the anode of the device.

6. a kind of control method of GTO structures as described in any one of claim 1 to 5, it is characterised in that the control method Including：

According to the change for being applied to positive bias voltage between the anode of the device and negative electrode, the device is controlled with the BJT Mode of operation conducting, or turned on the mode of operation of the common unlatchings of the BJT and GTO.

7. control method according to claim 6, it is characterised in that the basis is applied to the anode and the moon of the device The change of positive bias voltage between pole, controls the device to be turned on the mode of operation of the BJT, or with the BJT and GTO The common mode of operation opened is turned on, including：

Step 1. adds positive bias voltage between the anode and negative electrode of the device so that the device is in forward blocking shape State；

Step 2. applies positive bias voltage and cut-in voltage of the forward bias voltage less than GTO between gate pole and negative electrode, described BJT opens mode of operation so that the device is turned on the mode of operation of the BJT；

Step 3. increases the positive bias voltage for causing the device anode and negative electrode two ends in the electric current for flowing through the device Cut-in voltage equal to or higher than GTO, the GTO opens mode of operation, and is worked simultaneously with the BJT.

8. control method according to claim 6, it is characterised in that methods described also includes：

Apply anti-bias voltage between the gate pole and negative electrode of the device, flow through the gate current of the device for negative current, So that the device shut-off.

9. a kind of preparation method of GTO structures as described in any one of claim 1 to 5, it is characterised in that the preparation method Including：

A novel power semiconductor is made, in existing gate turn off thyristor GTO or bipolar junction transistor BJT work( In rate semiconductor devices preparation process, overleaf the impurity opposite with current device back side doping type is injected in part to increase by a step Processing step, formed novel power semiconductor structure.

10. preparation method according to claim 9, it is characterised in that one modified GTO of BJT auxiliary of the making Structure, in existing gate turn off thyristor GTO or bipolar junction transistor BJT power semiconductor preparation process, increases Plus one the step overleaf part injection impurity opposite with current device back side doping type processing step, form what BJT was aided in Modified GTO structures, including：

Step A. pre-processes wafer, and multiple etching formation front description on the wafer after the pre-treatment；

Step B. carries out multiple ion implanting in wafer frontside, obtains gate pole contact window and terminal structure；

If step C. current semiconductors are BJT, the impurity opposite with original doping type is injected in the back portion of BJT, made Form GTO in original BJT structures；If current semiconductor is GTO, in the back portion injection of GTO and original doping class The opposite impurity of type so that form BJT in original GTO structures；

Step D. carries out annealing activation to the ion for injecting, and completes to sacrifice oxidation, metal contact process, surface passivation technology with And metal interconnection process, and form final metal electrode.