CN106847790A - The interconnection structure and its manufacture method of a kind of integrated CNT and Graphene - Google Patents

Abstract

The invention discloses an interconnection structure and a manufacturing method thereof. The structure includes at least one interconnection structure, the interconnection structure includes an interconnection medium layer, and the lower surface of the interconnection medium layer is embedded with a graphene interconnection layer. Carbon nanotube interconnection holes for connecting the upper surface of the interconnection medium layer with the graphene interconnection layer are arranged in the interconnection medium layer. The method comprises: preparing a graphene layer on a substrate or an interconnection medium layer in an interconnection structure below; forming the graphene layer into a graphene interconnection layer; depositing a catalyst on the graphene interconnection layer; Deposit an interconnect dielectric layer on the interconnect dielectric layer in the lower interconnect structure; prepare through holes in the interconnect dielectric layer; grow carbon nanotube arrays on the graphene interconnect layer; form carbon nanotube arrays into carbon nanotubes interconnect vias. The interconnection structure and manufacturing method of the present invention can solve the problems of traditional high resistance, limited current carrying capacity of the interconnection structure, and the like. The invention can be widely used in the field of manufacturing semiconductor devices.

Description

An interconnect structure integrating carbon nanotubes and graphene and its manufacturing method

technical field

The invention relates to the technical field of manufacturing semiconductor devices, in particular to an interconnection structure using carbon nanotubes as a vertical interconnection material and graphene as a horizontal interconnection material and a manufacturing method thereof.

Background technique

The continuous reduction of the feature size of the integrated circuit process makes the number of devices per unit area of the integrated circuit double every time a new technology node is reached. The reduction of the transistor feature size not only improves the integration of the chip, reduces the operating voltage and power consumption of the transistor, but also increases the operating frequency of the transistor. But at the same time, due to the increased electron scattering effect at the metal grain boundaries and surfaces, the resistance of interconnected metal layers based on materials such as copper and tungsten increases rapidly as the feature size shrinks, which in turn causes delays in electrical signal transmission increase, limiting the overall performance of the IC. On the other hand, interconnection vias and first-layer interconnection lines in direct contact with transistors will withstand relatively large current densities, and fracture failures caused by electromigration are prone to occur during long-term work. Therefore, there is a need to further improve the performance of the interconnect structure of integrated circuits to solve the problems of increased resistance and fracture failure faced by current interconnect materials and structures.

At present, in order to solve the above-mentioned problems, an interconnection structure based on carbon layers and carbon nanotube through-holes formed on the metal interconnection layer is proposed in the prior art. However, due to the application of the metal layer, the overall current carrying capacity of the interconnect structure is limited, so it cannot fundamentally solve the problem of large contact resistance, especially cannot improve the large current carrying capacity required by integrated circuits. In addition, for graphene, although it is a two-dimensional carbon-based nanomaterial, it has the advantages of high current carrying capacity, high carrier mobility and high thermal conductivity, but when it is used as a horizontal interconnect material and When the interconnection materials of metal structures are used together, they also have the problem of large contact resistance, and for the conductance of single-layer graphene, it is difficult to compare with metal materials, and the realization of its integration process is quite difficult. Therefore, graphite If olefin is used as an interconnect material to integrate with existing metal interconnect structures, it will also face the problems of high contact resistance and limited overall carrying current.

Contents of the invention

In order to solve the above technical problems, the object of the present invention is to provide an interconnection structure integrating carbon nanotubes and graphene.

Another object of the present invention is to provide a method for manufacturing an interconnection structure integrating carbon nanotubes and graphene.

The technical scheme adopted in the present invention is: an interconnection structure integrating carbon nanotubes and graphene, including at least one interconnection structure, the interconnection structure including an interconnection medium layer, the lower surface of the interconnection medium layer A graphene interconnection layer is embedded, and a carbon nanotube interconnection hole for connecting the upper surface of the interconnection medium layer with the graphene interconnection layer is arranged in the interconnection medium layer.

Further, the number of interconnection structures is at least two, and the at least two interconnection structures are stacked sequentially from bottom to top, wherein, among the two interconnection structures adjacent up and down, the interconnection structures below are arranged The carbon nanotube interconnection holes are used to communicate the graphene interconnection layer arranged in the lower interconnection structure with the graphene interconnection layer arranged in the upper interconnection structure.

Further, the graphene interconnection layer is multi-layer graphene.

Further, the thickness of the graphene interconnection layer is greater than or equal to 3 nm.

Further, the interconnection dielectric layer is made of a dielectric material with a low dielectric constant.

Another technical solution adopted in the present invention is: a method for manufacturing an interconnected structure integrating carbon nanotubes and graphene, the steps included in the method include:

S1. Prepare a graphene layer on the substrate or the interconnection dielectric layer in the underlying interconnection structure;

S2. A patterned graphene interconnection line or graphene channel is prepared on the graphene layer, thereby forming a graphene interconnection layer;

S3, depositing a catalyst on the through-hole connection position of the graphene interconnection layer;

S4. Depositing an interconnection medium layer on the substrate or the interconnection medium layer in the underlying interconnection structure, so that the graphene interconnection layer in step S3 is embedded and arranged on the lower surface of the interconnection medium layer;

S5. Prepare a through hole in the interconnection medium layer, and the through hole is correspondingly arranged on the through hole connection position of the graphene interconnection layer;

S6. Based on the deposited catalyst, grow a carbon nanotube array on the through-hole connection position of the graphene interconnection layer;

S7. Carry out a chemical mechanical polishing process after filling the carbon nanotube array with a medium, thereby forming carbon nanotube interconnection holes, wherein the carbon nanotube interconnection holes are used to interconnect the upper surface of the dielectric layer and the graphene Interconnect layer connectivity.

Further, the step of preparing a graphene layer on the substrate described in the step S1 is specifically:

The graphene layer is prepared on the substrate by adopting the method of chemical vapor deposition to synthesize graphene for transfer and the method of thermal annealing of the metal film.

Further, the step of preparing a graphene layer on the interconnection dielectric layer in the lower interconnection structure described in the step S1 is specifically:

A chemical vapor deposition method and a metal thin film thermal annealing method are used to prepare a graphene layer on the interconnection medium layer in the interconnection structure below.

Further, the step of growing a carbon nanotube array on the through-hole connection position of the graphene interconnection layer described in the step S6 is specifically:

A chemical vapor deposition method is used to grow a carbon nanotube array on the through-hole connection position of the graphene interconnection layer.

Further, the catalyst is at least one of Fe, Ni, Co, FeAl and NiAl.

The beneficial effects of the present invention are: the interconnection structure proposed by the present invention is an interconnection structure with graphene as the horizontal interconnection layer and carbon nanotubes as the vertical interconnection layer, which can make full use of carbon nanotubes and graphite Graphene has the advantages of high current carrying capacity, high electrical conductivity and high thermal conductivity. The problem of the limited current carrying capacity of the connection structure.

Another beneficial effect of the present invention is: by using the interconnect structure manufacturing method of the present invention, it is possible to manufacture an interconnect structure with graphene as the horizontal interconnect layer and carbon nanotubes as the vertical interconnect layer, which It can make full use of the advantages of high current carrying capacity, high electrical conductivity and high thermal conductivity of carbon nanotubes and graphene, and solve the unavoidable gap between carbon nanotubes or graphene materials and metal interconnection materials in the prior art. The problem of high resistance and limited current carrying capacity of the interconnect structure due to indirect contact; and because the manufacturing method of the present invention directly prepares carbon nanotubes on the graphene interconnect layer, the manufacturing method adopted makes the final obtained The metal catalyst material is completely removed from the interconnection structure, which can avoid the problem of high resistance at the junction due to the contact between the carbon-based material and the metal material; at the same time, for the carbon nanotube array, the manufacturing method adopted can directly form The close contact of carbon nanotubes and graphene eliminates the influence of the presence of metal on the interface. Therefore, it can be seen that the method for manufacturing the interconnection structure of integrated carbon nanotubes and graphene proposed by the present invention realizes the seamless connection of two carbon-based materials and enhances the bonding strength of the two materials at the contact point. Interconnect structures with high electrical and thermal conductivity can be obtained.

Description of drawings

Fig. 1 is a structural schematic diagram of a specific embodiment of an interconnect structure of integrated carbon nanotubes and graphene of the present invention;

Fig. 2 is a structural schematic diagram of another specific embodiment of an interconnection structure integrating carbon nanotubes and graphene of the present invention;

Fig. 3 is the structural representation shown after preparing the first graphene layer on the substrate;

Fig. 4 is the structural representation shown after the first graphene layer is prepared into the first graphene interconnection layer;

Fig. 5 is the structural representation shown after depositing catalyst on the first graphene interconnection layer;

Fig. 6 is a schematic structural view after preparing the first interconnect dielectric layer on the substrate;

FIG. 7 is a schematic structural view after preparing through holes in the first interconnection dielectric layer;

Fig. 8 is the structure schematic diagram shown after growing the carbon nanotube array on the through-hole connection position of the first graphene interconnection layer;

Fig. 9 is a schematic structural view after preparing the first carbon nanotube interconnection holes;

Fig. 10 is the structural representation shown after preparing the second graphene layer on the first interconnection medium layer;

Fig. 11 is the structural representation shown after the second graphene layer is prepared into the second graphene interconnection layer;

Fig. 12 is a schematic diagram of a transmission electron microscope photo of multilayer graphene prepared on a substrate;

Fig. 13 is the surface scanning electron microscope schematic diagram shown after preparing catalyst on multilayer graphene;

Fig. 14 is a schematic diagram of a cross-sectional scanning electron microscope photo after growing carbon nanotubes on multi-layer graphene.

detailed description

In order to solve the traditional problems of high resistance and limited current carrying capacity of interconnection structures due to the contact between carbon nanotubes or graphene materials and metal interconnection materials, the present invention proposes an interconnection of integrated carbon nanotubes and graphene structure, which includes at least one interconnection structure, the interconnection structure includes an interconnection medium layer, the lower surface of the interconnection medium layer is embedded with a graphene interconnection layer, and the interconnection medium layer is provided with a The upper surface of the interconnection medium layer communicates with the carbon nanotube interconnection hole of the graphene interconnection layer, that is, the carbon nanotube interconnection hole, one end communicates with the upper surface of the interconnection medium layer, and the other end communicates with the upper surface of the interconnection medium layer. The via connection positions of the graphene interconnect layer are connected.

For at least one interconnection structure of the present invention, when it is applied, it is arranged between the upper surface of the substrate and the lower surface of the top interconnection layer, and the carbon nanometers in the interconnection structure closest to the top interconnection layer Tube interconnection vias, which are then used to communicate the graphene interconnection layer in the interconnection structure with the top interconnection layer;

When the number of interconnection structures is one, the interconnection medium layer in the interconnection structure is arranged between the upper surface of the substrate and the lower surface of the top interconnection layer, that is, the upper surface of the interconnection structure is provided with the top interconnection layer , and the graphene interconnection layer in the interconnection structure is arranged on the upper surface of the substrate and embedded in the lower surface of the interconnection medium layer, and the carbon nanotube interconnection holes in the interconnection structure are arranged in In the interconnection medium layer, and one end thereof communicates with the via connection position of the top interconnection layer, and the other end communicates with the via connection position of the graphene interconnection layer;

When the number of interconnection structures is at least two, the at least two interconnection structures are stacked sequentially from bottom to top, and they are arranged between the upper surface of the substrate and the lower surface of the top interconnection layer, that is, the at least two interconnection structures Among the two interconnection structures, the top interconnection layer is provided on the upper surface of the uppermost interconnection structure, wherein, among the at least two interconnection structures, the upper and lower adjacent interconnection structures are arranged on the lower interconnection layer The carbon nanotube interconnection holes in the structure are used to connect the graphene interconnection layer arranged in the lower interconnection structure with the graphene interconnection layer arranged in the upper interconnection structure.

For the graphene interconnection layer in the above-mentioned at least one interconnection structure, it can be multi-layer graphene, and at this time, a graphene interconnection line is prepared on the graphene interconnection layer; preferably, the graphene interconnection The thickness of the layer is equal to or greater than 3 nm.

For the graphene interconnection layer in the interconnection structure closest to the substrate, in addition to being multi-layer graphene, it can also be a single-layer or few-layer graphene material constituting the transistor channel, and at this time, the most A graphene channel is prepared on the graphene interconnection layer in the interconnection structure close to the substrate, preferably, its thickness is a single layer or few layers.

The interconnection structure of the present invention will be specifically described below in combination with detailed embodiments.

Example 1

When the number of interconnection structures is 1, as shown in FIG. 1, an interconnection structure integrating carbon nanotubes and graphene includes an interconnection structure, and the interconnection structure is arranged on the upper surface and the top of the substrate 101 between the lower surfaces of the interconnection layer 110;

Specifically, the interconnection structure includes:

The first interconnection medium layer 103 is arranged between the upper surface of the substrate 101 and the lower surface of the top interconnection layer 110;

The first graphene interconnection layer 102 is arranged on the upper surface of the substrate 101 and embedded in the lower surface of the first interconnection medium layer 103;

The first carbon nanotube interconnection hole 104 is embedded in the first interconnection medium layer 103, and one end thereof is connected to the through hole connection position of the first graphene interconnection layer 102, and the other end passes through the first interconnection The dielectric layer 103 is thus connected to the via connection position of the top interconnection layer 110, that is, at this time, the first carbon nanotube interconnection via hole 104 interconnects the upper surface of the first interconnection dielectric layer 103 with the first graphene. The connecting layer 102 is connected. Wherein, the top interconnection layer 110 is essentially a graphene interconnection layer, that is, the top graphene interconnection layer.

As a preferred implementation of this embodiment, the first graphene interconnection layer 102 and the top interconnection layer 110 are multilayer graphene, and at this time, the first graphene interconnection layer 102 and the top interconnection layer Graphene interconnection lines are prepared on 110; preferably, the thickness of the first graphene interconnection layer 102 and the top interconnection layer 110 is greater than or equal to 3 nm.

For the above-mentioned first graphene interconnection layer 102, in addition to multi-layer graphene, it can also be a single-layer or few-layer graphene material forming a transistor channel, and at this time, the first graphene A graphene channel is prepared on the interconnection layer 102, preferably, its thickness is a single layer or few layers.

As a preferred implementation of this embodiment, the first interconnection dielectric layer 103 is made of a dielectric material with a low dielectric constant, wherein the dielectric material with a low dielectric constant includes but is not limited to a porous dielectric material, Dielectric materials containing partial air gaps, etc.

Example 2

When the number of interconnection structures is two, as shown in Figure 2, an interconnection structure integrating carbon nanotubes and graphene includes a first interconnection structure and a second interconnection structure, the substrate 101, the second interconnection structure An interconnection structure, a second interconnection structure, and a top interconnection layer 110 are stacked sequentially from bottom to top, wherein the first interconnection structure includes a first graphene interconnection layer 102, a first interconnection dielectric layer 103 and The first carbon nanotube interconnection hole 104, the second interconnection structure includes a second graphene interconnection layer 105, a second interconnection medium layer 106 and a second carbon nanotube interconnection hole 107;

The first interconnection medium layer 103 is arranged between the upper surface of the substrate 101 and the lower surface of the second interconnection medium layer 106;

The first graphene interconnection layer 102 is arranged on the upper surface of the substrate 101 and embedded in the lower surface of the first interconnection medium layer 103;

The first carbon nanotube interconnection hole 104 is embedded in the first interconnection medium layer 103, and one end thereof is connected to the through hole connection position of the first graphene interconnection layer 102, and the other end passes through the first interconnection The dielectric layer 103 is thus connected to the via connection position of the second graphene interconnection layer 105, that is, at this time, the first carbon nanotube interconnection via hole 104 connects the upper surface of the first interconnection dielectric layer 103 to the first The graphene interconnect layer 102 is connected;

The second interconnection medium layer 106 is arranged between the upper surface of the first interconnection medium layer 103 and the lower surface of the top interconnection layer 110;

The second graphene interconnection layer 105 is arranged on the upper surface of the first interconnection medium layer 103 and embedded in the lower surface of the second interconnection medium layer 106;

The second carbon nanotube interconnection hole 107 is embedded in the second interconnection medium layer 106, and its one end is connected to the through hole connection position of the second graphene interconnection layer 105, and its other end passes through the second interconnection The dielectric layer 106 is thus connected to the via connection position of the top interconnection layer 110, that is, at this time, the second carbon nanotube interconnection via hole 107 interconnects the upper surface of the second interconnection dielectric layer 106 with the second graphene. The connecting layer 105 is connected. Wherein, the top interconnection layer 110 is essentially a graphene interconnection layer, that is, the top graphene interconnection layer.

As a preferred implementation of this embodiment, the first graphene interconnection layer 102, the second graphene interconnection layer 105, and the top interconnection layer 110 are all multilayer graphene, and at this time, the first graphene interconnection layer Graphene interconnection layer 102, the second graphene interconnection layer 105, and the top interconnection layer 110 are all prepared with graphene interconnection lines, preferably, the first graphene interconnection layer 102, the second graphene interconnection layer The thicknesses of the layer 105 and the top interconnection layer 110 are both greater than or equal to 3 nm.

For the above-mentioned first graphene interconnection layer 102, in addition to multi-layer graphene, it can also be a single-layer or few-layer graphene material forming a transistor channel, and at this time, the first graphene A graphene channel is prepared on the interconnection layer 102, preferably, its thickness is a single layer or few layers.

As a preferred implementation of this embodiment, the first interconnection dielectric layer 103 and the second interconnection dielectric layer 106 are made of a dielectric material with a low dielectric constant, wherein the dielectric material with a low dielectric constant Including but not limited to porous dielectric materials, dielectric materials containing some air gaps, etc.

It can be seen from Embodiment 2 that when the number of interconnection structures is greater than 2, the configuration of the structures can be analogously as above.

Example 3

For the manufacturing method of the interconnection structure described in the above-mentioned embodiment 1, it specifically includes:

S101, as shown in FIG. 3 , prepare a first graphene layer 201 on a substrate 101, wherein the substrate 101 can be made of semiconductor material silicon, silicon germanium, a silicon substrate on an insulating layer, etc., and can also include a compound Semiconductor materials, such as III-V, II-VI, silicon carbide and other materials, and new two-dimensional semiconductor materials, such as graphene, molybdenum disulfide, tungsten diselenide, black phosphorus and other materials;

For the above step S101, it can adopt the method of chemical vapor deposition to synthesize graphene for transfer and the method of thermal annealing of the metal film, so as to prepare the first graphene layer 201 on the substrate 101;

In this embodiment, the step S101 is specifically:

Deposit a layer of metallic nickel on an additional substrate by sputtering or evaporation, with a thickness between 50 nm and 500 nm; then put the substrate into a plasma vapor deposition equipment, and raise the temperature under the protection of a hydrogen atmosphere To 900 degrees Celsius, then apply an additional power of 200W to excite the plasma, and pass in a gas source containing carbon elements such as methane, and keep the gas passing time generally between 10 seconds and 5 minutes according to the thickness; finally turn off the carbon-containing gas source, applied power and heating power, the substrate temperature is rapidly dropped to room temperature, so that multi-layer graphene with a thickness of more than 3nm can be prepared; Put the bottom into a solution such as dilute nitric acid to etch away the nickel metal layer, so that the graphene layer floating on the surface of the solution can be transferred to the target substrate 101 to remove the mechanical support layer; then the sample is cleaned multiple times or subjected to a high temperature of 300 degrees Celsius Lower annealing, used to improve the quality of graphene;

In addition, for the above-mentioned process used to prepare the first graphene layer 201 on the substrate 101, single-layer or few-layer graphene can also be prepared on the substrate 101 through the adjustment of its preparation parameters;

S102, as shown in FIG. 4 , through process steps such as photolithography and etching, patterned graphene interconnect lines or graphene channels are prepared on the first graphene layer 201, thereby forming a first graphene interconnect Layer 102;

For the described step S102, it specifically includes: manufacturing a mask plate according to the specific shape of the required wire, and coating photoresist on the graphene layer; A series of steps, covering the required graphene layer with photoresist; performing dry etching with plasma, and removing the photoresist to obtain the first graphene interconnection layer 102; wherein, using plasma to first The graphene layer is subjected to dry etching, that is, the etching of graphene adopts a dry plasma etching method, and the gas used in this process can be oxygen, argon, hydrogen, nitrogen, hydrocarbons or fluorocarbons, It can also be a mixture of the above gases, and photoresist is used as a mask in lithography, which can facilitate removal after etching. In addition, it can also use photoresist in combination with other hard masks (such as metal, silicon nitride, etc.) and other materials) to realize the mask;

S103, as shown in FIG. 5 , deposit a catalyst 401 on the through-hole connection position of the first graphene interconnection layer 102, wherein, for the catalyst 401, its formation position needs to correspond to the first carbon formed in the subsequent step The positions of the interconnected holes 104 of nanotubes, and the catalyst 401 can be Fe, Ni, Co, FeAl, NiAl, etc., and can also be the superposition of the above materials; in addition, the preparation of the catalyst 401 can adopt vacuum evaporation or sputtering method, the thickness of the prepared catalyst 401 is between 0.5 nm and 10 nm;

S104, as shown in FIG. 6, depositing a first interconnection dielectric layer 103 on the substrate 101, so that the first graphene interconnection layer 102 in step S3 is embedded in the lower surface of the first interconnection dielectric layer 103;

Wherein, the first interconnection dielectric layer 103 may be a dielectric material with a low dielectric constant, and the dielectric material with a low dielectric constant includes but is not limited to a porous dielectric material, a dielectric material containing some air gaps, etc.; the first An interconnect dielectric layer 103 can be prepared by vapor deposition, sputtering, etc., and the thickness of the prepared first interconnect dielectric layer 103 is usually between 200 nm and 2 μm, and it can also be outside this range. Meet special application requirements;

S105. As shown in FIG. 7, through photolithography and etching and other process steps, through holes are prepared in the first interconnect dielectric layer 103, and the through holes are correspondingly arranged at the through hole connection positions of the first graphene interconnect layer , wherein the position of the through hole prepared in the first interconnect dielectric layer 103 corresponds to the position where the catalyst 401 is deposited as shown in FIG. 5 ;

For the step S105, that is, the manufacturing process of forming the through hole, it is specifically:

After coating the photoresist on the first interconnect dielectric layer 103, carry out photolithography, exposure, and development, and the pattern of the mask plate used is used to obtain the dielectric layer at the leaking through hole after development; then adopt dry method Plasma etching to form through holes;

Since it is necessary to ensure that the metal catalyst is not etched after dry plasma etching, in this embodiment, the etching process adopted is: set the inductively coupled plasma power to 935 W, and the reactive plasma power to 100 W, the gas is set to 10 sccm of fluorocarbon and 8 sccm of hydrogen, and 174 sccm of helium is used for backside cooling; this process parameter has a high etching selectivity ratio for metal materials, and combines the detection of the etching end point technology so that the metal catalyst remains after the etch is complete;

S106, as shown in FIG. 8 , based on the deposited catalyst 401, a chemical vapor deposition method is used to directly grow a carbon nanotube 701 array on the through-hole connection position of the first graphene interconnection layer 102, wherein the Chemical vapor deposition methods include plasma chemical vapor deposition methods, thermal chemical vapor deposition methods, microwave plasma chemical vapor deposition methods, etc. When plasma chemical vapor deposition methods are used, the growth temperature can be from 350 degrees Celsius to 850 degrees Celsius;

In this embodiment, the gas and the ratio used in the chemical vapor deposition method are methane 30sccm: nitrogen 35sccm: hydrogen 40sccm, the growth time is 1 minute, and the growth temperature is 650 degrees centigrade; after the growth is completed, methane and nitrogen are turned off. Down to room temperature in a hydrogen atmosphere; as shown in Figure 8, the catalyst particle 702 is located at the top of the carbon nanotube 701 during the growth process, and the root of the carbon nanotube 701 is directly connected with the first graphene interconnect layer 102; growth The lengths of the final carbon nanotubes 701 are not completely consistent, and the length of most of the carbon nanotubes 701 should be higher than the thickness of the first interconnection medium layer 103 by controlling the growth time;

S107. As shown in FIG. 9 , perform a chemical mechanical polishing process after filling the carbon nanotube array 701 with a medium, thereby forming a first carbon nanotube interconnection hole 104, wherein the first carbon nanotube interconnection hole 104 is used for the upper surface of the first interconnect dielectric layer 103 to communicate with the first graphene interconnect layer 102;

Among them, the filled medium can be silicon dioxide, silicon nitride and aluminum oxide, etc., and the medium filling method can be atomic layer deposition technology, chemical vapor deposition or physical vapor deposition technology, etc.; , the thickness of the filling medium needs to be set according to the spacing of the carbon nanotubes. Usually, the thickness of the filling medium is in the range of 10 nm to 50 nm. A carbon nanotube part, forming a first carbon nanotube interconnection hole 104;

S108. As shown in FIG. 10, prepare a second graphene layer 901 on the first interconnect dielectric layer 103. In this embodiment, the second graphene layer 901 is substantially the top graphene layer, which is equivalent to the first interconnection Prepare a top graphene layer on the dielectric layer 103 and the first carbon nanotube interconnection hole 104;

For step S108, the second graphene layer 901 is formed on the first interconnection medium layer 103 in the manner of direct growth by using chemical vapor deposition method and thermal annealing method of metal film, which is interconnected with the first carbon nanotubes The through hole 104 is directly connected;

In this embodiment, the preparation steps of the second graphene layer 901 specifically include: depositing a layer of metal Ni on the first interconnect dielectric layer 103 with a thickness of 50 nm to 500 nm; then preparing carbon source materials, Perform the steps of depositing a layer of carbon layer, depositing a diamond-like film, and ion-implanting carbon materials; then thermally annealing metal Ni in a protective gas at a temperature of 600 degrees Celsius to 1000 degrees Celsius; then use dilute nitric acid and other solutions to remove The upper layer of metal Ni, a multilayer second graphene layer 901 is grown at the interface between Ni and the first interconnection dielectric layer 103;

S109, through process steps such as photolithography and etching, a patterned graphene interconnection layer is prepared on the second graphene layer 901, thereby forming the top interconnection layer 110. At this time, the first carbon nanotubes are interconnected The hole 104 communicates the first graphene interconnection layer 102 with the top interconnection layer 110; for the preparation process of the top interconnection layer 110 in step S109, it is the same as the preparation process of the first graphene interconnection layer 102 in step S102 ;

Through the above-mentioned manufacturing steps, the interconnection structure finally prepared is shown in FIG. 1 .

Example 4

For the manufacturing method of the interconnection structure described in the above-mentioned embodiment 2, it specifically includes:

S201, as shown in FIG. 3 , prepare a first graphene layer 201 on a substrate 101, wherein the substrate 101 can be made of semiconductor material silicon, silicon germanium, a silicon substrate on an insulating layer, etc., and can also include a compound Semiconductor materials, such as III-V, II-VI, silicon carbide and other materials, and new two-dimensional semiconductor materials, such as graphene, molybdenum disulfide, tungsten diselenide, black phosphorus and other materials;

For the above step S201, it can adopt the method of chemical vapor deposition to synthesize graphene for transfer and the method of thermal annealing of the metal film, so as to prepare the first graphene layer 201 on the substrate 101;

In this embodiment, the step S201 is specifically:

Deposit a layer of metallic nickel on an additional substrate by sputtering or evaporation, with a thickness between 50 nm and 500 nm; then put the substrate into a plasma vapor deposition equipment, and raise the temperature under the protection of a hydrogen atmosphere To 900 degrees Celsius, then apply an additional power of 200W to excite the plasma, and pass in a gas source containing carbon elements such as methane, and keep the gas passing time generally between 10 seconds and 5 minutes according to the thickness; finally turn off the carbon-containing gas source, applied power and heating power, the substrate temperature is rapidly dropped to room temperature, so that multi-layer graphene with a thickness of more than 3nm can be prepared; Put the bottom into a solution such as dilute nitric acid to etch away the nickel metal layer, so that the graphene layer floating on the surface of the solution can be transferred to the target substrate 101 to remove the mechanical support layer; then the sample is cleaned multiple times or subjected to a high temperature of 300 degrees Celsius Lower annealing, used to improve the quality of graphene;

In addition, for the above-mentioned process used to prepare the first graphene layer 201 on the substrate 101, single-layer or few-layer graphene can also be prepared on the substrate 101 through the adjustment of its preparation parameters;

S202, as shown in FIG. 4 , through process steps such as photolithography and etching, patterned graphene interconnect lines and graphene channels are prepared on the first graphene layer 201, thereby forming a first graphene interconnect Layer 102;

For the described step S202, it specifically includes: manufacturing a mask plate according to the specific shape of the required wire, and coating photoresist on the graphene layer; A series of steps, covering the required graphene layer with photoresist; performing dry etching with plasma, and removing the photoresist to obtain the first graphene interconnection layer 102; wherein, using plasma to first The graphene layer is subjected to dry etching, that is, the etching of graphene adopts a dry plasma etching method, and the gas used in this process can be oxygen, argon, hydrogen, nitrogen, hydrocarbons or fluorocarbons, It can also be a mixture of the above gases, and photoresist is used as a mask in lithography, which can facilitate removal after etching. In addition, it can also use photoresist in combination with other hard masks (such as metal, silicon nitride, etc.) and other materials) to realize the mask;

S203, as shown in FIG. 5, deposit a catalyst 401 on the connection position of the through hole of the first graphene interconnection layer 102, wherein, for the catalyst 401, its formation position needs to correspond to the first carbon formed in the subsequent step The positions of the interconnected holes 104 of the nanotubes, and the catalyst 401 can be Fe, Ni, Co, FeAl, NiAl, etc., and can also be the superposition of the above materials; in addition, the preparation of the catalyst 401 can adopt vacuum evaporation or sputtering, the thickness of the prepared catalyst 401 is between 0.5 nm and 10 nm;

S204, as shown in FIG. 6, depositing a first interconnection dielectric layer 103 on the substrate 101, so that the first graphene interconnection layer 102 in step S3 is embedded in the lower surface of the first interconnection dielectric layer 103;

Wherein, the first interconnection dielectric layer 103 may be a dielectric material with a low dielectric constant, and the dielectric material with a low dielectric constant includes but is not limited to a porous dielectric material, a dielectric material containing some air gaps, etc.; the first An interconnect dielectric layer 103 can be prepared by vapor deposition, sputtering, etc., and the thickness of the prepared first interconnect dielectric layer 103 is usually between 200 nm and 2 μm, and it can also be outside this range. Meet special application requirements;

S205, as shown in FIG. 7, through photolithography and etching and other process steps, through holes are prepared in the first interconnect dielectric layer 103, and the through holes are correspondingly arranged at the through hole connection positions of the first graphene interconnect layer , wherein the position of the through hole prepared in the first interconnect dielectric layer 103 corresponds to the position where the catalyst 401 is deposited as shown in FIG. 5 ;

For the step S205, that is, the manufacturing process of forming the through hole, it is specifically:

After coating the photoresist on the first interconnect dielectric layer 103, carry out photolithography, exposure, and development, and the pattern of the mask plate used is used to obtain the dielectric layer at the leaking through hole after development; then adopt dry method Plasma etching to form through holes;

Since it is necessary to ensure that the metal catalyst is not etched after dry plasma etching, in this embodiment, the etching process adopted is: set the inductively coupled plasma power to 935 W, and the reactive plasma power to 100 W, the gas is set to 10 sccm of fluorocarbon and 8 sccm of hydrogen, and 174 sccm of helium is used for backside cooling; this process parameter has a high etching selectivity ratio for metal materials, and combines the detection of the etching end point technology so that the metal catalyst remains after the etch is complete;

S206, as shown in FIG. 8, based on the deposited catalyst 401, the carbon nanotube 701 array is directly grown on the through-hole connection position of the first graphene interconnection layer 102 by using a chemical vapor deposition method, wherein the Chemical vapor deposition methods include plasma chemical vapor deposition methods, thermal chemical vapor deposition methods, microwave plasma chemical vapor deposition methods, etc. When plasma chemical vapor deposition methods are used, the growth temperature can be from 350 degrees Celsius to 850 degrees Celsius;

In this embodiment, the gas and the ratio used in the chemical vapor deposition method are methane 30sccm: nitrogen 35sccm: hydrogen 40sccm, the growth time is 1 minute, and the growth temperature is 650 degrees centigrade; after the growth is completed, methane and nitrogen are turned off. Down to room temperature in a hydrogen atmosphere; as shown in Figure 8, the catalyst particle 702 is located at the top of the carbon nanotube 701 during the growth process, and the root of the carbon nanotube 701 is directly connected with the first graphene interconnect layer 102; growth The lengths of the final carbon nanotubes 701 are not completely consistent, and the length of most of the carbon nanotubes 701 should be higher than the thickness of the first interconnection medium layer 103 by controlling the growth time;

S207. As shown in FIG. 9 , perform a chemical mechanical polishing process after filling the carbon nanotube array 701 with a medium, thereby forming a first carbon nanotube interconnection hole 104, wherein the first carbon nanotube interconnection hole 104 is used for the upper surface of the first interconnect dielectric layer 103 to communicate with the first graphene interconnect layer 102;

Among them, the filled medium can be silicon dioxide, silicon nitride and aluminum oxide, etc., and the medium filling method can be atomic layer deposition technology, chemical vapor deposition or physical vapor deposition technology, etc.; , the thickness of the filling medium needs to be set according to the spacing of the carbon nanotubes. Usually, the thickness of the filling medium is in the range of 10 nm to 50 nm. A carbon nanotube part, forming a first carbon nanotube interconnection hole 104;

S208. As shown in FIG. 10 , prepare a second graphene layer 901 on the first interconnection dielectric layer 103. In this embodiment, the second graphene layer 901 is essentially used to prepare the second graphene layer in the second interconnection structure. The graphene interconnection layer 105 is equivalent to preparing the second graphene layer 901 on the first interconnection dielectric layer 103 and the first carbon nanotube interconnection holes 104;

For step S208, the second graphene layer 901 is formed on the first interconnect dielectric layer 103 in a direct growth manner by using chemical vapor deposition and thermal annealing of the metal film, which is interconnected with the first carbon nanotubes The through hole 104 is directly connected;

In this embodiment, the preparation steps of the second graphene layer 901 specifically include: depositing a layer of metal Ni on the first interconnect dielectric layer 103 with a thickness of 50 nm to 500 nm; then preparing carbon source materials, Perform the steps of depositing a layer of carbon layer, depositing a diamond-like film, and ion-implanting carbon materials; then thermally annealing metal Ni in a protective gas at a temperature of 600 degrees Celsius to 1000 degrees Celsius; then use dilute nitric acid and other solutions to remove The upper layer of metal Ni, a multi-layer second graphene layer 901 is grown at the interface between Ni and the first interconnection dielectric layer 103;

S209, as shown in FIG. 11, through process steps such as photolithography and etching, a patterned graphene interconnect layer is prepared on the second graphene layer 901, thereby forming a second graphene interconnect layer 105, at this time , the first carbon nanotube interconnection hole 104 communicates with the first graphene interconnection layer 102 and the second graphene interconnection layer 105; for the preparation process of the second graphene interconnection layer 105 in step S209, it and The preparation process of the first graphene interconnection layer 102 in step S202 is the same;

S210, using the preparation process from step S203 to step S207 to realize the preparation of the second interconnection medium layer 106 and the second carbon nanotube interconnection via holes 107;

S211, using the graphene layer preparation process in step S208 to realize the preparation of the third graphene layer on the second interconnect dielectric layer 106, at this time, the third graphene layer is the top graphene layer, and then, using The graphene interconnection layer preparation process of step S209 is to realize that the top graphene layer is prepared into the top interconnection layer 110;

Through the above-mentioned manufacturing steps, the interconnection structure finally prepared is shown in FIG. 2 .

From the steps of the interconnection structure manufacturing method in the above-mentioned embodiment 4, when the number of interconnection structures is greater than 2, the steps are repeated after the first interconnection structure is prepared and before the top interconnection layer 110 is prepared. In the preparation process of S208~210, it is only necessary to form an interconnection structure with a corresponding number of layers.

Example 5

When adopting the manufacturing method of the present invention to prepare multilayer graphene on the substrate, and the substrate material is an oxide layer substrate on silicon, the prepared multilayer graphene on the substrate, its transmission electron microscope photo is as follows Figure 12 shows. Wherein, the reference numeral 111 in the figure indicates an oxide layer substrate on silicon, and the reference numeral 112 indicates multi-layer graphene.

Example 6

When a 2nm Fe catalyst is prepared by sputtering on multi-layer graphene using the manufacturing method of the present invention, and then subjected to high-temperature annealing in a chemical vapor deposition device, the surface scanning electron microscope image is shown in FIG. 13 . It can be seen in Fig. 13 that after high temperature annealing, the deposited Fe film forms nanoparticles, which can be used for the growth of carbon nanotubes in the subsequent steps.

Example 7

Figure 14 shows a cross-sectional SEM picture of carbon nanotubes grown directly on multilayer graphene. Among them, the growth uses Fe catalyst 2 nm, the growth temperature is 700 degrees Celsius, and the growth time is 3 minutes, and the carbon nanotubes grown by this specific method have good vertical orientation, which can meet the requirements of carbon nanotube interconnection holes. In addition, since the catalyst particles are located on top of the carbon nanotubes after growth and can be removed in subsequent polishing steps, the influence of metal materials is completely removed at the interface between the interconnect dielectric layers in the final fabricated interconnect structure , realizing the seamless connection of carbon nanotubes and graphene.

The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. , these equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (10)

1. An interconnection structure integrating carbon nanotubes and graphene, characterized in that: comprise at least one interconnection structure, the interconnection structure comprises an interconnection medium layer, and the lower surface of the interconnection medium layer is embedded with In the graphene interconnection layer, the interconnection medium layer is provided with carbon nanotube interconnection holes for connecting the upper surface of the interconnection medium layer with the graphene interconnection layer. 2. An interconnection structure integrating carbon nanotubes and graphene according to claim 1, characterized in that: the number of the interconnection structures is at least two, and the at least two interconnection structures are from bottom to top The stacking is arranged successively, wherein, in the two interconnection structures adjacent up and down, the carbon nanotube interconnection holes arranged in the lower interconnection structure are used to connect the graphene interconnection layer arranged in the lower interconnection structure with the set The graphene interconnect layers in the upper interconnect structure are connected. 3. An interconnection structure integrating carbon nanotubes and graphene according to claim 1 or 2, characterized in that: the graphene interconnection layer is multi-layer graphene. 4. An interconnection structure integrating carbon nanotubes and graphene according to claim 3, characterized in that: the thickness of the graphene interconnection layer is greater than or equal to 3 nm. 5. An interconnection structure integrating carbon nanotubes and graphene according to claim 1 or 2, characterized in that: the interconnection dielectric layer is made of a dielectric material with a low dielectric constant. 6. A method for manufacturing an interconnected structure of integrated carbon nanotubes and graphene, characterized in that: the method includes the steps of: S1. Prepare a graphene layer on the substrate or the interconnection dielectric layer in the underlying interconnection structure; S2. A patterned graphene interconnection line or graphene channel is prepared on the graphene layer, thereby forming a graphene interconnection layer; S3, depositing a catalyst on the through-hole connection position of the graphene interconnection layer; S4. Depositing an interconnection medium layer on the substrate or the interconnection medium layer in the underlying interconnection structure, so that the graphene interconnection layer in step S3 is embedded and arranged on the lower surface of the interconnection medium layer; S5. Prepare a through hole in the interconnection medium layer, and the through hole is correspondingly arranged on the through hole connection position of the graphene interconnection layer; S6. Based on the deposited catalyst, grow a carbon nanotube array on the through-hole connection position of the graphene interconnection layer; S7. Carry out a chemical mechanical polishing process after filling the carbon nanotube array with a medium, thereby forming carbon nanotube interconnection holes, wherein the carbon nanotube interconnection holes are used to interconnect the upper surface of the dielectric layer and the graphene Interconnect layer connectivity. 7. According to claim 6, a method for manufacturing an interconnected structure of integrated carbon nanotubes and graphene, characterized in that: the step of preparing a graphene layer on the substrate described in the step S1, its specific for: The graphene layer is prepared on the substrate by adopting the method of chemical vapor deposition to synthesize graphene for transfer and the method of thermal annealing of the metal film. 8. A method for manufacturing an interconnection structure integrating carbon nanotubes and graphene according to claim 6, characterized in that: graphite is prepared on the interconnection medium layer in the interconnection structure below as described in the step S1 The step of the vinyl layer is specifically: A chemical vapor deposition method and a metal thin film thermal annealing method are used to prepare a graphene layer on the interconnection medium layer in the interconnection structure below. 9. According to any one of claims 6-8, a method for manufacturing an interconnection structure integrating carbon nanotubes and graphene, characterized in that: the through-hole connection in the graphene interconnection layer described in step S6 The step of growing the carbon nanotube array on the position is specifically: A chemical vapor deposition method is used to grow a carbon nanotube array on the through-hole connection position of the graphene interconnection layer. 10. A method for manufacturing an interconnected structure of integrated carbon nanotubes and graphene according to any one of claims 6-8, characterized in that: the catalyst is at least one of Fe, Ni, Co, FeAl, NiAl .