CN106843051B - A kind of FPGA time-delay mechanism and method - Google Patents
A kind of FPGA time-delay mechanism and method Download PDFInfo
- Publication number
- CN106843051B CN106843051B CN201710088359.2A CN201710088359A CN106843051B CN 106843051 B CN106843051 B CN 106843051B CN 201710088359 A CN201710088359 A CN 201710088359A CN 106843051 B CN106843051 B CN 106843051B
- Authority
- CN
- China
- Prior art keywords
- time
- signal
- delay
- module
- interval
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000007246 mechanism Effects 0.000 title claims abstract description 25
- 238000005259 measurement Methods 0.000 claims abstract description 28
- 230000003111 delayed effect Effects 0.000 claims abstract description 17
- 230000000737 periodic effect Effects 0.000 claims abstract description 9
- 230000001934 delay Effects 0.000 claims description 14
- 238000004364 calculation method Methods 0.000 claims description 13
- 230000008859 change Effects 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 230000002123 temporal effect Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Abstract
This application discloses a kind of FPGA time-delay mechanism and methods, are related to signal processing technology field, can improve the precision of the precision of delay time and the time interval of measurement while keeping lower cost and lower hardware complexity.The time-delay mechanism of the application includes delay adjustment module and measurement module, wherein delay adjustment module according to delay time for delaying or the first signal in advance；Measurement module is connect with delay adjustment module, measurement module is for determining specified time interval, it is divided between specified time through the moment where delay adjustment module the first signal adjusted, with in second signal correspond to adjustment after the first signal period initial time between time interval, second signal is periodic signal.The application is suitable for time delayed signal.
Description
Technical field
This application involves field of signal processing more particularly to a kind of FPGA time-delay mechanism and methods.
Background technique
In the fields such as quantum communications, Fibre Optical Sensor, satellite positioning, laser ranging, time of measuring interval and delay all have
There is universal application.It, can when the time interval difference needed for measuring time interval and the user between obtained multiple signals
With by delay adjustment signal between time interval, time interval needed for making time interval adjusted meet user, it
The time interval (i.e. specified time interval) between multiple signals adjusted is measured, again afterwards in order to multiple letters adjusted
It number is monitored.For example, user's desired signal receiving end receives the first signal after first receiving second signal again, and receive second
Have certain time interval (i.e. the time required to interval) at the time of signal and at the time of receiving the first signal, but in fact, due to
The problems such as signal transmits, may cause signal receiving end and first receives the first signal and receive second signal (i.e. two signals again
Phase position change), alternatively, receive second signal at the time of and receive the first signal at the time of time interval be not inconsistent
Interval, at this moment just needs to be adjusted the first signal, such as change the relative position of two signals the time required to closing
The case where change, can be such that the first signal delays or certain time in advance, so that the relative position of two signals and time interval are equal
Meet needed for user.
The prior art provides a kind of method being delayed by increasing the cable line length of transmission signal.According to big
It causes delay time to select the cable of different length, keeps transmission time of the unlike signal in transmission process different, to make more
There are certain time intervals between a signal.Although transmission time of the signal on unit length cable is fixed value,
User can only select a root long degree to be closer to the cable of required length when realizing delay in existing cable, and
Have no idea the cable that different length is chosen according to different delay requirement, result in this way the length of the cable of selection with
There are errors between required cable length, are delayed when using the cable of selection, can make needed for delay time and user
Delay time it is not identical, also result in the precision of delay time lower；When delay time is longer, need using longer electricity
Cable increases the interference that signal is subject in transmission process, so that signal quality declines, the fluctuation of signal is reinforced, so that
The leading edge position of signal is shaken, due to needing the position of rising edge of basis signal to come time of measuring interval, then signal
Rising edge position change after, the precision of the time interval measured reduces.
In order to solve the problems, such as that delay time precision is lower, the prior art additionally provides a kind of utilization high-precision delay chip
Come the method being delayed.High-precision delay chip is accessed between the signal sending end and signal receiving end of each signal, by matching
High-precision delay chip is set to be delayed.Although can be improved the precision of delay time in this way, add additional multiple high
Precision delay chip, so that increasing cost while increasing hardware complexity.
Summary of the invention
The application provides a kind of FPGA time-delay mechanism and method, can keep lower cost and lower hardware complexity
Meanwhile improving the precision of the precision of delay time and the time interval of measurement.
In order to achieve the above objectives, the application adopts the following technical scheme that
In a first aspect, the application provides a kind of FPGA time-delay mechanism, the FPGA time-delay mechanism includes delay adjustment module
And measurement module, wherein
Delay adjustment module according to delay time for delaying or the first signal in advance；
The measurement module is connect with delay adjustment module, and the measurement module is used to determine specified time interval,
It is divided between the specified time through the moment where delay adjustment module the first signal adjusted, it is corresponding with second signal
Time interval between the initial time in the period of the first signal adjusted, second signal are periodic signal.
Second aspect, the application provide a kind of FPGA time-delay method, and the FPGA time-delay method includes:
It is delayed according to delay time or the first signal in advance；
It determines specified time interval, the moment where the first signal adjusted is divided between the specified time, with the second letter
Corresponding to the time interval between the initial time in the period of the first signal adjusted in number, second signal is periodic signal.
The application provides a kind of FPGA (Field-Programmable Gate Array, field-programmable gate array) and prolongs
When device and method, the delay time of multiple signals can be controlled in FPGA, and measure specified between the signal after delay
Time interval since the precision of FPGA control delay time is higher, and will not generate interference to signal, and signal quality will not occur
Change, accurate measured value can be obtained when carrying out specified time interval measurement in this way, compared with using cable, improves
The precision of delay time, and improve the precision of the time interval of measurement；Due to passing through a FPGA delay adjustment module, energy
The delay of all signals is enough controlled, therefore, can only increase a delay in existing apparatus and adjust module, be delayed with high-precision
Chip is compared, and is reduced hardware complexity, is reduced costs simultaneously.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is a kind of structural schematic diagram of FPGA time-delay mechanism provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another kind FPGA time-delay mechanism provided in an embodiment of the present invention；
Fig. 3 is a kind of schematic illustration of FPGA time-delay mechanism provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of another kind FPGA time-delay mechanism provided in an embodiment of the present invention；
Fig. 5 is the schematic illustration of another kind FPGA time-delay mechanism provided in an embodiment of the present invention；
Fig. 6 is the schematic illustration of another kind FPGA time-delay mechanism provided in an embodiment of the present invention；
Fig. 7 is the structural schematic diagram of another kind FPGA time-delay mechanism provided in an embodiment of the present invention；
Fig. 8 is a kind of flow chart of FPGA time-delay method provided in an embodiment of the present invention；
Fig. 9 is the flow chart of another kind FPGA time-delay method provided in an embodiment of the present invention；
Figure 10 is the flow chart of another kind FPGA time-delay method provided in an embodiment of the present invention；
Figure 11 is the flow chart of another kind FPGA time-delay method provided in an embodiment of the present invention；
Figure 12 is the flow chart of another kind FPGA time-delay method provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts all other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of FPGA time-delay mechanism 10, as shown in Figure 1, the FPGA time-delay mechanism 10 includes delay
Adjust module 11 and measurement module 12, wherein
Delay adjustment module 11 according to delay time for delaying or the first signal in advance.
Measurement module 12 is connect with delay adjustment module 11, and measurement module 12 is for determining specified time interval.
Wherein, the is divided into after adjustment in moment, with second signal where the first signal after corresponding to adjustment between specified time
Time interval between the initial time in the period of one signal, second signal are periodic signal.
It should be noted that after adjustment the moment where the first signal compared to the moment where the first signal, may delay or
In advance, it delays or corresponding delay time may be different in advance.For example, in a period of time, there are moment 1,2,3,4,5,6,
7,8,9, second signal S is respectively present at moment 1, moment 5 and moment 91、S2And S3.If there are the first signal P at the moment 61,
The time interval between the first signal and the second signal is 1 at this time, and user needs the time between the first signal and the second signal
Between be divided into 3, if delaying the first signal, the moment where the first signal is 8 after adjustment, delay time 2；If the first letter in advance
Number, then the moment where the first signal is 4 after adjusting, and delay time 2, is delayed or corresponding delay time is identical in advance.If
At the moment 7, there are the first signal P1, the time interval between the first signal and the second signal is 2 at this time, and user needs the first signal
Time interval between second signal is 3, if delaying the first signal, the moment where the first signal is 8 after adjustment, when delay
Between be 1；If the first signal in advance, the moment where the first signal is 4 after adjustment, and delay time 3 is delayed or corresponding in advance
Delay time is different.
It delays or in advance after the first signal, then specified time interval is determined by measurement module, obtains in delay adjustment module
To after specified time interval, specified time interval is uploaded to terminal, in order to be monitored to signal adjusted.
The application provides a kind of FPGA time-delay mechanism, the delay time of multiple signals can be controlled in FPGA, and measure
Specified time interval between signal after delay since the precision of FPGA control delay time is higher, and will not produce signal
Raw interference, signal quality will not change, can accurately be measured when carrying out specified time interval measurement in this way
Value, compared with using cable, improves the precision of delay time, and improve the precision of the time interval of measurement；Due to logical
A FPGA delay adjustment module is crossed, the delay of all signals can be controlled, therefore, can only increase by one in existing apparatus
Delay adjustment module reduces hardware complexity, reduces costs simultaneously compared with high-precision delay chip.
In order to make the time interval after adjusting where the first signal between moment and second signal meet being taken for user
Between be spaced, in an implementation of the embodiment of the present invention, need to be determined according to initial interval and required time interval
Therefore delay time on the basis of implementation as shown in Figure 1, can also realize implementation as shown in Figure 2.Its
In, the FPGA time-delay mechanism further include:
Module 13 is obtained, for obtaining moment where the first signal and the second letter before time cycle of second signal, adjustment
Correspond to the initial interval between the initial time for adjusting the period of preceding first signal in number.
For example, as shown in figure 3, second signal is periodic signal, period T, in moment S1、S2And S3There is the second letter
Number, in moment P1There are the first signals, i.e. P1To adjust the moment where preceding first signal, adjustment preceding the is corresponded in second signal
The initial time in the period of one signal is S2, initial interval S2With P1Between time interval, i.e. T2。
Computing module 14, computing module 14 are connect with module 13 is obtained, and computing module 14 also connects with delay adjustment module 11
It connects, computing module 14 is based on according to the time cycle at required time interval, the second signal and the initial interval
Calculate delay time.
It should be noted that delay time can be required time when required time interval is greater than initial interval
The absolute value at interval and the difference of initial interval；Alternatively, delay time is spaced the time required to may be and initial time
The absolute value of the difference at interval adds the period of at least one second signal；Alternatively, delay time may be at least one
The difference in the period of binary signal and above-mentioned absolute value.
When required time interval is less than initial interval, delay time can be required time interval and initial time
The absolute value of the difference at interval is as delay time, by the first signal advance time-delay time；Alternatively, delay time may be institute
Take time interval and initial interval difference absolute value add at least one second signal period；Alternatively, when delay
Between or at least one second signal period and above-mentioned absolute value difference.
When determining delay time according to initial interval and required time interval, since second signal is period letter
Number, therefore increase on the basis of required time interval and the absolute value for the difference for obtaining initial interval acquired in module
The period of second signal, or be spaced the time required to the period of second signal is subtracted and obtain initial time acquired in module
The absolute value of the difference at interval, the value that operation obtains can be used as delay time, thus there is the value of multiple delay times,
It can be according to one of method that user demand or actual needs select the above-mentioned computation delay time come the computation delay time.
Signal adjusted is monitored for the ease of terminal, in an implementation of the embodiment of the present invention, is needed
Measure moment where the first signal and the initial time in second signal corresponding to the period of the first signal after adjustment after adjusting
Between specified time interval therefore on the basis of implementation as shown in Figure 2, can also realize reality as shown in Figure 4
Existing mode.Wherein, measurement module 12 includes:
First judgment module 121, first judgment module 121 are connect with delay adjustment module 11, and first judgment module 121 is used
In judging that the first signal delays delay time or advance time-delay time.
First computing module 123, the first computing module 123 are connect with first judgment module 121, the first computing module 122
For when the first signal delays delay time, the adduction of computation delay time and initial interval；First computing module 122
It is also used in the first signal advance time-delay time, calculates the difference of first time interval and delay time.Wherein, at the first time
Between be divided into adjust preceding first signal where correspond in moment and second signal adjust after the first signal period initial time
Between time interval.
Second judgment module 123, the second judgment module 123 are connect with the first computing module 122, the second judgment module 123
For judging whether adduction is greater than the time cycle of second signal；Second judgment module 123 is also used to judge whether difference is greater than
The time cycle of second signal.
Second computing module 124, the second computing module 124 are connect with the second judgment module 123, the second computing module 124
For in time cycle of the adduction greater than second signal, adduction to be subtracted at least one time cycle, obtain being less than week time
The first result of phase；Second computing module 124 be also used to difference be greater than second signal time cycle when, by difference subtract to
A few time cycle, obtain the second result less than the time cycle.
Specified module 125, specified module 125 are connect with the second judgment module 123, and module 125 is specified also to calculate with second
Module 124 connects, and specifies module 125 to be used for when adduction is greater than the time cycle of second signal, it is specified for specifying the first result
Time interval；Specified module 125 is also used to specify adduction between specified time when adduction is less than the time cycle of second signal
Every；Specified module 125 is also used to specify the second result between specified time when difference is greater than the time cycle of second signal
Every；Specified module 125 is also used to when difference is less than the time cycle of second signal, and specifying difference is specified time interval.
For example, being distinguished at the time of where each second signal as shown in figure 3, second signal is the periodic signal for being T the period
For S1、S2And S3, it is P at the time of where the first signal1, initial interval T2, T2+ T=T1, after adjustment where the first signal
Moment is P1' when the first signal delay or in advance when, the calculation method at specified time interval is as follows:
A, the first signal delays △ t1, △ t1< T and △ t1+T2<T
The adduction of delay time and initial interval is △ t1+T2, because of △ t1+T2< T, so being divided between specified time
△t1+T2。
B, the first signal delays △ t2, △ t2< T and △ t2+T2>T
The adduction of delay time and initial interval is △ t2+T2, because of △ t2+T2> T, so being divided between specified time
△t2+T2-T。
C, the first signal shifts to an earlier date △ t3, △ t3< T and △ t3<T2
Due to P1' and P1In the same period in second signal, therefore, first time interval T2, due to T2-△t3
< T, so being divided into T between specified time2-△t3。
D, the first signal shifts to an earlier date △ t4, △ t4< T and △ t4>T2
Due to P1' locating time cycle and P1The period of locating second signal is adjacent, and therefore, first time interval is
T1-△t4, due to T1-△t4< T, so being divided into T between specified time1-△t4。
As shown in figure 5, P1" and P1Between time interval be less than T, and P1" and P1' between time interval be n T, n
For positive integer.
E, the first signal delays △ t5, △ t5>T
The adduction of delay time and initial interval is △ t5+T2, because of △ t5+T2> T, so being divided between specified time
△T1, △ T1Calculation method can be using calculation method used by above-mentioned A or B, this will not be repeated here.
F, the first signal shifts to an earlier date △ t6, △ t6>T
△ T is divided between specified time2, △ T2Calculation method can be using calculation method used by above-mentioned C or D, herein
It does not repeat them here.
The application is by the calculation method at specified time interval according to delaying or in advance and delay time and second signal
Size relation between period is classified, and different classes of calculation method is different, so that between measurement module calculating specified time
Every when, can by the first signal after all adjustment may where at the time of the case where, fully according to think specified calculation method into
Row calculates, and improves the accuracy for calculating specified time interval.
In order to make the time interval required time interval of the first signal and second signal place moment, implement in the present invention
In one implementation of example, need to adjust the first signal.Wherein, corresponding in a time cycle of second signal to exist at least
Two the first signals, delay adjustment module 11 delay at least two first signals or the advance time-delay time as a whole.
For example, as shown in fig. 6, the moment where second signal is respectively S1、S2And S3, in S2And S3Between time interval
In, in moment P1With moment P2It is respectively present first signal, as a whole by two the first signals, while delaying △ t7Or
△ t in advance simultaneously8, adjust the moment where latter two first signal between time interval it is constant.
At this point, be standard by the moment where first signal in two the first signals, the corresponding computation delay time and
Specified time interval.When two the first signals are integrally delayed, the calculation method at specified time interval can using above-mentioned A, B or
Calculation method used by E；When two the first signals integrally in advance when, the calculation method at specified time interval with can use it is upper
State calculation method used by C, D or F.
In this application, at least two first signals are delayed using a delay adjustment module as a whole or is prolonged in advance
When the time, due to the setting delay adjustment module in FPGA, the precision that FPGA controls delay time is higher, and will not produce to signal
Raw interference, signal quality will not change, can accurately be measured when carrying out specified time interval measurement in this way
Value, which improves the precision of delay time, and improve the precision of the time interval of measurement；Due to being adjusted by a delay
Mould preparation block can control the delay of all signals, therefore, can only increase a delay in existing apparatus and adjust module, drop
Low hardware complexity, reduces costs simultaneously.
In order to calculate time interval, in an implementation of the embodiment of the present invention, when needing to be arranged for each signal
Between label therefore on the basis of implementation as shown in Figure 2, can also realize implementation as shown in Figure 7.Wherein,
FPGA time-delay mechanism 10 further include:
Time tag creation module 15 is connect with measurement module 12, and time tag creation module 15 is for marking adjustment preceding the
At the time of where one signal and second signal.
It should be noted that comprising the carry chain that construct by adder in time tag creation module 15, the first signal with
Second signal is digital signal by analog-signal transitions, realizes the number of temporal information after time tag creation module 15
Word conversion.At the time of time tag creation module 15 marks the rising edge place of the first signal and the second signal, and with week time
Phase creation time label corresponds to the period of the first signal in moment where the time cycle is greater than the first signal and second signal
Initial time between time interval.After a time cycle, continue the starting timing from the time cycle, for letter
Moment creation time label where number.For example, using 0,1,2,3,4,5,6,7,8,9 as one time cycle creation time mark
Label, in first time cycle, the time tag at moment where second signal is 1,5,9, and first time cycle terminates, after
The continuous starting timing from second time cycle, in second time cycle, the time tag at moment is where second signal
3、7。
The application uses time tag creation module, at the time of marking the first signal and the second signal place, the first signal
By analog-signal transitions it is the digital signal characterized by temporal information with second signal, then the first signal is controlled by FPGA and is prolonged
When.It is in this way after the number conversion of temporal information to the realization of the delay function of signal, FPGA control delay is to signal
Time-to-digital converter function does not have any influence, in this way to the performance of entire time-to-digital converter system just without any influence.
In addition, after by time tag creation module, that is, after analog-signal transitions are digital signal, it can be into one
Step carries out the processing of the first signal and the second signal.
The application provides a kind of FPGA time-delay method, as shown in figure 8, the FPGA time-delay method includes:
Step 201 is delayed or the first signal in advance according to delay time.
Step 202 determines specified time interval.
Wherein, the is divided into after adjustment in moment, with second signal where the first signal after corresponding to adjustment between specified time
Time interval between the initial time in the period of one signal, second signal are periodic signal.
In the implementation of the application, on the basis of implementation as shown in Figure 8, be also implemented as
Implementation shown in Fig. 9.Wherein, it is delayed according to delay time or in advance before the first signal executing step 101, it can be with
Execute step:
The moment where the first signal is corresponding with second signal before step 203, the time cycle for obtaining second signal, adjustment
Initial interval between the initial time in period for adjusting preceding first signal.
Step 204, according to required time interval, the time cycle of second signal and initial interval computation delay when
Between.
In the implementation of the application, on the basis of implementation as shown in Figure 9, be also implemented as
Implementation shown in Fig. 10.Wherein, step 202 determines specified time interval, can also be implemented as step 2021 to step
Rapid 2025:
Step 2021 judges that the first signal delays delay time or advance time-delay time.
Step 2022, when the first signal delays delay time, the adduction of computation delay time and initial interval；Or
Person calculates the difference of first time interval and delay time in the first signal advance time-delay time.
Wherein, first time interval is to correspond to after adjusting the in moment and second signal where adjusting preceding first signal
Time interval between the initial time in the period of one signal.
Step 2023 judges whether adduction is greater than the time cycle of second signal；Alternatively, judging whether difference is greater than second
The time cycle of signal.
Step 2024, adduction be greater than second signal time cycle when, adduction is subtracted at least one time cycle, is obtained
To the first result for being less than the time cycle；Alternatively, difference is subtracted at least one when difference is greater than the time cycle of second signal
A time cycle obtains the second result less than the time cycle.
Step 2025, adduction be greater than second signal time cycle when, specify the first result be specified time interval；Or
Person, when adduction is less than the time cycle of second signal, specifying adduction is specified time interval；Alternatively, being greater than second in difference
When the time cycle of signal, specifying the second result is specified time interval；Alternatively, being less than the time cycle of second signal in difference
When, specifying difference is specified time interval.
In the implementation of the application, on the basis of implementation as shown in Figure 8, be also implemented as
Implementation shown in Figure 11, the FPGA time-delay method include:
Step 205, second signal a time cycle in correspond to there are at least two first signals, by least two the
One signal is delayed as a whole or the advance time-delay time.
In the implementation of the application, on the basis of implementation as shown in Figure 9, be also implemented as
Implementation shown in Figure 12.Wherein, the first signal institute before executing step 203 and obtaining the time cycle of second signal, adjustment
In the step of the initial interval corresponded between the initial time for adjusting the period of preceding first signal in moment and second signal
Before rapid, step 206 can also be performed:
At the time of before step 206, label adjust where the first signal and the second signal.
The application provides a kind of FPGA time-delay method, the delay time of multiple signals can be controlled in FPGA, and measure
Specified time interval between signal after delay since the precision of FPGA control delay time is higher, and will not produce signal
Raw interference, signal quality will not change, can accurately be measured when carrying out specified time interval measurement in this way
Value, compared with using cable, improves the precision of delay time, and improve the precision of the time interval of measurement；Due to logical
A FPGA delay adjustment module is crossed, the delay of all signals can be controlled, therefore, can only increase by one in existing apparatus
Delay adjustment module reduces hardware complexity, reduces costs simultaneously compared with high-precision delay chip.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for method reality
For applying example, since it is substantially similar to Installation practice, so describing fairly simple, related place is referring to Installation practice
Part explanation.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the program can be stored in computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic
Dish, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access
Memory, RAM) etc..
The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any
Change or replacement within the technical scope of the present application should all be covered within the scope of protection of this application.Therefore, this Shen
Protection scope please should be subject to the scope of protection of the claims.
Claims (6)
1. a kind of field-programmable gate array FPGA time-delay mechanism, which is characterized in that the FPGA time-delay mechanism includes obtaining mould
Block, computing module, delay adjustment module and measurement module, wherein
The acquisition module, for obtaining moment and second signal where the first signal before time cycle of second signal, adjustment
In correspond to the initial interval between the initial time for adjusting the period of preceding first signal；
The computing module, the computing module are connect with the acquisition module, and the computing module is also adjusted with the delay
Module connection, the computing module be used for according to required time interval, the second signal time cycle and it is described initial when
Between delay time described in interval calculation；
Delay adjustment module according to the delay time for delaying or the first signal in advance；
The measurement module is connect with delay adjustment module, and the measurement module is described for determining specified time interval
The period of the first signal after corresponding to adjustment after adjusting in moment, with second signal where the first signal is divided between specified time
Time interval between initial time, second signal are periodic signal；
The measurement module includes:
First judgment module, first judgment module are connect with delay adjustment module, and the first judgment module is for judging
First signal delays the delay time or the in advance delay time；
First computing module, first computing module are connect with the first judgment module, and first computing module is used for
When the first signal delays the delay time, the adduction of the delay time Yu the initial interval is calculated；Described
One computing module is also used to when the first signal shifts to an earlier date the delay time, calculates first time interval and the delay time
Difference, the first time interval are to correspond to the first signal after adjustment in moment where adjusting preceding first signal and second signal
Period initial time between time interval；
Second judgment module, second judgment module are connect with first computing module, and second judgment module is used for
Judge whether the adduction is greater than the time cycle of second signal；Whether second judgment module is also used to judge the difference
Greater than the time cycle of second signal；
Second computing module, second computing module are connect with second judgment module, and second computing module is used for
When the adduction is greater than the time cycle of second signal, the adduction is subtracted at least one described time cycle, is obtained small
In the first result of the time cycle；Second computing module is also used to be greater than week time of second signal in the difference
When the phase, the difference is subtracted at least one described time cycle, obtains the second result less than the time cycle；
Specified module, the specified module are connect with second judgment module, and the specified module is also calculated with described second
Module connection, the specified module are used to specify first result when the adduction is greater than the time cycle of second signal
For the specified time interval；The specified module is also used to specify when the adduction is less than the time cycle of second signal
The adduction is the specified time interval；The specified module is also used to be greater than the time cycle of second signal in the difference
When, specifying second result is the specified time interval；The specified module is also used in the difference less than the second letter
Number time cycle when, specify the difference be the specified time interval.
2. FPGA time-delay mechanism according to claim 1, which is characterized in that corresponding in a time cycle of second signal
There are at least two first signals, at least two first signal is delayed as a whole or is shifted to an earlier date by the delay adjustment module
The delay time.
3. FPGA time-delay mechanism according to claim 1, which is characterized in that the FPGA time-delay mechanism further include:
Time tag creation module is connect with the measurement module, and the time tag creation module is for marking adjustment preceding first
At the time of where signal and second signal.
4. a kind of FPGA time-delay method, which is characterized in that the FPGA time-delay method includes:
It obtains to correspond in moment where the first signal and second signal before time cycle of second signal, adjustment and adjusts preceding first
Initial interval between the initial time in the period of signal；
When calculating the delay according to required time interval, the time cycle of the second signal and the initial interval
Between；
It is delayed according to the delay time or the first signal in advance；
Determine specified time interval, it is right in moment, with second signal where the first signal after adjusting to be divided between the specified time
Should time interval after adjustment between the initial time in the period of the first signal, second signal is periodic signal；
The determining specified time interval includes:
Judge that the first signal delays the delay time or the in advance delay time；
When the first signal delays the delay time, the adduction of the delay time Yu the initial interval is calculated；Or
Person, when the first signal shifts to an earlier date the delay time, the difference of calculating first time interval and the delay time, described first
Time interval is the starting corresponding to the period of the first signal after adjustment in moment and second signal where adjusting preceding first signal
Time interval between moment；
Judge whether the adduction is greater than the time cycle of second signal；Alternatively, judging whether the difference is greater than second signal
Time cycle；
When the adduction is greater than the time cycle of second signal, the adduction is subtracted at least one described time cycle, is obtained
To the first result for being less than the time cycle；Alternatively, when the difference is greater than the time cycle of second signal, by the difference
Value subtracts at least one described time cycle, obtains the second result less than the time cycle；
When the adduction is greater than the time cycle of second signal, specifying first result is the specified time interval；Or
Person, when the adduction is less than the time cycle of second signal, specifying the adduction is the specified time interval；Alternatively,
When the difference is greater than the time cycle of second signal, specifying second result is the specified time interval；Alternatively, institute
When stating time cycle of the difference less than second signal, specifying the difference is the specified time interval.
5. FPGA time-delay method according to claim 4, which is characterized in that corresponding in a time cycle of second signal
There are at least two first signals, at least two first signal is delayed as a whole or the delay time in advance.
6. FPGA time-delay method according to claim 4, which is characterized in that in the time cycle for obtaining second signal, adjust
Correspond in moment where whole preceding first signal and second signal first between the initial time for adjusting the period of preceding first signal
Before the step of beginning time interval, the FPGA time-delay method further include:
At the time of before label adjusts where the first signal and the second signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710088359.2A CN106843051B (en) | 2017-02-17 | 2017-02-17 | A kind of FPGA time-delay mechanism and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710088359.2A CN106843051B (en) | 2017-02-17 | 2017-02-17 | A kind of FPGA time-delay mechanism and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106843051A CN106843051A (en) | 2017-06-13 |
| CN106843051B true CN106843051B (en) | 2019-05-03 |
Family
ID=59127842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710088359.2A Active CN106843051B (en) | 2017-02-17 | 2017-02-17 | A kind of FPGA time-delay mechanism and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106843051B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113204011B (en) * | 2021-03-29 | 2022-05-20 | 上海星秒光电科技有限公司 | Pulse time output method and device, signal processing equipment and storage medium |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100388669C (en) * | 2004-05-26 | 2008-05-14 | 华为技术有限公司 | System and method for adjusting clock signal phase difference |
| US7187221B2 (en) * | 2004-06-30 | 2007-03-06 | Infineon Technologies Ag | Digital duty cycle corrector |
| WO2007010771A1 (en) * | 2005-07-15 | 2007-01-25 | Matsushita Electric Industrial Co., Ltd. | Signal processing device |
| CN101150316B (en) * | 2007-09-14 | 2011-05-11 | 电子科技大学 | A multi-channel clock synchronization method and system |
| CN102253254B (en) * | 2011-04-18 | 2013-10-09 | 中国航空工业集团公司北京长城计量测试技术研究所 | Device and method for generating multi-channel sine wave phase standard signals |
| CN102510364A (en) * | 2011-12-31 | 2012-06-20 | 成都芯通科技股份有限公司 | Method for calibrating amplitude phase consistency of intelligent multi-channel power amplifier |
| CN103457596A (en) * | 2012-06-05 | 2013-12-18 | 国民技术股份有限公司 | Time delay compensating circuit and method |
| CN106209033A (en) * | 2016-08-24 | 2016-12-07 | 固纬电子(苏州)有限公司 | Phase contrast regulation circuit |
-
2017
- 2017-02-17 CN CN201710088359.2A patent/CN106843051B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106843051A (en) | 2017-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106253902B (en) | Multi-channel parallel acquisition system with multi-device synchronous reset recognition and correction function | |
| US8923442B2 (en) | Reference voltage generation in a single-ended receiver | |
| CN104077257B (en) | The measuring method of multi-channel data transmission synchronization delayed time based on FPGA and system | |
| CN103580656B (en) | Triggering shake real time correction circuit during a kind of grab sample and method | |
| CN103309397B (en) | Based on the synchronous sampling method of the data acquisition equipment of USB | |
| CN110995241B (en) | LVDS delay circuit with self-adaptive phase adjustment | |
| JP6463495B2 (en) | Global clock determination method and structure between systems | |
| CN101539436A (en) | Systems and method for improving accuracy of sensor signals | |
| RU2010108218A (en) | SCHEME DEVICE AND METHOD FOR MEASURING TACT SIGNAL SHAKING | |
| CN118038799A (en) | Signal generating device, driving chip, display system and driving method | |
| US8976341B2 (en) | Optoelectric control apparatus for satellite laser ranging system | |
| CN102981551B (en) | A kind of temperature compensation system for real-time clock and method | |
| CN109945950B (en) | Precision ADC Sampling Clock for High Precision Wireless Guided Wave Radar | |
| CN106230435B (en) | Clock source generating means and method | |
| CN106843051B (en) | A kind of FPGA time-delay mechanism and method | |
| CN102651685B (en) | Signal delay device and method | |
| CN106341124B (en) | The method of phase delay for RF-PWM modulator measured indirectly | |
| CN105634473B (en) | The frequency adjusting method and device of mobile terminal | |
| CN115580275A (en) | High-precision pulse signal generating device, FPGA chip and signal processing equipment | |
| CN105527624B (en) | A kind of method and weather radar system of radar return dynamic estimation noise | |
| US8224606B2 (en) | Measuring clock jitter | |
| CN107566199A (en) | Signal processing apparatus and method and the electronic equipment including the device | |
| KR102919659B1 (en) | Apparatus and method for clock phase calibration | |
| CN117692122A (en) | Dynamic digital multiplying sampling system, method, apparatus and readable medium | |
| CN112129993B (en) | Zero crossing signal output and power line data transmission method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: Room C149, Building 889 Qiju Road, Minhang District, Shanghai, 201100 Patentee after: Shanghai star Photoelectric Technology Co., Ltd. Address before: Room 1201, No. 18, Lane 58, Hexuan Road, Jiading District, Shanghai, 20112 Patentee before: Shanghai star Photoelectric Technology Co., Ltd. |
|
| CP02 | Change in the address of a patent holder | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210813 Address after: 201100 room 321, No. 28, Yuanwen Road, Minhang District, Shanghai Patentee after: SHANGHAI SIMINICS PHOTOELECTRIC TECHNOLOGY Co.,Ltd. Patentee after: Shandong xingsec Photoelectric Technology Co.,Ltd. Address before: 201100 room c149, building 2, No. 889, Qishen Road, Minhang District, Shanghai Patentee before: SHANGHAI SIMINICS PHOTOELECTRIC TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right |