CN106817123B - Phase compensation device based on digital time delay - Google Patents
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Abstract
The invention discloses a phase compensation device based on digital time delay, which adopts an N-stage structure, the phase compensation precision of each stage is different, the phase compensation range is different, the sum of the phase compensation of each stage is equal to the input phase compensation value or the phase compensation value closest to the input in the phase compensation range, and N is an integer greater than or equal to 1; the input signal sampling rate of the phase compensation device is fmThe phase compensation precision is fn，fm≤fn. The invention makes up the deficiency that the existing phase compensation device needs a large number of registers and high-speed shift clocks when the phase compensation range is larger or the compensation precision is higher, and the hardware overhead is very large, and on the premise of ensuring the compensation range and the compensation precision, the structure of the phase compensation device is greatly simplified, the number of shift registers is reduced, the area can be well saved, and the power consumption can be well reduced.
Description
Technical Field
The invention belongs to the field of digital signal processing, and particularly relates to a phase compensation device based on digital time delay.
Background
In the field of digital signal processing, phase compensation of signals is a common phenomenon, for example, in an electric energy metering system, a phase deviation between current and voltage channels needs to be compensated in the current and voltage channels.
The phase compensation method based on digital delay is implemented by a shift register, but when the phase compensation range is large or the compensation accuracy is high, a large number of registers and a high-speed shift clock are required, the hardware overhead is large, and it is fatal to a system. With the development of signal processing, the requirements on the range and precision of phase compensation are higher and higher, and the disadvantages of the conventional structure of phase compensation based on digital delay are more and more prominent.
Disclosure of Invention
The invention aims to overcome the defects that a large number of registers and high-speed shift clocks are needed and hardware overhead is large when the phase compensation range is large or the compensation precision is high in the conventional phase compensation device, and provides a digital delay-based phase compensation device capable of saving hardware resources.
The invention solves the technical problems through the following technical scheme:
the invention provides a phase compensation device based on digital time delay, which is characterized in that the phase compensation device adopts an N-stage structure, the phase compensation precision of each stage is different, the phase compensation range is different, the sum of the phase compensation of each stage is equal to the input phase compensation value or the phase compensation value closest to the input in the phase compensation range, and N is an integer greater than or equal to 1;
the input signal sampling rate of the phase compensation device is fmThe phase compensation precision is fn，fm≤fn。
According to the technical scheme, on the premise of ensuring the compensation range and the compensation precision, based on hierarchical structure compensation, different clocks are adopted in different levels to compensate in different precision and different compensation ranges, the structure of the phase compensation device is greatly simplified, the area can be well saved, the power consumption can be well reduced, and especially when the precision of the phase compensation is far higher than the sampling rate of an input signal and the required phase compensation range is large, the effect of saving the consumption of hardware resources is more prominent.
Preferably, one of the N stages employs a first phase compensation circuit, and the first phase compensation circuit is configured to compensate an input signal within a first phase compensation range;
the first phase compensation circuit includes:
the first shift register chain comprises a plurality of shift registers and alternative selectors which are equal in number to the shift registers, the shift registers are alternately connected with the alternative selectors, signals input into the first shift register chain are input through a first shift register of the first shift register chain and output through a last alternative selector of the first shift register chain;
the number of the shift registers of the first shift register chain is determined according to the phase compensation range of the first phase compensation circuit;
a decoder for decoding the phase compensation value and generating a selection signal for controlling the alternative selector.
Namely, the arrangement sequence of the devices on the first shift register chain is as follows: a shift register, an alternative selector, then a shift register, an alternative selector, … …, to the last shift register, the last alternative selector; the decoder is connected to each of the two-out-of-one selectors.
Preferably, one of the N stages employs a second phase compensation circuit, and the second phase compensation circuit is configured to compensate the input signal within a second phase compensation range;
the second phase compensation circuit includes:
the second shift register chain comprises a plurality of shift registers and alternative selectors which are equal in number to the shift registers, the shift registers are alternately connected with the alternative selectors, signals input into the second shift register chain are input through a first shift register of the second shift register chain and output through a last alternative selector of the second shift register chain;
the number of shift registers of the second shift register chain is determined according to the phase compensation range of the second phase compensation circuit.
Namely, the arrangement sequence of the devices on the second shift register chain is as follows: a shift register, an alternative selector, then a shift register, an alternative selector, … …, through to the last shift register, the last alternative selector. The second phase compensation range is different from the first phase compensation range.
Preferably, one of the N stages employs a third phase compensation circuit, and the third phase compensation circuit is configured to compensate an input signal within a third phase compensation range;
the third phase compensation circuit includes:
the third shift register chain comprises a plurality of shift registers and alternative selectors which are equal in number to the shift registers, the shift registers are alternately connected with the alternative selectors, signals input into the third shift register chain are input through a first shift register of the third shift register chain and output through a last alternative selector of the third shift register chain;
the number of shift registers of the third shift register chain is determined according to the phase compensation range of the third phase compensation circuit.
Namely, the arrangement sequence of the devices on the third shift register chain is as follows: a shift register, an alternative selector, then a shift register, an alternative selector, … …, through to the last shift register, the last alternative selector. The third phase compensation range is different from both the second phase compensation range and the first phase compensation range.
Preferably, N is equal to 1, a first phase compensation circuit is adopted in the one-stage structure, an input signal of the phase compensation device is input by a first shift register of the first shift register chain and output by a last one-out-of-two selector of the first shift register chain;
let fnDivided by fmIs x, the remainder is y: f. ofm＝fnOr, fm<fnAnd y is not equal to 0;
the shift registers of the first shift register chain have a clock frequency fn。
Preferably, the maximum time delay of the phase compensation in the phase compensation range of the phase compensation device is set as T:
the number of shift registers of the first shift register chain is ceil (T/f)n) The number of shift registers to be shifted is floor (phase compensation value/f)n)。
Wherein ceil (×) represents the upper round and floor (×) represents the lower round.
Preferably, N is equal to 2, the two-stage structure employs a first phase compensation circuit and a second phase compensation circuit, the first shift register chain is connected with the second shift register chain, and an input signal of the phase compensation device is input by the first shift register chain and output by the second shift register chain;
let fnDivided by fmIs x, the remainder is y: f. ofm<fn，y＝0；
Decomposition of x into x-2pX q, p is 0, q is equal to 2 or an odd number greater than 2:
the shift registers of the first shift register chain have a clock frequency fm；
The shift registers of the second shift register chain have a clock frequency fnThe number is q-1.
Preferably, the maximum time delay of the phase compensation in the phase compensation range of the phase compensation device is set as T:
the number of shift registers of the first shift register chain is ceil (T/f)m) The number of shift registers to be shifted is floor (phase compensation value/f)m)；
The number of shift registers to be shifted in the second shift register chain is round (phase compensation value-compensation amount/f of the first phase compensation circuit)m)。
Where round (×) indicates rounding.
Preferably, N is equal to 3, a three-stage structure adopts a first phase compensation circuit, a third phase compensation circuit and a second phase compensation circuit, the first shift register chain, the third shift register chain and the second shift register chain are sequentially connected, an input signal of the phase compensation device is input by the first shift register chain, passes through the third shift register chain and is output by the second shift register chain;
let fnDivided by fmIs x, the remainder is y: f. ofm<fn，y＝0；
Decomposition of x into x-2pXq, p is an integer greater than 0, q is equal to 2 or an odd number greater than 2;
the shift registers of the first shift register chain have a clock frequency fm；
A previous shift register in the third shift register chainThe clock frequency of (a) is half of the clock frequency of the next shift register, and the clock frequency of the last shift register is fn2, the number is p;
the shift registers of the second shift register chain have a clock frequency fnThe number is q-1.
Preferably, the maximum time delay of the phase compensation in the phase compensation range of the phase compensation device is set as T:
the number of shift registers of the first shift register chain is ceil (T/f)m) The number of shift registers to be shifted is floor (phase compensation value/f)m)；
The number of shift registers to be shifted in the third shift register chain is floor (phase compensation value-compensation amount of the first phase compensation circuit-
)；
The number of shift registers to be shifted in the second shift register chain is round (phase compensation value-compensation amount of the first phase compensation circuit-compensation amount of the second phase compensation circuit/f)m)。
On the basis of the common knowledge in the field, the above preferred conditions can be combined randomly to obtain the preferred embodiments of the invention.
The positive progress effects of the invention are as follows: on the premise of ensuring the compensation range and the compensation precision, the invention compensates based on the hierarchical structure, different clocks are adopted in different stages to compensate with different precisions and different compensation ranges, the structure of the phase compensation device is greatly simplified, the number of shift registers is reduced, the area can be well saved, the power consumption can be well reduced, and especially, when the precision of the phase compensation is far higher than the sampling rate of an input signal and the required phase compensation range is larger, the effect of saving the consumption of hardware resources is more prominent.
Drawings
Fig. 1 is a block diagram of a digital delay-based phase compensation apparatus according to embodiment 1 of the present invention.
Fig. 2 is a block diagram of a first phase compensation circuit of the phase compensation apparatus based on digital delay according to embodiment 1 of the present invention.
Fig. 3 is a block diagram of a third phase compensation circuit of the phase compensation apparatus based on digital delay according to embodiment 1 of the present invention.
Fig. 4 is a block diagram of a second phase compensation circuit of the phase compensation apparatus based on digital delay according to embodiment 1 of the present invention.
Fig. 5 is a block diagram of a digital delay-based phase compensation apparatus according to embodiment 3 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, a phase compensation device based on digital delay adopts a three-stage structure, namely a first stage 1, an intermediate stage 2 and a last stage 3. The first stage 1 adopts a first phase compensation circuit as shown in fig. 2, the middle stage 2 adopts a third phase compensation circuit as shown in fig. 3, and the last stage 3 adopts a second phase compensation circuit as shown in fig. 4. The phase compensation precision of each stage is different and the phase compensation range is different.
Setting the sampling rate of the input signal of the phase compensation device as fmThe phase compensation precision is fnMaximum delay of phase compensation is T, fnDivided by fmHas a quotient of x and a remainder of y, and x is decomposed into x-2pX q, q is equal to 2 or an odd number greater than 2:
fm<fny is 0 and p is an integer greater than 0.
The first phase compensation circuit is configured to compensate an input signal in a first phase compensation range, as shown in fig. 2, and includes:
a first shift register chain including a plurality of shift registers 11 and a plurality of alternative selectors 12 (i.e., MUXs in the figure), the number of the shift registers 11 and the number of the alternative selectors 12 are the same, the shift registers 11 are alternately connected to the alternative selectors 12, and a signal input to the first shift register chain is input by a first shift register 11 of the first shift register chain and output by a last alternative selector 12 of the first shift register chain;
a decoder 13 for decoding the phase compensation value to generate a selection signal for controlling the one-out-of-two selector 12;
the clock frequency of the shift registers 11 of the first shift register chain is fmThe number of shift registers 11 of said first shift register chain is equal to ceil (T/f)m) If the input of the decoder is Ao…A1Then the first phase compensation range is
The third phase compensation circuit is configured to compensate the input signal in a third phase compensation range, as shown in fig. 3, and includes:
a third shift register chain including a plurality of shift registers 31 and a plurality of one-out-of-two selectors 32, the number of the shift registers 31 and the number of the one-out-of-two selectors 32 being the same, the shift registers 31 and the one-out-of-two selectors 32 being alternately connected, a signal input to the third shift register chain being input by a first shift register 31 of the third shift register chain and being output by a last one-out-of-two selector 32 of the third shift register chain;
the clock frequency of the previous shift register 31 in the third shift register chain is half of the clock frequency of the next shift register 31, and the clock frequency of the last shift register 31 is fnA/2, the number of shift registers 31 of the third shift register chain is p, and the third phase compensation range is p
The second phase compensation circuit is used for compensating the input signal in a second phase compensation range, as shown in fig. 4, and includes:
a second shift register chain including a plurality of shift registers 21 and a plurality of one-out-of-two selectors 22, the number of the shift registers 21 and the number of the one-out-of-two selectors 22 being the same, the shift registers 21 and the one-out-of-two selectors 22 being alternately connected, a signal input to the second shift register chain being input by a first shift register 21 of the second shift register chain and being output by a last one-out-of-two selector 22 of the second shift register chain;
the shift registers 21 of the second shift register chain have a clock frequency fnThe number of shift registers 21 of the second shift register chain is q-1, and the second phase compensation range is q-1
The shift registers in the first shift register chain, the third shift register chain and the second shift register chain are all D flip-flops.
The first shift register chain, the third shift register chain and the second shift register chain are sequentially connected, an input signal din of the phase compensation device is input by the first phase compensation circuit, and an output signal dout is output by the second phase compensation circuit through the third phase compensation circuit. That is, the output of the first phase compensation circuit is the input of the third phase compensation circuit, and the output of the third phase compensation circuit is the input of the second phase compensation circuit.
The phase compensation device divides the input phase compensation value into three parts, wherein the first part is Ao…A1The second part is Bp…B1And the third part is Cq-1…C1The three parts respectively compensate the input signal by three stages, and the sum of the phase compensation of each stage is equal to the input phase compensation value or is closest to the phase compensation value in the phase compensation range.
The following describes a process of phase compensation using the phase compensation device of the present embodiment with reference to a specific example:
the input signal having a sampling frequency fmThe required phase compensation accuracy is f for 1MnThe maximum delay of the phase compensation is 50ns, and the phase compensation value required at a certain moment is 35.8 ns. So x is fn/fm＝2p×q＝21X 2, i.e., p is 1 and q is 2.
In a first stage 1, the shift registers of the first shift register chain have a clock frequency fm1M, the corresponding precision is 1ns, the number ceil (50/1) of the shift registers is 50, and the binary bit number input by the decoder is ceil (log2(50)) -6; the required phase compensation value is 35.8ns, the number of shift registers to be shifted is floor (35.8/1) ═ 35, and the input A of the decodero…A16' b100011, the compensation to the input signal is realized by the selection of the alternative selector, and the compensation amount is 35 ns.
The number p of shift registers in the intermediate stage 2 and the third shift register chain is 1, and the corresponding clock frequency is fn2M, corresponding to a precision of 0.5ns, 0.8ns for the required phase compensation value (35.8-35), 1 for the number of shift registers to be shifted (floor ((35.8-35)/0.5), Bp…B11' b1, realizing the compensation of the input signal through the selection of the alternative selector, wherein the compensation amount is 0.5 ns;
the last stage 3, the number of shift registers (q-1) is 1, the corresponding clock frequency fn is 4M, the corresponding accuracy is 0.25ns, the required phase compensation value (35.8-35-0.5) is 0.3ns, the number of shift registers to be shifted is round ((35.8-35-0.5)/0.25) is 1, Cq-1…C11' b1, realizing the compensation of the input signal through the selection of the alternative selector, wherein the compensation amount is 0.25 ns;
phase compensation value, three parts Ao…A1，Bp…B1，Cq-1…C1Total 8 bits, total offset is 35.75 ns.
In this example, a total of 50+1+1 to 52 shift registers are used, and if a hierarchical structure is not adopted, a total of 203 shift registers (50.8/0.25) are required, so that the use of the registers is greatly reduced, and the power consumption is also greatly reduced because the hierarchical structure adopts different clocks. Especially, when the required phase compensation precision is far larger than the sampling rate of the input signal, the effect of saving hardware resources is more obvious.
Example 2
The phase compensation device based on digital delay of this embodiment is basically the same as the phase compensation device of embodiment 1, except that the phase compensation device of this embodiment adopts a two-stage structure, namely, a first stage and a last stage (i.e., without the intermediate stage in embodiment 1), wherein the first stage adopts the first phase compensation circuit in embodiment 1, and the last stage adopts the second phase compensation circuit in embodiment 1. The phase compensation precision of each stage is different and the phase compensation range is different.
Wherein f ism<fn，y＝0，p＝0。
The bit compensation device of this embodiment divides the input phase compensation value into two parts, and compensates the input signal by two stages, respectively, and the sum of the phase compensation of each stage is equal to the input phase compensation value or is closest to the phase compensation value in the phase compensation range.
Example 3
The phase compensation apparatus based on digital delay of the present embodiment is substantially the same as the phase compensation apparatus of embodiment 1, except that, as shown in fig. 5, the phase compensation apparatus of the present embodiment adopts a one-stage structure, which is a first stage (i.e., without the intermediate stage and the last stage in embodiment 1), wherein the first stage adopts the first phase compensation circuit in embodiment 1.
fm＝fnOr, fm<fnAnd y is not equal to 0;
in this embodiment, the clock frequency of the shift register of the first shift register chain is fn；
The number of shift registers of the first shift register chain is ceil (T/f)n) The number of shift registers to be shifted is floor (phase compensation value/f)n)。
The bit compensation device of the embodiment compensates the input phase compensation value by one stage, and the sum of the phase compensation of each stage is equal to the input phase compensation value or is closest to the phase compensation value in the phase compensation range.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (8)
1. A phase compensation device based on digital time delay is characterized in that the phase compensation device adopts an N-stage structure, the phase compensation precision of each stage is different, the phase compensation range is different, the sum of the phase compensation of each stage is equal to an input phase compensation value or the phase compensation value closest to the input in the phase compensation range, and N is an integer greater than or equal to 1;
the input signal sampling rate of the phase compensation device is fmThe phase compensation precision is fn，fm≤fn；
One of the N stages adopts a first phase compensation circuit, and the first phase compensation circuit is used for compensating an input signal in a first phase compensation range;
the first phase compensation circuit includes:
the first shift register chain comprises a plurality of shift registers and alternative selectors which are equal in number to the shift registers, the shift registers are alternately connected with the alternative selectors, signals input into the first shift register chain are input through a first shift register of the first shift register chain and output through a last alternative selector of the first shift register chain;
the number of the shift registers of the first shift register chain is determined according to the phase compensation range of the first phase compensation circuit;
a decoder for decoding the phase compensation value to generate a selection signal for controlling the one-out-of-two selector;
n is equal to 1, a first phase compensation circuit is adopted in a one-stage structure, an input signal of the phase compensation device is input by a first shift register of the first shift register chain and output by a last one-out-of-two selector of the first shift register chain;
let the quotient of fn divided by fm be x, the remainder be y: fm ═ fn, or, fm < fn and y ≠ 0;
the clock frequency of the shift registers of the first shift register chain is fn.
2. The phase compensation apparatus of claim 1, wherein one of the N stages employs a second phase compensation circuit for compensating the input signal within a second phase compensation range;
the second phase compensation circuit includes:
the second shift register chain comprises a plurality of shift registers and alternative selectors which are equal in number to the shift registers, the shift registers are alternately connected with the alternative selectors, signals input into the second shift register chain are input through a first shift register of the second shift register chain and output through a last alternative selector of the second shift register chain;
the number of shift registers of the second shift register chain is determined according to the phase compensation range of the second phase compensation circuit.
3. The phase compensation apparatus of claim 2, wherein one of the N stages employs a third phase compensation circuit for compensating an input signal in a third phase compensation range;
the third phase compensation circuit includes:
the third shift register chain comprises a plurality of shift registers and alternative selectors which are equal in number to the shift registers, the shift registers are alternately connected with the alternative selectors, signals input into the third shift register chain are input through a first shift register of the third shift register chain and output through a last alternative selector of the third shift register chain;
the number of shift registers of the third shift register chain is determined according to the phase compensation range of the third phase compensation circuit.
4. The phase compensation apparatus of claim 1, wherein the phase compensation maximum time delay of the phase compensation range of the phase compensation apparatus is set to T:
the number of shift registers of the first shift register chain is ceil (T/f)n) The number of shift registers to be shifted is floor (phase compensation value/f)n)。
5. The phase compensation apparatus of claim 2, wherein N is equal to 2, a two-stage structure employs a first phase compensation circuit and a second phase compensation circuit, the first shift register chain is connected to the second shift register chain, an input signal of the phase compensation apparatus is input by the first shift register chain and output by the second shift register chain;
let fnDivided by fmIs x, the remainder is y: f. ofm<fn，y＝0；
Decomposition of x into x-2pX q, p is 0, q is equal to 2 or an odd number greater than 2:
the shift registers of the first shift register chain have a clock frequency fm；
The shift registers of the second shift register chain have a clock frequency fnThe number is q-1.
6. The phase compensation apparatus of claim 5, wherein the phase compensation maximum time delay of the phase compensation range of the phase compensation apparatus is set to T:
the number of shift registers of the first shift register chain is ceil (T/f)m) The number of shift registers to be shifted is floor (phase compensation value/f)m)；
The number of shift registers to be shifted in the second shift register chain is round (phase compensation value-compensation amount/f of the first phase compensation circuit)m)。
7. The phase compensation apparatus according to claim 3, wherein N is equal to 3, a three-stage structure employs a first phase compensation circuit, a third phase compensation circuit, and a second phase compensation circuit, the first shift register chain, the third shift register chain, and the second shift register chain are connected in sequence, and an input signal of the phase compensation apparatus is input by the first shift register chain, passes through the third shift register chain, and is output by the second shift register chain;
let fnDivided by fmIs x, the remainder is y: f. ofm<fn，y＝0；
Decomposition of x into x-2pXq, p is an integer greater than 0, q is equal to 2 or an odd number greater than 2;
the shift registers of the first shift register chain have a clock frequency fm；
The clock frequency of the previous shift register in the third shift register chain is half of the clock frequency of the next shift register, and the clock frequency of the last shift register is fn2, the number is p;
the shift registers of the second shift register chain have a clock frequency fnThe number is q-1.
8. The phase compensation apparatus of claim 7, wherein the maximum delay of phase compensation of the phase compensation range of the phase compensation apparatus is set to T:
the number of shift registers of the first shift register chain is ceil (T/f)m) Need forThe number of shifted shift registers is floor (phase compensation value/f)m)；
The number of shift registers to be shifted in the third shift register chain is floor (phase compensation value-compensation amount of the first phase compensation circuit-
)；
The number of shift registers to be shifted in the second shift register chain is round (phase compensation value-compensation amount of the first phase compensation circuit-compensation amount of the second phase compensation circuit/f)m)。
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