CN106815627A - Semiconductor storage and adapter - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor memory device and an adapter including a wireless antenna that ensures sufficient communication performance while suppressing an increase in manufacturing cost. A semiconductor memory device according to one embodiment includes a first substrate, a nonvolatile memory, a memory controller, a first interface terminal, a first antenna, and a communication controller. The first antenna is connected to the first substrate, at least a part of which is located outside the first substrate in a plan view of the first surface, and at least a remaining part is located on the first substrate. The communication controller is configured to communicate with a second external device via the first antenna.

Description

Semiconductor storage device and adapter

This application claims Japanese patent application No. 2015-233522 (application date: November 30, 2015) and Japanese patent application No. 2016-100705 (application date: May 19, 2016) as the priority of the earlier application. This application incorporates this earlier application in its entirety by reference.

technical field

This embodiment relates to a semiconductor storage device and an adapter.

Background technique

Antennas for communicating with external devices are sometimes mounted on various devices. For example, an antenna such as a dipole antenna, a loop antenna, or a dielectric antenna is mounted on the device.

However, mounting the antenna on the device may increase the manufacturing cost of the device.

Contents of the invention

Embodiments of the present invention provide a semiconductor memory device and an adapter including a wireless antenna that ensures sufficient communication performance while suppressing an increase in manufacturing cost.

A semiconductor memory device according to one embodiment includes a first substrate, a nonvolatile memory, a memory controller, a first interface terminal, a first antenna, and a communication controller. The first substrate has a first face and a second face opposite to the first face. The nonvolatile memory is mounted on the first surface. The memory controller is mounted on the first substrate and configured to control the nonvolatile memory. The first interface terminal is mounted on the first substrate and can be electrically connected to a first external device. The first antenna is connected to the first substrate, at least a part is located outside the first substrate in a plan view of the first surface, and at least a remaining part is located on the first substrate. The communication controller is configured to communicate with a second external device via the first antenna.

Description of drawings

FIG. 1 is a perspective view showing an SD card according to the first embodiment.

FIG. 2 is a block diagram showing an example of a system configuration including an SD card according to the first embodiment.

Fig. 3 is a plan view showing the SD card according to the first embodiment with the top cover removed.

4 is a cross-sectional view showing the SD card according to the first embodiment along line F4 - F4 in FIG. 3 .

5 is a plan view showing the SD card according to the second embodiment with the top cover removed.

6 is a plan view showing the first substrate of the second embodiment with the sealing resin removed.

Fig. 7 is a bottom view showing a first substrate of the second embodiment.

8 is a cross-sectional view schematically showing a part of the first substrate according to the second embodiment along the line F8 - F8 in FIG. 6 .

9 is a cross-sectional view schematically showing a part of the first substrate according to the second embodiment along line F9 - F9 in FIG. 6 .

Fig. 10 is a plan view showing a part of the first substrate of the second embodiment.

11 is a plan view showing a part of the first substrate in one step of the manufacturing process of the second embodiment.

12 is a plan view showing an SD card according to a modified example of the second embodiment with the top cover removed.

Fig. 13 is a plan view showing an SD card according to a third embodiment.

14 is a plan view showing a first substrate according to a fourth embodiment.

15 is a plan view showing a part of the first substrate of the fourth embodiment.

16 is a plan view showing a part of the first substrate in one step of the manufacturing process of the fourth embodiment.

17 is a plan view showing a first substrate according to a modified example of the fourth embodiment.

FIG. 18 is a plan view showing part of a first substrate in a modified example of the fourth embodiment.

19 is a plan view showing a part of the first substrate in one of the manufacturing steps of a modified example of the fourth embodiment.

Fig. 20 is a bottom view showing the SD card according to the fifth embodiment, omitting the bottom cover.

Fig. 21 is a plan view showing an SD card according to a sixth embodiment.

detailed description

Hereinafter, the semiconductor storage device and the adapter according to the embodiments will be described in detail with reference to the drawings. In addition, this invention is not limited by these embodiment.

In addition, a plurality of representations may be described at the same time for a component related to an embodiment and/or a description of the component. Regarding the constituent elements and explanations, the adoption of other forms of expression that are not described is not affected. In addition, regarding the constituent elements and explanations that do not describe a plurality of expression forms, it does not affect the adoption of other expression forms.

(first embodiment)

Next, a first embodiment will be described with reference to FIGS. 1 to 4 . FIG. 1 is a perspective view showing an SD card 11 according to the first embodiment. The SD card 11 is an example of a semiconductor storage device. The semiconductor storage device may be other devices such as a multimedia card or a USB flash memory, for example. The semiconductor storage device may include a device or system including a semiconductor chip, and may include a wireless communication device such as a mobile phone.

As shown in each figure, in this specification, an X-axis, a Y-axis, and a Z-axis are defined. The X axis, the Y axis, and the Z axis are orthogonal to each other. The X axis is defined along the width of the SD card 11 . The Y axis is defined along the length of the SD card 11 . The Z axis is defined along the thickness of the SD card 11 .

Wireless communication technology is applied to the SD card 11 of this embodiment. For example, near field communication (NFC) using a frequency of 13.56 MHz is applied to the SD card 11 . Other wireless communication technologies can also be adapted to the SD card 11 .

The NFC-adapted SD card 11 induces a current in the wireless antenna through electromagnetic induction. Therefore, as described below, the SD card 11 has, for example, a wireless antenna formed in a shape that can be called a coil shape, a spiral shape, or a spiral shape.

FIG. 2 is a block diagram showing an example of a system configuration including the SD card 11 of the first embodiment. As shown in FIG. 2 , SD card 11 is configured to be electrically connected to host device 12 . Furthermore, the SD card 11 is configured to communicate wirelessly with the wireless communication host device 13 . The host device 12 is an example of a first external device. The wireless communication host device 13 is an example of a second external device. The host device 12 and the wireless communication host device 13 are respectively, for example, a personal computer, a portable computer, a smart phone, a portable phone, a server, a smart card, or other devices.

The SD card 11 has an interface (I/F) terminal 22 , a wireless antenna 23 , a communication controller 24 , a flash memory (flash memory) 25 , a memory controller 26 , and a capacitor 27 . The I/F terminal 22 is an example of a first interface terminal. The flash memory 25 is an example of a nonvolatile memory.

The communication controller 24 controls communication between the SD card 11 and the host device 12 and communication between the SD card 11 and the wireless communication host device 13 . The communication controller 24 has a storage unit 24a and a voltage detector 24b. The storage unit 24 a may be an electronic component independent of the communication controller 24 . In this case, the communication controller 24 is connected to the storage unit 24a.

Communications controller 24 and memory controller 26 may also be included in one electronic component. In addition, for example, a plurality of electronic components and wiring and programs may also constitute the communication controller 24 and the memory controller 26 . That is, the communication controller 24 and the memory controller 26 may each be composed of one electrical component, a plurality of electrical components, or one or more electrical components and a program.

When the SD card 11 is electrically connected to the host device 12 , the SD card 11 operates using electric power supplied from the host device 12 . For example, the SD card 11 is written with data by the host device 12 or read by the host device 12 .

The SD card 11 can transmit and receive data with the wireless communication host device 13 without being connected to other devices such as the host device 12 and the wireless communication host device 13 and without being supplied with power from the other devices. For example, the SD card 11 can transmit and receive data with the wireless communication host device 13 using electric power generated (induced) by electromagnetic induction of the wireless antenna 23 . The SD card 11 performs communication using NFC at, for example, a frequency of about 13.56 MHz, and transmits or receives data to or from the wireless communication host device 13 . In this way, the SD card 11 can operate without receiving power supply from the host device 12 .

The SD card 11 of this embodiment transmits and receives data to and from the host device 12 along the SD interface. The SD card 11 can also use other interfaces to send and receive data with the host device 12 . The SD card 11 transmits and receives data with the wireless communication host device 13 along the NFC interface. The SD card 11 can also use other wireless communication interfaces to transmit and receive data with the wireless communication host device 13 . In addition, the host device 12 and the wireless communication host device 13 may be the same device.

As shown in FIG. 1 , the SD card 11 also has a casing 31 . The case 31 is made of, for example, a synthetic resin that is a non-magnetic body and an insulator. The housing 31 can also be made of other materials.

The casing 31 is formed in a substantially quadrangular box shape. The housing 31 may also be formed in other shapes. The housing 31 has: a bottom cover 32 , a top cover 33 and a lock switch 34 . The bottom cover 32 is an example of the first cover. The top cover 33 is an example of the second cover.

FIG. 3 is a plan view showing the SD card 11 according to the first embodiment with the top cover 33 removed. FIG. 3 shows a portion of each of the communication controller 24 , the flash memory 25 , and the memory controller 26 missing. FIG. 3 shows the appearance of missing parts of the communication controller 24, the flash memory 25, and the memory controller 26 by dashed-two dotted lines.

As shown in FIG. 3 , the SD card 11 also has a first substrate 41 and an antenna module 42 . The casing 31 accommodates the first substrate 41 , the antenna module 42 , the communication controller 24 , the flash memory 25 and the memory controller 26 .

The communication controller 24 , the flash memory 25 and the memory controller 26 are mounted on the first substrate 41 . The antenna module 42 has a second substrate 45 and a first antenna pattern 46 . In the first embodiment, the wireless antenna 23 of FIG. 2 has a first antenna pattern 46 . The first antenna pattern 46 is an example of a first antenna.

The SD card 11 is formed in a substantially quadrangular card shape and has four end portions 11a, 11b, 11c, and 11d. For convenience of description, the four end portions 11a to 11d of the SD card 11 are respectively referred to as a front end portion 11a, a rear end portion 11b, a left end portion 11c, and a right end portion 11d. In addition, the front end 11a, the rear end 11b, the left end 11c, and the right end 11d are names based on the positions in FIG.

The front end portion 11a is one end portion of the SD card 11 in the direction along the Y-axis. The rear end portion 11b is the other end portion of the SD card 11 in the direction along the Y-axis, and is located on the opposite side of the front end portion 11a. The front end portion 11a and the rear end portion 11b extend in a direction along the X-axis.

The left end portion 11c is one end portion of the SD card 11 in the direction along the X-axis. The right end portion 11d is the other end portion of the SD card 11 in the direction along the X-axis, and is located on the opposite side of the left end portion 11c. The left end portion 11c and the right end portion 11d extend in the direction along the Y-axis.

FIG. 4 is a cross-sectional view showing the SD card 11 according to the first embodiment along line F4 - F4 in FIG. 3 . As shown in FIG. 4 , the bottom cover 32 has a bottom surface 51 and a first inner surface 52 . The bottom surface 51 is formed on one surface of the housing 31 exposed to the outside. The first inner surface 52 is located on the opposite side of the bottom surface 51 .

In the bottom cover 32 , a first concave portion 55 , a second concave portion 56 and a plurality of terminal holes 57 are provided. Furthermore, FIG. 4 shows one of the plurality of terminal holes 57 . The first concave portion 55 and the second concave portion 56 may be called, for example, a recess, a receiving portion, or a fitting portion, respectively. The first concave portion 55 and the second concave portion 56 are respectively disposed on the first inner surface 52 . In other words, the first and second recesses 55 , 56 are portions recessed from the first inner surface 52 .

The first concave portion 55 and the second concave portion 56 are arranged so as to partially overlap each other in the direction along the Y-axis. The first concave portion 55 is closer to the front end portion 11 a than the second concave portion 56 . In detail, the end of the first recess 55 in the positive direction along the Y axis (the direction indicated by the arrow of the Y axis) is closer to the front end 11a than the end of the second recess 56 in the positive direction along the Y axis. .

In the first recess 55, the first substrate 41 is housed. In the thickness direction of the first substrate 41 (direction along the Z-axis), a part of the first substrate 41 is located outside the first recess 55 . In other words, the depth of the first concave portion 55 is shallower than the thickness of the first substrate 41 . In addition, the depth of the first concave portion 55 may be deeper than the thickness of the first substrate 41 . The antenna module 42 is housed in the second recess 56 . A part of the antenna module 42 can also be located outside the second recess 56 .

A plurality of terminal holes 57 are provided in the first concave portion 55 . The plurality of terminal holes 57 are adjacent to the front end portion 11 a and are aligned in the direction along the X-axis. The plurality of terminal holes 57 respectively penetrate the bottom cover 32 from the bottom surface 51 across the first concave portion 55 of the first inner surface 52 . In other words, the plurality of terminal holes 57 are respectively opened in the first recesses 55 .

The top cover 33 is installed on the bottom cover 32 . The top cover 33 covers the first substrate 41 accommodated in the first recess 55 and the antenna module 42 accommodated in the second recess 56 .

The top cover 33 has a top surface 61 and a second inner surface 62 . The top surface 61 is formed on one surface of the housing 31 exposed to the outside. When the case 31 is described, the top surface 61 is located on the opposite side to the bottom surface 51 . When the top cover 33 is described, the second inner surface 62 is located on the opposite side of the top surface 61 .

In the top cover 33, a third concave portion 65 is provided. The third concave portion 65 is disposed on the second inner surface 62 . By attaching the top cover 33 to the bottom cover 32 , a part of the first substrate 41 located outside the first recess 55 is accommodated in the third recess 65 . The first recess 55 and the third recess 65 hold the first substrate 41 and restrict the movement of the first substrate 41 .

The first substrate 41 is, for example, a printed circuit board (PCB). The first substrate 41 may be another substrate such as a flexible printed circuit board (FPC). The first substrate 41 has a first surface 41a, a second surface 41b, and an end surface 41c.

The first face 41 a is formed substantially flat, and faces the top cover 33 . The second surface 41b is formed substantially flat and is located on the opposite side to the first surface 41a. The second surface 41b faces the bottom cover 32 . The end surface 41c connects the edge of the first surface 41a and the edge of the second surface 41b.

As shown in FIG. 3 , the communication controller 24 , the flash memory 25 and the memory controller 26 are mounted on the first surface 41 a of the first substrate 41 . In addition, at least one of the communication controller 24 , the flash memory 25 and the memory controller 26 may be mounted on other parts of the first substrate 41 . In addition, the communication controller 24 may be provided in other places such as the second substrate 45, for example.

The first substrate 41 is formed in a substantially quadrangular plate shape. The first substrate 41 may also be formed in other shapes. The length of the first substrate 41 in the direction along the Y axis is shorter than half of the length of the housing 31 in the direction along the Y axis. The size of the first substrate 41 is not limited thereto, for example, the length of the first substrate 41 along the Y-axis direction may also be longer than half of the length of the housing 31 along the Y-axis direction.

As shown in FIG. 4 , a plurality of I/F terminals 22 are provided on the second surface 41 b of the first substrate 41 . 4 shows one of the plurality of I/F terminals 22 . The plurality of I/F terminals 22 are adjacent to the front end portion 11a of the SD card 11, and are arranged in a direction along the X-axis. The plurality of I/F terminals 22 are exposed to the outside of the case 31 through the plurality of terminal holes 57 of the bottom cover 32 .

The I/F terminal 22 of the present embodiment is an SD interface terminal, and ensures electrical connection to the host device 12 . In other words, the I/F terminal 22 can be electrically connected to the host device 12 .

The second substrate 45 of the antenna module 42 is FPC. Therefore, the second substrate 45 is thinner and more flexible than the first substrate 41 . The second substrate 45 may also be another substrate such as a PCB.

The second substrate 45 has a connection surface 45a. The connection surface 45 a faces the top cover 33 . A part of the connection surface 45 a of the second substrate 45 faces a part of the second surface 41 b of the first substrate 41 . That is, when the first surface 41 a is viewed from above as in FIG. 3 , a part of the first substrate 41 overlaps a part of the second substrate 45 .

The second substrate 45 is formed in a substantially square film shape. Therefore, the number of second substrates 45 cut out from one large substrate can become larger. The second substrate 45 may be formed in other shapes.

The length of the second substrate 45 in the direction along the Y axis is longer than the length of the first substrate 41 in the direction along the Y axis. The size of the second substrate 45 is not limited thereto, for example, the length of the second substrate 45 along the Y-axis direction may also be shorter than the length of the first substrate 41 along the Y-axis direction. In addition, the length of the second substrate 45 in the direction along the X-axis is shorter than the length of the first substrate 41 in the direction along the X-axis. The size of the second substrate 45 is not limited thereto. For example, the length of the second substrate 45 along the X-axis direction may also be longer than the length of the first substrate 41 along the X-axis direction.

The first antenna pattern 46 is mounted on the second substrate 45 . The first antenna pattern 46 of this embodiment is a wiring pattern formed on the second substrate 45 . The first antenna pattern 46 may also be formed of other materials such as insulated copper wire. The first antenna pattern 46 included in the wireless antenna 23 is a loop antenna formed in a coil shape. In this embodiment, the first antenna pattern 46 is formed in a substantially quadrilateral ring shape. In addition, the first antenna pattern 46 may be formed in another shape such as a ring shape.

The first antenna pattern 46 as a loop antenna is formed of a conductor (wiring pattern) extending to surround the inner area of the first antenna pattern 46 . In the first antenna pattern 46, the conductor may surround the inner region of the first antenna pattern 46, or may be wound shorter than one turn. In other words, the inner area of the first antenna pattern 46 and the outer area of the first antenna pattern 46 may also communicate. The conductor can also be wound with multiple turns. The first antenna pattern 46 generates a magnetic flux passing through the inside of the first antenna pattern 46 by applying a voltage to the end of the conductor. In addition, when the magnetic flux passes through the inside of the first antenna pattern 46, a voltage is generated in the conductor. In this way, the first antenna pattern 46 communicates with an external device through electromagnetic induction.

The second substrate 45 includes a first portion P1, a second portion P2, and a third portion P3. The first to third parts P1 to P3 may also be called, for example, regions or ranges, respectively.

The first part P1 is a part of the second substrate 45 on which the first antenna pattern 46 is mounted. Described in detail, the first portion P1 is a portion of the second substrate 45 that overlaps the first antenna pattern 46 when viewing the connection surface 45a of the second substrate 45 in plan view as shown in FIG. 3 .

The second portion P2 is a part of the second substrate 45 surrounded by the first portion P1. The third portion P3 is a part of the second substrate 45 surrounding the first portion P1. In other words, the third portion P3 is located between the first portion P1 and the end portion 45 b of the second substrate 45 . The first part P1 is located between the second part P2 and the third part P3.

As shown by the dashed line in FIG. 3 , two first pads 71 and two second pads 72 are provided on the second surface 41 b of the first substrate 41 . The two first pads 71 are an example of a plurality of first pads, and may also be called, for example, patterns, lands, conductors, or metal parts. The two second pads 72 are respectively an example of the second pads, and may also be called, for example, patterns, bonding areas, conductors or metal parts.

As shown in FIG. 2 , a circuit C is provided on the first substrate 41 . Circuit C includes: I/F terminal 22 , communication controller 24 , flash memory 25 , memory controller 26 , two first pads 71 in FIG. 3 , and various wirings and electronic components provided on first substrate 41 . That is, the circuit C is a portion provided on the first substrate 41 and through which, for example, a current supplied from the outside or induced inside the SD card 11 flows.

The two first pads 71 of FIG. 3 are included in the circuit C as described above. On the other hand, the two second pads 72 are electrically independent from the circuit C, respectively. That is, when the current flows in the circuit C, no current flows in the respective second pads 72 . Furthermore, the second pad 72 may also be connected to the ground.

The first antenna pattern 46 of the antenna module 42 has two third pads 75 . Furthermore, the second substrate 45 has two fourth pads 76 . The third and fourth pads 75, 76 are indicated by dotted lines in FIG. 3 . The two third pads 75 are an example of a plurality of third pads, which may also be called, for example, patterns, lands, conductors or metal parts. The two fourth pads 76 are examples of fourth pads, and may also be called patterns, bonding areas, conductors or metal parts, for example.

The two third pads 75 are two terminals of the first antenna pattern 46 . In other words, one third pad 75 is provided at one end of the first antenna pattern 46 . Another third pad 75 is provided at the other end of the first antenna pattern 46 .

The two fourth pads 76 are electrically independent from the first antenna pattern 46 respectively. For example, when current flows in the first antenna pattern 46 , no current flows in each of the fourth pads 76 . Furthermore, the fourth pad 76 may also be connected to the ground.

A third pad 75 and a fourth pad 76 are respectively disposed on the second portion P2 of the second substrate 45 . Another third pad 75 and another fourth pad 76 are respectively provided on the third portion P3 of the second substrate 45 . In this way, at least one of the two third pads 75 and the two fourth pads 76 is disposed on the second part P2, and at least one of the two third pads 75 and the two fourth pads 76 A pad is provided on the third portion P3. Furthermore, the two third pads 75 and the two fourth pads 76 may also be all disposed on the second portion P2 or the third portion P3.

The third pad 75 and the fourth pad 76 are provided on the connection surface 45 a of the second substrate 45 . The two third pads 75 are respectively soldered to the corresponding first pads 71 of the first substrate 41 through the flux 78 shown in FIG. 4 . The two fourth pads 76 are respectively soldered to the corresponding second pads 72 of the first substrate 41 by solder 78 .

The first antenna pattern 46 is electrically connected to the circuit C of the first substrate 41 by soldering the third pad 75 to the first pad 71 . The first antenna pattern 46 is electrically connected to the communication controller 24, for example. On the other hand, the second pad 72 and the fourth pad 76 soldered to each other are electrically independent from the circuit C and the first antenna pattern 46 .

The antenna module 42 is mounted on the first substrate 41 by soldering the third and fourth pads 75 and 76 to the first and second pads 71 and 72 respectively. The third pad 75 is fixed to the corresponding first pad 71 by solder 78 . Furthermore, the fourth pad 76 is fixed to the corresponding second pad 72 by solder 78 .

When the first surface 41 a of the first substrate 41 is viewed from above as shown in FIG. 3 , a part of the first antenna pattern 46 overlaps the first substrate 41 . In addition, when the first surface 41 a is viewed from above, a part of the first part P1 , a part of the second part P2 , and a part of the third part P3 of the second substrate 45 overlap the first substrate 41 , respectively.

In addition, when the first surface 41a of the first substrate 41 is viewed from above as shown in FIG. In other words, a part of the inner side 46 a of the first antenna pattern 46 does not overlap with the first substrate 41 in a plan view of the first surface 41 a. The inner side 46a of the first antenna pattern 46 is an area surrounded by the circular first antenna pattern 46 . The inner side 46a may also be empty. In addition, objects may also exist on the inner side 46a. In addition, when viewing the first surface 41 a of the first substrate 41 in a plan view, a part of the first antenna pattern 46 is located outside the first substrate 41 .

According to another form of expression, when the first surface 41 a of the first substrate 41 is viewed from above as shown in FIG. 3 , a part of the second portion P2 of the second substrate 45 is located outside the first substrate 41 . When the first surface 41a is viewed from above as in FIG. 3 , the inner side 46a of the first antenna pattern 46 substantially coincides with the second portion P2. Furthermore, the inner side 46a of the first antenna pattern 46 may also be different from the second portion P2.

As shown in FIG. 4 , a part of the inner side 46 a of the first antenna pattern 46 outside the first substrate 41 faces the bottom cover 32 and the top cover 33 along the Z-axis. In other words, a part of the inner side 46a of the first antenna pattern 46 outside the first substrate 41 overlaps the bottom cover 32 and the top cover 33 made of resin in the direction along the Z axis.

As shown in FIG. 3 , on the first surface 41 a of the first substrate 41 , a plurality of connection pads 81 are provided. Each of the plurality of connection pads 81 is an example of a connection pad, and may also be called, for example, a pattern, a land, a conductor, or a metal part. To each of the plurality of connection pads 81, the terminals of the corresponding communication controller 24, flash memory 25, or memory controller 26 are electrically connected by, for example, soldering. Furthermore, the connection pads 81 may also be provided on the second surface 41b.

The first leads 82 respectively extend from the plurality of connection pads 81 . The first lead 82 is covered, for example, with the first solder resist 83 of the first substrate 41 . The first solder resist 83 forms at least a part of the first surface 41 a of the first substrate 41 . For illustration, the first lead 82 is indicated by a two-dot chain line in FIG. 3 .

The first leads 82 extend from the corresponding connection pads 81 toward the end surface 41 c of the first substrate 41 . In other words, the first lead 82 extends toward the edge of the first surface 41 a of the first substrate 41 . The first lead 82 may also have a plurality of bent portions. The end portion of the first lead 82 is away from the end edge of the first surface 41a.

In the first solder resist 83, a plurality of first openings 84 are provided. The first opening 84 is, for example, a notch extending from the edge of the first surface 41 a of the first substrate 41 . The first opening 84 may be a hole.

When the first surface 41 a of the first substrate 41 is viewed from above as in FIG. 3 , the end of the first lead 82 substantially overlaps the edge of the first solder resist 83 forming the first opening 84 . In addition, the end portion of the first lead wire 82 may also be arranged at another position. The first opening 84 is used when the first lead 82 is etched back.

As shown in FIG. 4 , the sealing resin 86 covers the first surface 41 a of the first substrate 41 , the communication controller 24 , the flash memory 25 and the memory controller 26 . The sealing resin 86 is, for example, a synthetic resin, and closely adheres to the first surface 41 a of the first substrate 41 , the communication controller 24 , the flash memory 25 , and the memory controller 26 . The sealing resin 86 covers the first opening 84 of the first solder resist 83 . In addition, FIG. 3 shows the first substrate 41 with the sealing resin 86 omitted.

In the SD card 11 described above, the wireless antenna 23 (first antenna pattern 46 ) of FIG. 2 generates current or voltage by electromagnetic induction when receiving radio waves transmitted from the wireless communication host device 13 . The wireless antenna 23 supplies the generated electric power to the communication controller 24 .

The wireless antenna 23 of the present embodiment is set corresponding to a predetermined frequency or frequency band corresponding to NFC. The first antenna pattern 46 and part of the inner side 46a of the wireless antenna 23 overlap the first substrate 41 along the Z-axis, so the frequency or frequency band of radio waves received by the first antenna pattern 46 may be shifted. The frequency or frequency band of this radio wave is adjusted by the capacitor 27, for example.

The wireless antenna 23 transmits data received from the wireless communication host device 13 to the communication controller 24 . Furthermore, the wireless antenna 23 transmits the data received from the communication controller 24 to the wireless communication host device 13 .

The communication controller 24 can communicate with the wireless communication host device 13 via the wireless antenna 23 . The communication controller 24 controls NFC using the wireless antenna 23 for the wireless communication host device 13 .

The communication controller 24 can operate using the electric power generated in the wireless antenna 23 by the above-mentioned electromagnetic induction. The communication controller 24 receives a signal or data represented by a current or a voltage generated in the wireless antenna 23 based on radio waves from the wireless communication host device 13 , and operates based on the signal or data. For example, the communication controller 24 receives data at a predetermined frequency corresponding to NFC from the wireless communication host device 13 via the wireless antenna 23 during operation, and writes the data into the storage unit 24a. In addition, the communication controller 24 reads the data written in the storage unit 24 a during operation, and transmits the data to the wireless communication host device 13 via the wireless antenna 23 . More specifically, the communication controller 24 can perform NFC-based communication when receiving a signal of a predetermined frequency corresponding to NFC via the wireless antenna 23 .

When writing to the flash memory 25 , the communication controller 24 transmits data received from the host device 12 via the I/F terminal 22 to the memory controller 26 . When reading the flash memory 25 , the communication controller 24 transmits the data received from the memory controller 26 to the host device 12 via the I/F terminal 22 .

For example, when the SD card 11 is electrically connected to the host device 12 , sufficient power is supplied to the communication controller 24 . In this case, the communication controller 24 can write the data received by NFC from the wireless communication host device 13 via the wireless antenna 23 into the flash memory 25 via the memory controller 26 .

When sufficient power is supplied to the communication controller 24, the communication controller 24 can read the data written into the flash memory 25 via the memory controller 26 to generate data, and write the data into the storage unit 24a.

When enough power is supplied to the communication controller 24, the communication controller 24 can read a part or all of the data written into the flash memory 25 through the memory controller 26, and pass the read data through the wireless antenna. 23 and sent to the wireless communication host device 13.

The storage unit 24a is a low-power memory that can be operated using electric power generated by the wireless antenna 23 . The storage unit 24a is, for example, a nonvolatile memory. The storage unit 24 a stores data based on control performed by the communication controller 24 or the memory controller 26 . In addition, the storage unit 24a may be a memory for temporarily storing data. The storage unit 24 a is, for example, EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory). The storage unit 24a may be another memory.

As described above, the communication controller 24 and the storage unit 24 a can operate using electric power induced in the wireless antenna 23 by the radio wave from the wireless communication host device 13 . However, the communication controller 24 and the storage unit 24 a may operate using the power supplied from the host device 12 when the power is supplied from the host device 12 to the SD card 11 .

The voltage detector 24b monitors the voltage supplied from the wireless antenna 23 to the communication controller 24, and continues to output a reset signal for communication by NFC until the voltage reaches a predetermined value. Thereby, abnormal startup and abnormal operation of communication by NFC can be suppressed.

The flash memory 25 is, for example, a NAND type flash memory. Furthermore, the nonvolatile memory is not limited to NAND flash memory, and may be NOR flash memory, magnetoresistive random access memory (MRAM), phase change memory (Phase Change Random Access Memory: PRAM), resistance change memory (Resistive Random Access Memory: ReRAM), or other nonvolatile memories such as ferroelectric random access memory (FeRAM).

The memory controller 26 controls writing of data to and reading from the flash memory 25 . More specifically, the memory controller 26 writes the data into the flash memory 25 when receiving a write command and data from the host device 12 via the I/F terminal 22 and the communication controller 24 . When the memory controller 26 receives a read command from the host device 12 through the I/F terminal 22 and the communication controller 24, it reads data from the flash memory 25 and passes the data through the communication controller 24 and the I/F The terminal 22 sends to the host device 12 .

When, for example, the SD card 11 is electrically connected to the host device 12 , sufficient power is supplied to the memory controller 26 . In this case, the memory controller 26 can write data received from the wireless communication host device 13 via the wireless antenna 23 and the communication controller 24 into the flash memory 25 . When sufficient power is supplied to the memory controller 26 , the memory controller 26 can transmit the data read from the flash memory 25 to the wireless communication host device 13 via the communication controller 24 and the wireless antenna 23 .

The flash memory 25 and the memory controller 26 operate using power supplied from the host device 12 .

Capacitor 27 has, for example, two terminals. One terminal is electrically connected to one end of the wireless antenna 23 . The other terminal is electrically connected to the other end of the wireless antenna 23 .

The capacitor 27 adjusts the frequency of the current or voltage generated at the wireless antenna 23 . More specifically, the capacitor 27 adjusts the frequency shift of NFC caused by the first antenna pattern 46 and part of the inner side 46a of the wireless antenna 23 overlapping the first substrate 41 in the direction along the Z axis.

The above-mentioned data, for example, can be the data sent and received between the wireless communication host device 13 and the SD card 11 along the NFC interface, can also be the feature data of the data written into the flash memory 25, or can be sent from the wireless communication host device 13 via The feature data received by the communication controller 24 through the wireless antenna 23 may also be feature data related to the flash memory 25 or feature data related to the SD card 11 . To be more specific, the data may also be, for example: a part (for example, initial or final) data of image data written into the flash memory 25, thumbnail image data, management information of data written into the flash memory 25, storage capacity of the flash memory 25, flash memory 25, etc. The remaining capacity of 25, the name of the file written in the flash memory 25, the generation time of the data, the shooting time data when the data is image data, and the number of files written in the flash memory 25.

In this embodiment, the write instruction and data from the host device 12 are first received by the communication controller 24 and then received by the memory controller 26 . This is because, first, the communication controller 24 judges whether the writing instruction and the data are received from the host device 12 or the wireless communication host device 13, and switches operations based on the judgment result.

As described above, the SD card 11 transmits and receives data with the wireless communication host device 13 using the electric power generated by the electromagnetic induction of the wireless antenna 23 . Specifically, in NFC, magnetic flux passes through the inner side 46a of the first antenna pattern 46 of the wireless antenna 23, thereby generating electric power at the first antenna pattern 46, and the communication controller 24 receives the electric current generated at the first antenna pattern 46 or A signal or data represented by voltage. Furthermore, the communication controller 24 transmits data to the wireless communication host device 13 by generating a magnetic flux passing through the inner side 46 a of the first antenna pattern 46 of the wireless antenna 23 .

As shown in FIG. 3 , a part of the inner side 46 a of the first antenna pattern 46 is located outside the first substrate 41 in a plan view of the first surface 41 a of the first substrate 41 . Therefore, the magnetic flux passing through the inner side 46 a of the first antenna pattern 46 can be suppressed from being affected by the first substrate 41 and the communication controller 24 , flash memory 25 , and memory controller 26 mounted on the first substrate 41 .

In the SD card 11 according to the first embodiment, the first antenna pattern 46 provided on the antenna module 42 is connected to the first substrate 41 . Generally, a loop antenna like the first antenna pattern 46 is less expensive than a chip antenna. Therefore, for example, compared with a case where a chip antenna is mounted on the first substrate 41 instead of the first antenna pattern 46, an increase in the manufacturing cost of the SD card 11 can be suppressed. Furthermore, the first antenna pattern 46 which is a loop antenna generates magnetic flux over a larger range than the chip antenna. Therefore, the area in which communication by NFC can be ensured is large. In addition, at least a part of the first antenna pattern 46 is located outside the first substrate 41 in a plan view of the first surface 41 a. Accordingly, it is possible to suppress the magnetic flux generated by the first antenna pattern 46 from being affected by electronic components such as the flash memory 25 mounted on the first substrate 41 and the pattern of the first substrate 41 . Furthermore, the size of the first substrate 41 which is a PCB can be reduced, and an increase in the manufacturing cost of the SD card 11 can be suppressed.

At least a part of the first antenna pattern 46 is located outside the first substrate 41 in a plan view of the first surface 41 a. Thereby, the magnetic flux passing through the inner side 46a of the first antenna pattern 46 can be suppressed from being affected by electronic components such as the flash memory 25 mounted on the first substrate 41 and the pattern of the first substrate 41 .

The SD card 11 has a second substrate 45 different from the first substrate 41 on which the first antenna pattern 46 is mounted. Thus, the antenna module 42 having the first antenna pattern 46 mounted on the second substrate 45 can be manufactured separately from the first substrate 41 in advance. By mounting the antenna module 42 on the first substrate 41 , the first antenna pattern 46 is easily connected to the first substrate 41 .

The first antenna pattern 46 is electrically connected to the circuit C by soldering the plurality of third pads 75 to the plurality of first pads 71 . Furthermore, the fourth pad 76 of the second substrate 45 is soldered to the second pad 72 provided on the first substrate 41 . Thereby, for example, the antenna module 42 can be mounted on the first substrate 41 more firmly than in a case where only the third pad 75 is soldered to the first pad 71 . Furthermore, even if the dimensional accuracy of the first and second recesses 55 and 56 for positioning the first substrate 41 and the antenna module 42 decreases, the electrical connection between the first substrate 41 and the first antenna pattern 46 can be ensured.

At least one of the plurality of third pads 75 and fourth pads 76 is disposed on the second portion P2, and at least another of the plurality of third pads 75 and fourth pads 76 is disposed on the third portion P3. Thereby, the second substrate 45 can be suppressed from detaching from the first substrate 41 , and the plurality of first pads 71 can be suppressed from detaching from the plurality of third pads 75 .

The second substrate 45 is thinner than the first substrate 41 . Accordingly, when the first antenna pattern 46 mounted on the second substrate 45 overlaps with the first substrate 41 , it is possible to suppress the SD card 11 from becoming thicker.

Generally, the influence on the magnetic flux of the first antenna pattern 46 due to the overlap between the first antenna pattern 46 and the first substrate 41 is greater than the influence on the first antenna pattern 46 due to the overlap between the inner side 46a of the first antenna pattern 46 and the first substrate 41. The influence of the magnetic flux of the antenna pattern 46 is small. In the present embodiment, at least a part of the first antenna pattern 46 overlaps with the first substrate 41 (is located on the first substrate 41 ) in a plan view of the first surface 41 a. Therefore, when the first antenna pattern 46 and the inner side 46a of the first antenna pattern 46 are enlarged, the influence of the magnetic flux on the first antenna pattern 46 due to the first substrate 41 can be suppressed.

The bottom cover 32 is provided with a first recess 55 for accommodating the first substrate 41 and a second recess 56 for accommodating the antenna module 42 and the first antenna pattern 46 mounted on the antenna module 42 . Accordingly, by accommodating the first substrate 41 and the first antenna pattern 46 in the first and second recesses 55 , 56 , positioning of the first substrate 41 and the first antenna pattern 46 relative to the housing 31 can be easily performed.

(second embodiment)

Next, a second embodiment will be described with reference to FIGS. 5 to 11 . In addition, in the following description of several embodiments, the component which has the same function as the component already demonstrated may be attached|subjected with the same code|symbol as the component already mentioned, and description is abbreviate|omitted. In addition, a plurality of constituent elements attached with the same symbols are not limited to having the same functions and properties, and may have different functions and properties corresponding to the respective embodiments.

FIG. 5 is a plan view showing the SD card 11 according to the second embodiment with the top cover 33 removed. Like the first embodiment, the first surface 41 a of the first substrate 41 , the communication controller 24 , the flash memory 25 , the memory controller 26 , the first solder resist 83 , and the first opening 84 are covered with the sealing resin 86 . The sealing resin 86 of the second embodiment is an example of a covering member.

FIG. 6 is a plan view showing the first substrate 41 of the second embodiment with the sealing resin 86 removed. FIG. 7 is a bottom view showing the first substrate 41 of the second embodiment. FIG. 8 is a cross-sectional view schematically showing a part of the first substrate 41 according to the second embodiment along the line F8 - F8 in FIG. 6 .

As shown in FIG. 8 , the first substrate 41 has the aforementioned first solder resist 83 , base substrate 91 , and second solder resist 92 . The base substrate 91 may also be called, for example, a base material. In addition, the first substrate 41 may have more layers than the configuration shown in FIG. 8 .

The base substrate 91 is, for example, an insulating board made of paper or glass cloth covered with a synthetic resin. The base substrate 91 can also be made of other materials. The base substrate 91 has a first forming surface 91 a and a second forming surface 91 b. The first forming surface 91a is an example of a forming surface.

The first forming surface 91 a is a substantially flat surface facing the top cover 33 . The first formation surface 91 a forms a part of the first surface 41 a of the first substrate 41 . The first formation surface 91 a is covered with the first solder resist 83 . The first solder resist 83 of the second embodiment is an example of a solder resist. The first solder resist 83 forms a part of the first surface 41 a of the first substrate 41 .

The second forming surface 91 b is a substantially flat surface facing the bottom cover 32 . The second forming surface 91b is located on the opposite side to the first forming surface 91a. The second formation surface 91 b forms a part of the second surface 41 b of the first substrate 41 . The second formation surface 91b is covered with the second solder resist 92 . The second solder resist 92 forms a part of the second surface 41 b of the first substrate 41 .

As shown in FIG. 6 , the first substrate 41 of the second embodiment has a second antenna pattern 101 . The second antenna pattern 101 is an example of a second antenna. The second antenna pattern 101 has: a first pattern 101a, a second pattern 101b and a third pattern 101c. The second pattern 101b is an example of the first wiring. The first pattern 101a and the third pattern 101c are respectively an example of the second wiring.

The first pattern 101 a and the third pattern 101 c shown in FIG. 7 are provided on the second formation surface 91 b of the base substrate 91 . In other words, the first pattern 101 a and the third pattern 101 c are mounted on the second surface 41 b of the first substrate 41 .

The second pattern 101 b shown in FIG. 6 is provided on the first forming surface 91 a of the base substrate 91 . In other words, the second pattern 101b is mounted on the first surface 41a of the first substrate 41 .

As shown in FIG. 7 , one end of the first pattern 101 a is electrically connected to one end of the second pattern 101 b through a first via 102 . One end of the third pattern 101c is electrically connected to the other end of the second pattern 101b through the second via hole 103 . In this way, the first to third patterns 101a, 101b, 101c form a continuous second antenna pattern 101 . The second antenna pattern 101 extends adjacent to the end surface 41c of the first substrate 41 . The second antenna pattern 101 extends adjacent to, for example, the right end portion 11d, the front end portion 11a, and the left end portion 11c of the SD card 11 .

As shown in FIG. 7 , at least a part of the second pattern 101 b overlaps the plurality of I/F terminals 22 in a plan view of the second surface 41 b of the first substrate 41 . Similarly, when viewing the first surface 41 a of the first substrate 41 in a plan view, at least a part of the second pattern 101 b overlaps the plurality of I/F terminals 22 .

At the other end portion of the first pattern 101a, a fifth pad 105 is formed. At the other end of the third pattern 101c, a sixth pad 106 is formed. In other words, the fifth and sixth pads 105 and 106 are formed at both ends of the second antenna pattern 101 . The fifth and sixth pads 105 , 106 are disposed on the second surface 41 b of the first substrate 41 .

As shown in FIG. 5, the first antenna pattern 46 of the antenna module 42 has: a first rolled portion 46b and a second rolled portion 46c. The first rolled portion 46b and the second rolled portion 46c are parts of the coiled first antenna pattern 46, respectively.

The first antenna pattern 46 also has a seventh pad 107 and an eighth pad 108 . The seventh pad 107 and the eighth pad 108 are disposed on the connection surface 45 a of the second substrate 45 .

The seventh pad 107 is provided at one end of the first roll portion 46 b of the first antenna pattern 46 . At the other end portion of the first roll portion 46b, a third pad 75 is provided. The eighth pad 108 is provided at one end of the second roll portion 46c of the first antenna pattern 46 . At the other end portion of the second rolled portion 46c, another third pad 75 is provided.

As described above, the first antenna pattern 46 is composed of a pattern formed in a coil shape. In the second embodiment, the pattern forming the first antenna pattern 46 is divided into a first roll portion 46b and a second roll portion 46c.

The seventh pad 107 and the eighth pad 108 are disposed on the third portion P3 of the second substrate 45 . Furthermore, at least one of the seventh pad 107 and the eighth pad 108 may be disposed on the second portion P2.

The seventh pad 107 of the second substrate 45 is soldered to the fifth pad 105 of the first substrate 41 . Furthermore, the eighth pad 108 of the second substrate 45 is soldered to the sixth pad 106 of the first substrate 41 .

The first roll portion 46b of the first antenna pattern 46 is electrically connected to the first pattern 101a of the second antenna pattern 101 by soldering the seventh pad 107 to the fifth pad 105 . Furthermore, by soldering the eighth pad 108 to the sixth pad 106, the second rolled portion 46c of the first antenna pattern 46 is electrically connected to the third pattern 101c of the second antenna pattern 101. In other words, the first antenna pattern 46 is electrically connected to the second antenna pattern 101 .

The second antenna pattern 101 is connected to the first antenna pattern 46 to form a loop antenna 111 together with the first antenna pattern 46 . That is, the loop antenna 111 has a third pad 75, a first volume 46b, a seventh pad 107, a fifth pad 105, a first pattern 101a, a first via hole 102, and a second pattern 101b electrically connected to each other. , the second via hole 103 , the third pattern 101 c , the sixth pad 106 , the eighth pad 108 , the second roll portion 46 c and another third pad 75 . In the second embodiment, the wireless antenna 23 of FIG. 2 has a loop antenna 111 .

The loop antenna 111 is formed of a conductor (the first antenna pattern 46 and the second antenna pattern 101 ) extending to surround the inner area of the loop antenna 111 . In the loop antenna 111, the conductor only needs to surround the inner area of the loop antenna 111, or may be wound shorter than one turn. In other words, the inner area of the loop antenna 111 and the outer area of the loop antenna 111 may also communicate. The conductor can be wound multiple times. The loop antenna 111 generates a magnetic flux passing through the inside of the loop antenna 111 by applying a voltage to the end of the conductor. In addition, when the magnetic flux passes through the inside of the loop antenna 111, a voltage is generated in the conductor. In this way, the loop antenna 111 communicates with an external device through electromagnetic induction.

As shown in FIG. 6 , the first substrate 41 has a plurality of first regions A1 and second regions A2. The plurality of first areas A1 and second areas A2 may also be called, for example, sections or areas, respectively. The plurality of first areas A1 and second areas A2 are respectively surrounded by the loop antenna 111 .

Each of the plurality of first regions A1 is the first substrate 41 that overlaps with at least one of the communication controller 24 , flash memory 25 , and memory controller 26 in a plan view of the first surface 41 a of the first substrate 41 as shown in FIG. 6 . a part of.

The plurality of first areas A1 are respectively surrounded by the second area A2 and separated from the loop antenna 111 . In other words, the communication controller 24 , the flash memory 25 and the memory controller 26 are separated from the loop antenna 111 . Furthermore, at least one of the communication controller 24 , the flash memory 25 and the memory controller 26 may be adjacent to the loop antenna 111 .

The second area A2 is a part of the first substrate 41 surrounded by the loop antenna 111 and separated from the plurality of first areas A1 in plan view of the first surface 41 a. In this way, the portion surrounded by the loop antenna 111 of the first substrate 41 is divided into a plurality of first areas A1 or second areas A2. In the portion surrounded by the loop antenna 111 of the first substrate 41, other areas different from the first and second areas A1 and A2 may be provided.

FIG. 9 is a cross-sectional view schematically showing a part of the first substrate 41 according to the second embodiment along the line F9 - F9 in FIG. 6 . As shown in FIG. 9 , a ground line 113 is provided on the first substrate 41 . The ground wire 113 may also be called, for example, a ground wire pattern, a ground wire layer, or a conductor. The ground line 113 is provided, for example, on the first formation surface 91 a of the base substrate 91 . The ground wire 113 can also be disposed on the second forming surface 91b.

The ground wires 113 are respectively disposed in the plurality of first regions A1. In other words, the ground wire 113 is disposed outside the second area A2. Furthermore, a part of the ground wire 113 may also be disposed in the second area A2. In addition, the ground wire 113 may also be provided on a portion of the first substrate 41 surrounding the loop antenna 111 .

As shown in FIG. 6 , the first leads 82 extend from the plurality of connection pads 81 , respectively. FIG. 6 omits a portion of the first lead 82 extending from the connection pad 81 . 6 shows a part of each of the plurality of first leads 82 extending from the connection pad 81 hidden under the communication controller 24 , the flash memory 25 and the memory controller 26 .

A plurality of first leads 82 are disposed on the first forming surface 91a. Therefore, the first solder resist 83 covers the first leads 82 . FIG. 6 shows the first lead 82 by a dashed-two dotted line for explanation.

Several first leads 82 extend from corresponding connection pads 81 to the second antenna pattern 101 . The other first leads 82 extend toward the edge of the first surface 41 a of the first substrate 41 . The plurality of first leads 82 may respectively have a plurality of bent portions.

FIG. 10 is a plan view showing a part of the first substrate 41 of the second embodiment. As shown in FIG. 10 , each of the plurality of first leads 82 has a first end portion 82a. The first end portion 82 a is an end portion of the first lead 82 extending from the connection pad 81 . In other words, the first end portion 82 a is located on the opposite side of the connection pad 81 .

The first end portion 82a is away from other conductors including the second antenna pattern 101 . Specifically, the first end portion 82 a of the first lead 82 is separated from a conductive portion of a member or component different from the first lead 82 . Therefore, the first leads 82 are electrically separated from other electrical conductors different from the connection pads 81 .

When the first surface 41 a of the first substrate 41 is viewed from above as shown in FIG. 10 , the first end portion 82 a substantially overlaps the edge of the first solder resist 83 forming the first opening 84 . In addition, the first end portion 82a may also be arranged at other positions. The first opening 84 in the second embodiment is a hole. Furthermore, the first opening 84 may also be a notch.

As shown in FIG. 8 , wiring 114 is mounted on the first substrate 41 . The wiring 114 is an example of the first conductive pattern. The wiring 114 is provided, for example, on the first formation surface 91 a of the base substrate 91 and extends from the connection pad 81 . In other words, the wiring 114 is connected to the connection pad 81 .

The wiring 114 electrically connects the connection pad 81 and another conductor different from the connection pad 81 . For example, the wiring 114 extending from the connection pad 81 on which the communication controller 24 is mounted electrically connects the connection pad 81 and the first pad 71 . The wiring 114 extending from the connection pad 81 on which the flash memory 25 is mounted electrically connects the connection pad 81 to the connection pad 81 on which the memory controller 26 is mounted. The wiring 114 can connect the connection pad 81 to other conductors such as the I/F terminal 22 , the capacitor 27 , other electronic components, or other terminals.

The second lead 115 extends from the second antenna pattern 101 . The second lead 115 is disposed on the first forming surface 91a. Therefore, the first solder resist 83 covers the second lead 115 . FIG. 10 shows the second lead 115 by a two-dot chain line for explanation.

The second lead 115 has a second end portion 115a. The second end portion 115 a is an end portion of the second lead 115 extending from the second antenna pattern 101 . In other words, the second end portion 115a is located on the opposite side of the second antenna pattern 101 .

The second end portion 115 a is away from other electrical conductors including the first end portion 82 a of the first lead 82 . Therefore, the second lead 115 is electrically separated from other conductors different from the second antenna pattern 101 . When the first surface 41 a of the first substrate 41 is viewed from above as shown in FIG. 10 , the second end portion 115 a substantially overlaps the edge of the first solder resist 83 forming the first opening 84 . Furthermore, the second end portion 115a can also be disposed at other positions.

The number of first leads 82 is greater than the number of second leads 115 . At the edge of the first solder resist 83 forming one first opening 84 , the first end portions 82 a of the plurality of first leads 82 and the second end portion 115 a of one second lead 115 substantially overlap. When the first opening 84 is viewed from above the first surface 41a of the first substrate 41 as shown in FIG. overlapping.

The third lead 116 also extends from the second antenna pattern 101 . The third lead 116 is disposed on the first forming surface 91a. Therefore, the first solder resist 83 covers the third lead 116 . FIG. 10 shows the third lead 116 by a two-dot chain line for explanation.

The third lead 116 is located between the second antenna pattern 101 and the end surface 41c of the first substrate 41 . The third lead 116 extends from the second antenna pattern 101 toward the end surface 41c of the first substrate 41 . In other words, the third lead 116 extends from the second antenna pattern 101 to the edge of the first surface 41 a of the first substrate 41 .

The third lead 116 has a third end portion 116a. The third end portion 116 a is an end portion of the third lead 116 extending from the second antenna pattern 101 . In other words, the third end portion 116a is located on the opposite side of the second antenna pattern 101 .

In the first solder resist 83, a second opening 119 is provided. The second opening 119 is, for example, a notch extending from the edge of the first surface 41 a of the first substrate 41 . The second opening 119 may also be a hole.

When the first surface 41a of the first substrate 41 is viewed from above as shown in FIG. 10 , the third end portion 116a of the third lead 116 substantially overlaps the edge of the first solder resist 83 forming the second opening 119 . The third end portion 116a is away from other electrical conductors. Therefore, the third lead 116 is electrically separated from other conductors different from the second antenna pattern 101 . Furthermore, the third end portion 116a can be disposed at other positions. The second opening 119 is covered with the sealing resin 86 similarly to the first opening 84 .

As described above, in the present embodiment, the first to third leads 82 , 115 , and 116 are mounted on the first formation surface 91 a of the first substrate 41 . However, the first to third leads 82, 115, and 116 may be mounted on other locations such as the second formation surface 91b.

As mentioned above, the fifth pad 105 and the sixth pad 106 are formed at both ends of the second antenna pattern 101 . In other words, the fifth and sixth pads 105 and 106 are respectively connected to the second antenna pattern 101 .

The fifth pad 105 electrically connects the second antenna pattern 101 and the seventh pad 107 . The sixth pad 106 electrically connects the second antenna pattern 101 and the eighth pad 108 . Thus, the fifth and sixth pads 105 and 106 are examples of second conductive patterns that electrically connect the second antenna pattern 101 to other conductors different from the second antenna pattern 101 . The second conductive pattern is not limited to the fifth and sixth pads 105 and 106, and may be other conductive patterns.

A part of the method for manufacturing the first substrate 41 according to the second embodiment will be exemplified below. In addition, the manufacturing method of the 1st board|substrate 41 is not limited to the following method, You may use another method.

FIG. 11 is a plan view showing a part of the first substrate 41 in one of the manufacturing steps of the second embodiment. Before forming the plurality of connection pads 81 on the first substrate 41 , the first plating lead L1 and the second plating lead L2 shown in FIG. 11 are provided on the first formation surface 91 a of the base substrate 91 .

On the base substrate 91 on which the first and second plating leads L1 and L2 are provided, a plurality of connection pads 81 and other plurality of pads are formed by electrolytic plating. The first and second plating leads L1 and L2 are provided, for example, to form a plurality of connection pads 81 and other plurality of pads by electrolytic plating.

The first plating lead L1 includes the aforementioned plurality of first leads 82 and second leads 115 . In other words, the plurality of first and second leads 82 and 115 connected to each other form the first plating lead L1.

The first plating lead L1 extends from the second antenna pattern 101 , has a plurality of branched portions, and is connected to a plurality of connection pads 81 . In other words, the connection pads 81 are formed by electrolytic plating at a plurality of end portions of the first plating lead L1.

The second plating lead L2 includes the third lead 116 described above. The second plating lead L2 extends from the second antenna pattern 101 to the end surface 41c of the first substrate 41 . The second plating lead L2 is electrically connected to the plurality of connection pads 81 through the second antenna pattern 101 and the first plating lead L1. In other words, the potentials of the second plating lead L2 and the second antenna pattern 101, the first plating lead L1, and the plurality of connection pads 81 are respectively equal. Furthermore, the potentials of the second plating lead L2 and the second antenna pattern 101 , the first plating lead L1 , and the plurality of connection pads 81 may also be different.

When the connection pad 81 is formed by electrolytic plating, the second plating lead L2 is connected to a power source. For example, before the plurality of first substrates 41 are cut out from one collective substrate, a lead connected to the second plating lead L2 of each first substrate 41 is mounted on the collective substrate including the plurality of first substrates 41 . A voltage is applied to the second plating lead L2 via this lead by clamping the collective substrate by a jig connected to a power source. The connection pad 81 is formed by electrolytic plating by applying a voltage to the first plating lead L1 through the second plating lead L2 and the second antenna pattern 101 . A collective substrate may also be referred to as a frame, strip, sheet or aggregate.

A part of the first plating lead L1 is exposed through the plurality of first openings 84 . The first opening 84 exposes, for example, a portion where the plurality of first leads 82 and the second leads 115 are connected (branched portion). A part of the second plating lead L2 is exposed through the second opening 119 .

When forming the plurality of connection pads 81 , a part of the first plating lead L1 and a part of the second plating lead L2 are removed, for example, by etch back. The first plating lead L1 is etched back through the first opening 84 to be divided into a plurality of first leads 82 and second leads 115 . The second plating lead L2 is etched back through the second opening 119 to form the third lead 116 . Thus, the plurality of connection pads 81 are electrically separated from the second antenna pattern 101 .

Next, the communication controller 24, the flash memory 25, and the memory controller 26 are electrically connected by soldering to the formed connection pads 81, respectively. Furthermore, the sealing resin 86 covers the first surface 41 a of the first substrate 41 , the communication controller 24 , the flash memory 25 , the memory controller 26 , the first solder resist 83 , the first opening 84 , and the second opening 119 . The first substrate 41 is manufactured as described above.

In the SD card 11 according to the second embodiment, the second antenna pattern 101 forming one loop antenna 111 together with the first antenna pattern 46 is mounted on the first substrate 41 . Thus, compared with the case where the SD card 11 has only the first antenna pattern 46, the range in which the magnetic flux is generated from the first antenna pattern 46 and the second antenna pattern 101 is in the direction along the X axis and the direction along the Y axis. As the magnetic flux is expanded, the range in which communication can be performed by the magnetic flux is expanded. Furthermore, since the magnetic flux captured by the loop antenna 111 is larger than that captured by the first antenna pattern 46, the range of communication enabled by the magnetic flux is also expanded in the direction along the Z axis. In this way, the range in which communication by magnetic flux can be performed is expanded, and the communication characteristics of the SD card 11 are improved.

The second antenna pattern 101 has a second pattern 101b mounted on the first forming surface 91a, and first and third patterns 101a and 101c mounted on the second forming surface 91b. Since a part of the second antenna pattern 101 is mounted on the second formation surface 91b, it is possible to suppress a reduction in the range where various electronic components such as the flash memory 25 can be mounted on the first surface 41a.

The first substrate 41 has a first area A1 on which an electronic component such as the flash memory 25 is mounted and a ground line 113 is provided, and a second area A2 separated from the first area A1 . By setting the second area A2, the impact on the loop antenna 111 formed by the first antenna pattern 46 and the second antenna pattern 101 generated by the communication controller 24, the flash memory 25, the memory controller 26 and the ground line 113 is reduced. The influence of magnetic flux.

The first lead 82 extends from the connection pad 81 to which an electronic component such as the flash memory 25 is connected. The first lead 82 is electrically separated from other electrical conductors. On the other hand, the second lead 115 extends from the second antenna pattern 101 . The second lead 115 is electrically separated from other electrical conductors. The first and second leads 82 and 115 are connected, for example, in the manufacturing process of the SD card 11 to form the first plating lead L1. In this case, by applying a voltage to the first and second leads 82 and 115 via the second antenna pattern 101 , the connection pad 81 can be formed at the end of the first lead 82 by electrolytic plating. After the connection pad 81 is formed, the first lead 82 and the second lead 115 are divided. Thus, on the first substrate 41 on which the second antenna pattern 101 is formed, the connection pad 81 can be formed by electrolytic plating of the first and second leads 82 and 115 .

In the first solder resist 83, there is provided a first opening overlapping a region between the first end portion 82a of the first lead 82 and the second end portion 115a of the second lead 115 in a plan view of the first formation surface 91a. 84. Accordingly, in the manufacturing process of the SD card 11 , the first lead 82 and the second lead 115 connected to each other can be divided by, for example, etching back through the first opening 84 .

The sealing resin 86 covers the flash memory 25 , the memory controller 26 and the first opening 84 of the first solder resist 83 . Thus, the sealing resin 86 protects the flash memory 25, the memory controller 26, and the first formation surface 91a, and can suppress damage to the flash memory 25, the memory controller 26, and the first formation surface 91a.

Between the second antenna pattern 101 and the end surface 41 c of the first substrate 41 , a third lead 116 extends from the second antenna pattern 101 . The third lead 116 is electrically isolated from other electrical conductors. The third lead 116 can be connected to a power source during the manufacturing process of the SD card 11, for example. Therefore, by applying a voltage to the first lead 82 through the third lead 116, the second antenna pattern 101, and the second lead 115, the connection pad 81 is formed by electrolytic plating. After the connection pads 81 are formed, the third leads 116 are separated from the leads of the collective substrate. Thus, on the first substrate 41 on which the second antenna pattern 101 is formed, the connection pad 81 can be formed by electrolytic plating of the first and second leads 82 and 115 .

The number of the plurality of first leads 82 is greater than the number of the plurality of second leads 115 . The plurality of first leads 82 are connected to a corresponding one of the second leads 115 during the manufacturing process of the SD card 11 , for example. A plurality of first leads 82 having a first end 82a separated from other conductors and a plurality of first leads 82a separated from other conductors are respectively formed by removing portions where a plurality of first leads 82 and second leads 115 are connected by, for example, etching back. The body leaves the second lead 115 of the second end portion 115a. In this way, an increase in the number of second leads 115 can be suppressed without providing a number of second leads 115 corresponding to the number of first leads 82 . Therefore, the presence of conductors inside the second antenna pattern 101 can be reduced, and the influence of the magnetic flux on the single loop antenna 111 formed by the first antenna pattern 46 and the second antenna pattern 101 can be suppressed.

Next, a modified example of the second embodiment will be described with reference to FIG. 12 . FIG. 12 is a plan view showing the SD card 11 according to a modified example of the second embodiment with the top cover 33 removed.

As shown in FIG. 12 , the end surface 41c of the first substrate 41 includes a front end surface 41ca, a rear end surface 41cb, a left end surface 41cc, and a right end surface 41cd. In addition, the front end surface 41ca, the rear end surface 41cb, the left end surface 41cc, and the right end surface 41cd are referred to based on the positions in FIG.

The front end surface 41ca is one end surface of the first substrate 41 in the direction along the Y axis. The I/F terminal 22 is adjacent to the front end surface 41ca. The rear end surface 41cb is the other end surface of the first substrate 41 in the direction along the Y axis, and is located on the opposite side to the front end surface 41ca. The front end surface 41ca and the rear end surface 41cb extend in the direction along the X-axis.

The left end surface 41cc is one end surface of the first substrate 41 in the direction along the X-axis. The right end surface 41cd is the other end surface of the first substrate 41 in the direction along the X-axis, and is located on the opposite side to the left end surface 41cc. The left end surface 41cc and the right end surface 41cd extend in the direction along the Y axis.

The second antenna pattern 101 extends adjacent to the front end surface 41ca, a part of the rear end surface 41cb, the left end surface 41cc, and the right end surface 41cd of the first substrate 41 . In a portion adjacent to the rear end surface 41cb of the end surface 41c, the second antenna pattern 101 is opened. In other words, the inner region of the second antenna pattern 101 and the outer region of the second antenna pattern 101 communicate at a portion adjacent to the rear end surface 41cb of the end surface 41c. In addition, the shape of the second antenna pattern 101 is not limited thereto.

In the modified example of the second embodiment, the plurality of first leads 82 respectively extend from the connection pads 81 to the rear end surface 41cb of the first substrate 41 . In other words, the first lead 82 extends in a direction away from the front end surface 41ca adjacent to the I/F terminal 22 .

When viewing the first surface 41a of the first substrate 41 in plan view as shown in FIG. 12 , the first end portion 82a of the first lead 82 substantially overlaps the rear end surface 41cb. That is, the first lead 82 extends from the connection pad 81 to the rear end surface 41cb. The first end portion 82a is away from other conductors including the second antenna pattern 101 .

On extension lines of several first leads 82 extending from the connection pad 81, the second antenna pattern 101 sometimes exists. In this case, the first lead 82 has at least one bent portion and extends on a path that does not cross the second antenna pattern 101 . In other words, the first lead wire 82 extends away from the second antenna pattern 101 and departs from the second antenna pattern 101 .

In the modified example of the second embodiment, all the first leads 82 do not cross the second antenna pattern 101 and extend from the connection pad 81 to the rear end surface 41cb. The first lead 82 is electrically separated from another conductor different from the connection pad 81 .

At least one connection pad 81 is closer to any one of the front end surface 41ca, the left end surface 41cc, and the right end surface 41cd than the rear end surface 41cb. That is, the first lead 82 extends from the connection pad 81 to the rear end surface 41cb, not to the front end surface 41ca, the left end surface 41cc, or the right end surface 41cd which is the nearest end surface 41c.

In the modified example of the second embodiment, the first opening 84 is not provided in the first solder resist 83 . Although the first opening 84 may be provided in the first solder resist 83 , as described above, the first end portion 82 a of the first lead 82 overlaps the rear end surface 41 cb in a planar view of the first surface 41 a.

The rear end surface 41cb of the first substrate 41 faces the antenna module 42 having the first antenna pattern 46 . In addition, at least a part of the rear end surface 41cb overlaps with the antenna module 42 in a plan view of the first surface 41a.

The second antenna pattern 101 is connected to the first antenna pattern 46 . In order to make the inner area of the second antenna pattern 101 larger, the second antenna pattern 101 extends adjacent to the front end surface 41ca , the left end surface 41cc and the right end surface 41cd separated from the first antenna pattern 46 . Therefore, by extending the first lead 82 from the connection pad 81 to the rear end surface 41cb, the first lead 82 is easily arranged on the route away from the second antenna pattern 101 . Furthermore, the first lead 82 may also extend from the connection pad 81 to the front end surface 41ca, the left end surface 41cc, or the right end surface 41cd.

A part of the first lead 82 overlaps the inner side 46a of the first antenna pattern 46 in plan view of the first surface 41a. The first lead 82 is thinner than the conductor forming the first antenna pattern 46 . Therefore, the influence of the first lead 82 on the magnetic flux of the first antenna pattern 46 can be suppressed.

In the SD card 11 according to the modified example of the second embodiment, all the first leads 82 are separated from the second antenna pattern 101 and extend from the connection pad 81 to the end surface 41 c of the first substrate 41 . Accordingly, it is not necessary to electrically separate the first lead 82 and the second antenna pattern 101 by etching back, and it is possible to suppress an increase in the manufacturing process and manufacturing cost of the SD card 11 .

(third embodiment)

Next, a third embodiment will be described with reference to FIG. 13 . FIG. 13 is a plan view showing the SD card 11 according to the third embodiment. As shown in FIG. 13 , the SD card 11 of the third embodiment has a micro SD card 131 and an adapter 132 . The micro SD card 131 mounted on the adapter 132 is used as the full size SD card 11 .

The micro SD card 131 is an example of a semiconductor device, and may also be called, for example, a device, a module, a unit, a medium, and a component. The semiconductor device may be another device such as a mini SD card or a USB flash memory.

The micro SD card 131 has a first substrate 41 , a plurality of I/F terminals 22 , a communication controller 24 , a flash memory 25 , and a memory controller 26 . The I/F terminal 22 of the third embodiment is a micro SD interface terminal.

The micro SD card 131 is electrically connected to the host device 12 as a single body, and data can be written into or read out by the host device 12 .

The micro SD card 131 has two first connection terminals 135 . The first connection terminal 135 is provided on the second surface 41 b of the first substrate 41 similarly to the I/F terminal 22 . The two first connection terminals 135 are, for example, adjacent to the plurality of I/F terminals 22 . The first connecting terminal 135 can also be disposed at other locations.

The two first connection terminals 135 are electrically connected to the communication controller 24, for example. The two first connection terminals 135 are exposed to the outside through openings, for example. In addition, the first connection terminal 135 may also be included in the I/F terminal 22 .

The adapter 132 is an adapter for using a micro SD card as a reader/writer for a full-size SD card. Adapters can also be: for example, an adapter to use a mini SD card as a reader/writer for a full-sized SD card; an adapter to use an SD card, mini SD card, or micro SD card as a USB connector ; An adapter for making the A terminal of USB serve as a connector of other USB standards like Type C; and other adapters such as this.

The adapter 132 has a case 141 , a plurality of full-size I/F terminals 142 , a loop antenna 143 and two second connection terminals 144 . The full-size I/F terminal 142 is an example of a second interface terminal. The loop antenna 143 is a first antenna and an example of the antenna.

The case portion 141 is made of, for example, a synthetic resin that is a non-magnetic body and an insulator. The box part 141 can also be made of other materials. The box portion 141 is formed in a substantially quadrangular box shape.

The full-size I/F terminal 142 is an SD interface terminal. A full-size I/F terminal 142 is provided at one end of the box portion 141 in the direction along the Y-axis. A plurality of full-size I/F terminals 142 are arranged in a direction along the X-axis. The full-size I/F terminal 142 is exposed outside the box portion 141 .

In the box portion 141, an insertion port 141a is provided. The insertion port 141a is opened at the other end of the case portion 141 in the direction along the Y-axis. The micro SD card 131 is detachably attached to the adapter 132 by inserting it into the insertion port 141a.

By inserting the micro SD card 131 into the insertion port 141a, the plurality of I/F terminals 22 of the micro SD card 131 are electrically connected to the corresponding full-size I/F terminals 142 . The I/F terminal 22 can be electrically connected to the host device 12 via the full-size I/F terminal 142 .

The loop antenna 143 is housed in the case portion 141 . The loop antenna 143 is formed, for example, in what may be called a coil shape, a helical shape, or a spiral shape. In the present embodiment, the loop antenna 143 is formed of a copper wire wound into a coil. A copper wire wound into a coil is an example of a wound conductor. In addition, the loop antenna 143 may be, for example, a pattern formed on a substrate.

The box part 141 includes an outer frame area 151 and an inner area 152 . The outer frame region 151 is a frame-shaped portion adjacent to the peripheral end portion 141 b of the box portion 141 . The inner area 152 is surrounded by the outer frame area 151 .

The loop antenna 143 is arranged in the outer frame area 151 of the box part 141 . In other words, the loop antenna 143 extends along the peripheral end portion 141 b of the case portion 141 . Also, the configuration of the loop antenna 143 is not limited thereto.

The two second connection terminals 144 are provided inside the insertion port 141a. The two second connection terminals 144 are two terminals of the loop antenna 143 . One second connection terminal 144 is electrically connected to one end of the loop antenna 143 . Another second connection terminal 144 is electrically connected to the other end of the loop antenna 143 .

By inserting the micro SD card 131 into the insertion port 141a, the two first connection terminals 135 of the micro SD card 131 are electrically connected to the corresponding second connection terminals 144, respectively. Accordingly, the communication controller 24 is electrically connected to the loop antenna 143 via the first and second connection terminals 135 and 144 .

The communication controller 24 of the third embodiment communicates with the wireless communication host device 13 via the loop antenna 143 instead of the first antenna pattern 46 of the first embodiment. That is, in the third embodiment, the wireless antenna 23 in FIG. 2 has the loop antenna 143 .

The first antenna pattern 46 of the adapter 132 transmits data received from the wireless communication host device 13 to the communication controller 24 of the micro SD card 131 . Furthermore, the first antenna pattern 46 of the adapter 132 transmits the data received from the communication controller 24 of the micro SD card 131 to the wireless communication host device 13 .

FIG. 13 shows the micro SD card 131 inserted into the insertion port 141a by a dashed-two dotted line. When the first surface 41 a of the first substrate 41 is viewed from above as shown in FIG. 13 , a part of the inner side 143 a of the loop antenna 143 is located outside the micro SD card 131 . The inner side 143 a of the loop antenna 143 is a region surrounded by the loop antenna 143 . In addition, a part of the loop antenna 143 is located outside the first substrate 41 in a planar view of the first surface 41 a.

In the SD card 11 of the third embodiment, the micro SD card 131 having the first substrate 41 is attached to the adapter 132 having the loop antenna 143 . Thus, even if the micro SD card 131 is small, the micro SD card 131 can communicate with the wireless communication host device 13 via the loop antenna 143 of the adapter 132 .

The loop antenna 143 is formed of a wound copper wire. This makes it possible to suppress an increase in the manufacturing cost of the SD card 11 compared to, for example, the case where the loop antenna 143 is formed using a pattern on a substrate.

(fourth embodiment)

Next, a fourth embodiment will be described with reference to FIGS. 14 to 16 . FIG. 14 is a plan view showing the first substrate 41 according to the fourth embodiment. As shown in FIG. 14 , in the fourth embodiment, the first antenna pattern 46 is mounted on the first substrate 41 . In the fourth embodiment, the wireless antenna 23 of FIG. 2 has a first antenna pattern 46 .

FIG. 15 is a plan view showing a part of the first substrate 41 according to the fourth embodiment. As shown in FIGS. 14 and 15 , on the first substrate 41 of the fourth embodiment, similar to the second embodiment, a plurality of connection pads 81 , a plurality of first leads 82 , a first solder resist 83 , and a first solder resist 83 are provided. The second lead 115 and the third lead 116 . In the first solder resist 83, a plurality of first openings 84 and second openings 119 are provided.

The second lead 115 extends from the first antenna pattern 46 instead of extending from the second antenna pattern 101 of the second embodiment. The third lead 116 also extends from the first antenna pattern 46 .

FIG. 16 is a plan view showing a part of the first substrate 41 in one step of the manufacturing process of the fourth embodiment. As shown in FIG. 16 , before forming the plurality of connection pads 81 on the first substrate 41 , the first plating lead L1 and the second plating lead L2 are provided on the first formation surface 91 a of the base substrate 91 .

The first plating lead L1 includes a plurality of first leads 82 and second leads 115 . The first plating lead L1 extends from the first antenna pattern 46 , has a plurality of branched portions, and is connected to a plurality of connection pads 81 . In other words, at the end portion of the first plating lead L1, the connection pad 81 is formed by electrolytic plating.

The second plating lead L2 includes a third lead 116 . The second plating lead L2 extends from the first antenna pattern 46 to the end face 41c of the first substrate 41 . The second plating lead L2 is electrically connected to the plurality of connection pads 81 via the first antenna pattern 46 and the first plating lead L1.

When the connection pad 81 is formed by electrolytic plating, the second plating lead L2 is connected to a power source. After the plurality of connection pads 81 are formed, a part of the first plating lead L1 and a part of the second plating lead L2 are removed, for example, by etch back. The first plating lead L1 is etched back through the first opening 84 to be divided into a plurality of first leads 82 and second leads 115 . The second plating lead L2 is etched back through the second opening 119 to form the third lead 116 . Thereby, the plurality of connection pads 81 are electrically separated from the first antenna pattern 46 .

In the SD card 11 of the fourth embodiment, the first leads 82 extend from the connection pads 81 to which electronic components such as the flash memory 25 are connected. The first lead 82 is electrically separated from other conductors. On the other hand, the second lead 115 extends from the first antenna pattern 46 . The second lead 115 is electrically separated from other electrical conductors. The first and second leads 82 and 115 are connected, for example, during the manufacturing process of the SD card 11 to form the first plating lead L1. In this case, by applying a voltage to the first and second leads 82 and 115 via the first antenna pattern 46 , the connection pad 81 can be formed at the end of the first lead 82 by electrolytic plating. After the connection pad 81 is formed, the first lead 82 and the second lead 115 are divided. Thus, on the first substrate 41 on which the first antenna pattern 46 is formed, the connection pad 81 can be formed by electrolytic plating of the first and second leads 82 and 115 . Therefore, the first antenna pattern 46 not as a chip antenna but as a loop antenna can be provided on the first substrate 41 , and an increase in the manufacturing cost of the SD card 11 can be suppressed.

Next, a modified example of the fourth embodiment will be described with reference to FIGS. 17 to 19 . FIG. 17 is a plan view showing a first substrate 41 according to a modified example of the fourth embodiment. As shown in FIG. 17 , in a modified example of the fourth embodiment, on the first substrate 41, a plurality of connection pads 81, a plurality of first leads 82, a first solder resist 83, a plurality of second leads 115, A plurality of third leads 116 and a plurality of fourth leads 161 . In the first solder resist 83 , a plurality of first openings 84 , a plurality of second openings 119 and a plurality of third openings 162 are provided.

17 represents a plurality of first leads 82, a plurality of second leads 115, a plurality of third leads 116, and a plurality of fourth leads 161 with solid lines for illustration, and represents a plurality of first openings 84, A plurality of second openings 119 and a plurality of third openings 162 .

FIG. 18 is a plan view showing a part of the first substrate 41 according to a modified example of the fourth embodiment. In the modified example of the fourth embodiment, the first antenna pattern 46 is wound a plurality of times. Therefore, as shown in FIG. 18 , in a region adjacent to the end surface 41c of the first substrate 41 , the extending portion 46d of the first antenna pattern 46 and the other extending portion 46d extend substantially in parallel with a gap therebetween. The extension portion 46d of the first antenna pattern 46 is a part of the first antenna pattern 46 extending along the adjacent end face 41c.

The fourth lead 161 is disposed on the first forming surface 91a. Therefore, the first solder resist 83 covers the fourth lead 161 . A plurality of fourth lead wires 161 extend from the extension portion 46d of the first antenna pattern 46 to other adjacent extension portions 46d. For example, a fourth lead 161 extends from one extension 46d to another extension 46d adjacent to the extension 46d and farther away from the flash memory 25 than the extension 46d. That is, the fourth lead 161 is located between two adjacent extension parts 46d, 46d of the first antenna pattern 46 .

The plurality of fourth leads 161 respectively have fourth end portions 161a. The fourth end portion 161 a is an end portion of the fourth lead 161 extending from the first antenna pattern 46 . In other words, the fourth end portion 161a is located on the opposite side of the first antenna pattern 46 .

The fourth end portion 161a is away from other conductors including the other extension portion 46d of the first antenna pattern 46 . Therefore, the fourth lead 161 is electrically separated from another conductor different from the extension portion 46d of the first antenna pattern 46 . In other words, the fourth lead wire 161 does not connect the extension portion 46d of the first antenna pattern 46 with the other extension portion 46d in the course of winding the first antenna pattern 46 multiple times.

The third opening 162 is a hole provided in the first solder resist 83 . The third opening 162 is located between adjacent two extensions 46d, 46d of the first antenna pattern 46 in a region adjacent to the end surface 41c of the first substrate 41 . The third opening 162 is away from the two adjacent extension parts 46d, 46d of the first antenna pattern 46 .

The fourth end 161 a of the fourth lead 161 substantially overlaps the edge of the first solder resist 83 forming the third opening 162 in a plan view of the first surface 41 a of the first substrate 41 . Furthermore, the fourth end portion 161a may also be disposed at other positions.

The fourth end portions 161a of the plurality of fourth leads 161 extending from one extension portion 46d of the first antenna pattern 46 substantially overlap the edge of the first solder resist 83 forming one third opening 162 . Furthermore, the fourth end portions 161a of the plurality of fourth leads 161 extending from the other extension portion 46d of the first antenna pattern 46 substantially overlap the edge of the first solder resist 83 forming the third opening 162 .

The fourth end 161a of the fourth lead 161 extended from one extension 46d of the first antenna pattern 46 is opposite to the fourth end 161a of the fourth lead 161 extended from the other extension 46d of the first antenna pattern 46 . The fourth lead 161 extending from one extension 46d of the first antenna pattern 46 is located on the extension line of the fourth lead 161 extending from the other extension 46d of the first antenna pattern 46 .

The corresponding first leads 82 , the second leads 115 , the third leads 116 and the plurality of fourth leads 161 are located on the extension lines of each other. Furthermore, the arrangement of the first lead 82 , the second lead 115 , the third lead 116 and the fourth lead 161 is not limited thereto.

FIG. 19 is a plan view showing a part of the first substrate 41 in one of the manufacturing steps of the modified example of the fourth embodiment. As shown in FIG. 19 , before the step of forming the plurality of connection pads 81 on the first substrate 41 , a plurality of plating leads L are provided on the first formation surface 91 a of the base substrate 91 . The plating lead L is provided, for example, to form the plurality of connection pads 81 and other plurality of pads by electrolytic plating.

The plurality of plating leads L respectively include a first lead 82 , a second lead 115 , a third lead 116 and a plurality of fourth leads 161 . The plating lead L extends from the connection pad 81 to the end surface 41 c of the first substrate 41 . In other words, at the end of the plating lead L, the connection pad 81 is formed by electrolytic plating.

Each of the plurality of plating leads L linearly extends from one connection pad 81 to the end surface 41 c of the first substrate 41 . It should be noted that the plurality of plating leads L may be bent or joined (branched).

The plurality of plating leads L intersects the plurality of extensions 46d of the first antenna pattern 46 . In other words, the plurality of plating leads L electrically connects the extension 46d of the first antenna pattern 46 and the other extension 46d. Also, for example, in the case of wiring the flash memory 25 and/or the memory controller 26 using a wire bonding technique, a part of the first antenna pattern 46 may be formed using a bonding wire and separated from the plating wire L.

Before the plurality of first substrates 41 are cut out from one collective substrate, the plurality of plating leads L are connected to the leads of the collective substrate including the plurality of first substrates 41 . That is, the plurality of plating leads L connects the leads of the collective substrate and the inner side 46a of the first antenna pattern 46, respectively. When the connection pad 81 is formed by electrolytic plating, the plating lead L is connected to a power source.

When forming the plurality of connection pads 81 , a part of the plated lead L is removed, for example, by etch back. The plating lead L is etched back through the first opening 84, the second opening 119, and the plurality of third openings 162, thereby being divided into the first lead 82, the second lead 115, the third lead 116, and the plurality of fourth leads. 161.

The plurality of connection pads 81 are electrically separated from the first antenna pattern 46 by etching back the plated lead L. As shown in FIG. Furthermore, the extension 46d of the first antenna pattern 46 is electrically separated from the other extension 46d.

In the SD card 11 according to the modified example of the fourth embodiment, the first lead 82 extends from the connection pad 81 , and the second lead 115 extends from the first antenna pattern 46 . Furthermore, the third lead 116 extends from the first antenna pattern 46 to the end face 41c of the first substrate 41, and the fourth lead 161 extends from the extension 46d of the first antenna pattern 46 to the other extension 46d. The first to fourth lead wires 82, 115, 116, and 161 are electrically separated from other electrical conductors, respectively. The first to fourth leads 82 , 115 , 116 , and 161 are connected, for example, during the manufacturing process of the SD card 11 to form plating leads L. In this case, by applying a voltage to the plating lead L intersecting the first antenna pattern 46 , the connection pad 81 can be formed at the end of the first lead 82 by electrolytic plating. After the connection pad 81 is formed, the first to fourth leads 82, 115, 116, 161 are divided. Thus, on the first substrate 41 on which the first antenna pattern 46 is formed, the connection pad 81 can be formed by electrolytic plating of the first to fourth leads 82 , 115 , 116 , and 161 .

In the formation process of the connection pad 81 mentioned above, voltage is applied to each of the several plating lead L extended linearly. Therefore, the distance from the power source to the end portion of the first lead 82 of each plating lead L becomes uniform easily. Moreover, the distance from the end surface 41c of the 1st board|substrate 41 to the end part of the 1st lead 82 of each plating lead L becomes uniform easily. Therefore, the power supply is stable, and the plurality of connection pads 81 can be easily formed uniformly by electrolytic plating.

(fifth embodiment)

A fifth embodiment will be described below with reference to FIG. 20 . FIG. 20 is a bottom view showing the SD card 11 according to the fifth embodiment with the bottom cover 32 omitted. In FIG. 20 , the first substrate 41 is indicated by a two-dot chain line.

As shown in FIG. 20 , in the fifth embodiment, the first antenna pattern 46 is mounted on the top cover 33 . In the fifth embodiment, the wireless antenna 23 of FIG. 2 has a first antenna pattern 46 .

In the fifth embodiment, the first antenna pattern 46 is buried inside the top cover 33 . In other words, the first antenna pattern 46 is located between the top surface 61 and the second inner surface 62 of the top cover 33 . Furthermore, the first antenna pattern 46 can be disposed on the second inner surface 62 of the top cover 33 , or can be disposed on the bottom cover 32 , for example. The first antenna pattern 46 may be a conductive pattern formed by various methods such as printing, or may be a conductor such as a copper wire.

At both ends of the first antenna pattern 46, first terminals 171 are provided. The first terminal 171 protrudes, for example, from the third recess 65 of the second inner surface 62 of the top cover 33 . The first terminal 171 overlaps the first substrate 41 in a planar view of the second surface 41 b of the first substrate 41 as shown in FIG. 20 .

On the first surface 41 a of the first substrate 41 , two second terminals 172 are provided. The second terminal 172 is opposite to the first terminal 171 . For example, the second terminal 172 is electrically connected to the first terminal 171 via a conductive spring. The second terminal 172 may be in direct contact with the first terminal 171 or may be connected by solder. Thus, the circuit C of the first substrate 41 and the first antenna pattern 46 are electrically connected.

In the SD card 11 of the fifth embodiment, the first antenna pattern 46 is disposed on the top cover 33 of the casing 31 . Accordingly, it is possible to suppress a decrease in the degree of freedom of wiring on the first substrate 41 . Furthermore, by providing the first antenna pattern 46 on the case 31 of the SD card 11, an increase in the number of parts of the SD card 11 can be suppressed, and an increase in the manufacturing cost of the SD card 11 can be suppressed.

The first terminal 171 of the first antenna pattern 46 and the second terminal 172 of the first substrate 41 are electrically connected by, for example, a spring. Accordingly, even if the first antenna pattern 46 and the first substrate 41 move relative to each other, damage to the connecting portion between the first antenna pattern 46 and the first substrate 41 can be suppressed.

(sixth embodiment)

Next, a sixth embodiment will be described with reference to FIG. 21 . FIG. 21 is a plan view showing the SD card 11 according to the sixth embodiment. As shown in FIG. 21 , a label 181 is attached to the top surface 61 of the top cover 33 .

The label 181 is a sheet attached to the casing 31 . On the label 181, for example, the specification, storage capacity, insertion direction, and description of the SD card 11 are described. In addition, the tag 181 is not limited to this. The label 181 is attached, for example, to the concave portion 183 provided on the top surface 61 . Also, a part of the label 181 may be located outside the recess 183 .

In the sixth embodiment, the first antenna pattern 46 is mounted on the tag 181 . In the sixth embodiment, the wireless antenna 23 of FIG. 2 has a first antenna pattern 46 .

In the sixth embodiment, the first antenna pattern 46 is buried inside the tag 181 . Furthermore, the first antenna pattern 46 can be provided on the adhesive surface of the label 181 attached to the top cover 33 , for example. The adhesive surface is the surface of the label 181 on which the adhesive is applied. The first antenna pattern 46 may be a conductive pattern formed by various methods such as printing, or may be a conductor such as a copper wire.

At both ends of the first antenna pattern 46, third terminals 185 are provided. The third terminal 185 is provided, for example, on the above-mentioned adhesive surface of the label 181 . The third terminal 185 overlaps the first substrate 41 in a planar view of the top surface 61 of the top cover 33 as shown in FIG. 21 .

On the top cover 33, two penetrating electrodes 187 are provided. The penetrating electrode 187 is formed of a conductor and penetrates the top cover 33 . The penetrating electrode 187 protrudes from the top surface 61 and protrudes from the second inner surface 62 . The third terminal 185 of the first antenna pattern 46 is opposed to the through electrode 187 . The third terminal 185 is in contact with the penetration electrode 187 and is electrically connected to the penetration electrode 187 .

The third terminal 185 is brought into contact with the penetrating electrode 187 when the label 181 is attached to the concave portion 183 of the top cover 33 . That is, the concave portion 183 is used for alignment between the third terminal 185 and the through-electrode 187 .

On the first surface 41a of the first substrate 41, two fourth terminals 189 are provided. The fourth terminal 189 is opposed to the through electrode 187 . For example, the fourth terminal 189 is electrically connected to the through electrode 187 via a conductive spring. The fourth terminal 189 may be in direct contact with the penetrating electrode 187 or may be connected by solder.

The through electrode 187 is interposed between the third terminal 185 of the first antenna pattern 46 and the fourth terminal 189 of the first substrate 41 . Accordingly, the third terminal 185 is electrically connected to the fourth terminal 189 via the penetrating electrode 187 , thereby electrically connecting the circuit C of the first substrate 41 and the first antenna pattern 46 .

In the SD card 11 of the sixth embodiment, the first antenna pattern 46 is provided on the label 181 . Accordingly, it is possible to suppress a decrease in the degree of freedom of wiring on the first substrate 41 . Furthermore, by providing the first antenna pattern 46 on the label 181 of the SD card 11, an increase in the number of parts of the SD card 11 can be suppressed, and an increase in the manufacturing cost of the SD card 11 can be suppressed.

The adhesive surface of the label 181 is adhered to the top surface 61 of the top cover 33 protruding through the electrode 187 . Accordingly, relative movement of the tag 181 on which the first antenna pattern 46 is mounted and the penetration electrode 187 can be suppressed, and damage to the connecting portion between the first antenna pattern 46 and the first substrate 41 can be suppressed.

Not limited to the top surface 61 of the top cover 33 , the label 181 can also be attached to other parts of the casing 31 . For example, the label 181 can also be attached to the second inner surface 62 of the top cover 33 . In this case, the third terminal 185 and the fourth terminal 189 can be electrically connected without the through electrode 187 .

In addition, not limited to the label 181, the first antenna pattern 46 may be mounted on a sheet that does not have an adhesive surface. In this case, for example, the above-described sheet is sandwiched between the label 181 not having the first antenna pattern 46 and the top cover 33 . Thereby, the sheet|seat which does not have an adhesive surface can be attached to the case 31. FIG.

According to at least one embodiment described above, when viewing the first surface of the first substrate in a plan view, at least a part of the first antenna is located outside the first substrate, and at least a part of the remaining part is located on the first substrate. Accordingly, an increase in the manufacturing cost of the semiconductor memory device can be suppressed.

Although some embodiments of the present invention have been described, these embodiments are only illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and/or modifications thereof are included in the scope and/or gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Claims (19)

1. A semiconductor storage device, wherein, have: a first substrate having a first face and a second face opposite the first face; a non-volatile memory mounted on the first surface; a memory controller mounted on the first substrate and configured to: control the nonvolatile memory; a first interface terminal mounted on the first substrate and capable of being electrically connected to a first external device; a first antenna connected to the first substrate, at least a part of which is located outside the first substrate and at least a remaining part of which is located on the first substrate in a plan view of the first surface; and A communication controller configured to communicate with a second external device via the first antenna. 2. The semiconductor memory device according to claim 1, wherein, the first antenna generates a voltage based on electric waves from the second external device, The communication controller is operable with the generated voltage. 3. The semiconductor memory device according to claim 1 or 2, wherein, A second substrate is further provided, and the first antenna is mounted on the second substrate. 4. The semiconductor memory device according to claim 3, wherein, Also have: a circuit mounted on the first substrate and including the nonvolatile memory, the memory controller, the first interface terminal, and a plurality of first pads; and a second pad mounted on the first substrate and electrically independent from the circuit, the first antenna has a plurality of third pads soldered to the plurality of first pads, The second substrate has a fourth pad electrically independent from the circuit and soldered to the second pad. 5. The semiconductor memory device according to claim 4, wherein, The second substrate has a first portion on which the first antenna is mounted, a second portion surrounded by the first portion, and a third portion surrounding the first portion, At least one of the plurality of third pads and the fourth pad is disposed on the second portion, and at least another of the plurality of third pads and the fourth pad is disposed on the second portion. Describe the third part. 6. The semiconductor memory device according to claim 3, wherein, The second substrate is thinner than the first substrate. 7. The semiconductor memory device according to claim 1 or 2, wherein, At least a part of the inner side of the first antenna is located outside the first substrate in a plan view of the first surface. 8. The semiconductor memory device according to claim 1 or 2, wherein: A second antenna is further provided. The second antenna is mounted on the first substrate and connected to the first antenna to form a single antenna together with the first antenna. 9. The semiconductor memory device according to claim 8, wherein, The first interface terminal is mounted on the second surface, The second antenna has a first wiring mounted on the first surface and a second wiring mounted on the second surface and connected to the first wiring, At least a part of the first wiring overlaps the first interface terminal when viewed from above on the first surface. 10. The semiconductor memory device according to claim 8, wherein, further comprising a ground line provided on the first substrate, said first substrate has at least one first region and at least one second region, The at least one first area is surrounded by the one antenna formed by the first antenna and the second antenna, and is connected to the non-volatile memory and the first surface when viewing the first surface from above. At least one side of the memory controller overlaps and is provided with the ground line, The at least one second area is surrounded by the one antenna formed by the first antenna and the second antenna, and is separated from the first area in a plan view of the first surface. 11. The semiconductor memory device according to claim 8, wherein, Also have: a connection pad mounted on the first substrate and electrically connected to any one of the nonvolatile memory, the memory controller, and the communication controller; a first conductive pattern mounted on the first substrate, connected to the connection pad, and electrically connects the connection pad to another conductor different from the connection pad; a second conductive pattern mounted on the first substrate, connected to the second antenna, and electrically connecting the second antenna to another conductor different from the second antenna; a first lead mounted on the first substrate, extending from the connection pad, and electrically separated from another conductor different from the connection pad; and A second lead extends from the second antenna and is electrically separated from another electrical conductor different from the second antenna. 12. The semiconductor memory device according to claim 11, wherein, the first lead has a first end on an opposite side of the connection pad, the second lead has a second end on the opposite side of the second antenna, The first substrate has: a formation surface provided with the first lead and the second lead; and a solder resist covering the formation surface, the first lead, and the second lead, An opening is provided in the solder resist, and the opening overlaps a region where the first end portion of the first lead and the second lead are viewed in plan view on the first surface. the region between the second ends. 13. The semiconductor memory device according to claim 12, wherein, The first substrate further has a cover member that covers the nonvolatile memory, the memory controller, the solder resist, and the opening. 14. The semiconductor memory device according to claim 11, wherein, further comprising a third lead mounted on the first substrate, The first substrate has an end surface connecting an end edge of the first surface and an end edge of the second surface, The third lead extends from the second antenna between the second antenna and the end face of the first substrate, and is electrically separated from other electrical conductors. 15. The semiconductor memory device according to claim 11, wherein, further comprising a plurality of connection pads and a plurality of first leads, The number of the plurality of first leads is greater than the number of the second leads. 16. The semiconductor memory device according to claim 1 or 2, wherein, further comprising a case housing the first substrate and the first antenna and having a first cover and a second cover, The first cover is provided with a first recess for accommodating the first substrate and a second recess for accommodating the first antenna, The second cover is installed on the first cover and covers the first substrate and the first antenna. 17. The semiconductor memory device according to claim 1, wherein, Also have: an adapter having said first antenna and a second interface terminal; and a semiconductor device having the first substrate and detachably attached to the adapter, The first interface terminal can be electrically connected to the first external device via the second interface terminal. 18. The semiconductor memory device according to claim 17, wherein, The first antenna is formed from a wound conductor. 19. An adapter wherein, have: a box part, which is provided with an insertion port; an antenna housed in the box; and The plurality of second connection terminals are provided inside the insertion port and connected to the antenna, and are configured to be electrically connected to the plurality of first connection terminals provided in the semiconductor device by inserting the semiconductor device into the insertion port. connected, the semiconductor device is configured to communicate with an external device via the antenna.