CN106802598A - A power supply method based on multi-core access point architecture and multi-core access point - Google Patents

Abstract

The embodiment of the invention discloses a power supply method based on a multi-core access point architecture and a multi-core access point, wherein the multi-core access point comprises at least two cores, at least two direct current voltage sources and at least two load monitors, and the power supply method comprises the following steps: a first load monitor monitors a first load condition of the first core; the first load monitor generates a first voltage control signal corresponding to the first load state according to the corresponding relation between the load state and the voltage control signal, and outputs the first voltage control signal to the first direct current stabilized voltage supply; the first voltage control signal is used for the first direct current stabilized voltage supply to output a target output voltage corresponding to the first voltage control signal to the first core according to the corresponding relation between the voltage control signal and the output voltage. The embodiment of the invention is beneficial to reducing the overall power consumption of the multi-core access point.

Description

A power supply method based on multi-core access point architecture and multi-core access point

technical field

The present invention relates to the field of communication technology, in particular to a power supply method based on a multi-core access point architecture and a multi-core access point.

Background technique

At present, when an access point (Access point, AP) has more and more functions, the AP may be equipped with multiple central processing units (English: Central Processing Unit, CPU for short), so as to realize the diversified functions of the AP. For an AP equipped with multiple CPUs, each CPU of the AP uses the same power supply voltage. In actual work, the greater the CPU load, the higher the required operating voltage. When the load of each CPU is different, In order to meet the operating voltage requirements of the CPU with the largest load, the operating voltage of each CPU is the operating voltage of the CPU with the largest load, resulting in the low-load CPU still working at a high operating voltage, wasting the power consumption of the low-load CPU , thereby increasing the overall power consumption of the AP.

Contents of the invention

Embodiments of the present invention provide a power supply method based on a multi-core access point architecture and a multi-core access point, which can reduce the overall power consumption of the multi-core access point.

The first aspect of the embodiments of the present invention provides a power supply method based on a multi-core access point architecture, the multi-core access point includes at least two cores, at least two DC voltage sources and at least two load monitors, the Power supply methods include:

The first load monitor monitors the first load status of the first core, the first load monitor is any one of the at least two load monitors, and the first core is one of the at least two cores any one;

The first load monitor generates a first voltage control signal corresponding to the first load state according to the corresponding relationship between the load state and the voltage control signal, and outputs the first voltage control signal to the first DC regulator Power supply; the first DC regulated power supply is any one of the at least two DC voltage sources, and the first DC regulated voltage is correspondingly connected to the first load monitor and the first core, The first core is correspondingly connected to the first load monitor;

Wherein, the first voltage control signal is used for the first DC stabilized power supply to output the target output voltage corresponding to the first voltage control signal to the first core according to the corresponding relationship between the voltage control signal and the output voltage .

The second aspect of the embodiment of the present invention provides a multi-core access point, including a voltage source and N cores, and the multi-core access point also includes N DC regulated power supplies and N load monitors, wherein:

Each core is connected to a DC regulated power supply and a load monitor. The DC regulated power supply connected to each core is different, and the load monitors connected to each core are different;

Each DC regulated power supply corresponds to a load monitor and a core, and each DC regulated power supply is connected to a different load monitor;

The voltage source is connected to the N DC regulated power supplies, and the first load monitor monitors the first load state of the correspondingly connected first core, and generates a first voltage control signal according to the first load state and sends it to the correspondingly connected The first DC stabilized power supply, the first DC stabilized power supply outputs the target output voltage corresponding to the first voltage control signal to the first core according to the corresponding relationship between the voltage control signal and the output voltage; the first DC stabilized power supply A load monitor is any one of the N load monitors, the first core is any one of the N cores, and the first DC stabilized power supply is the N DC stabilized power supply Any one of the power sources, the N is a positive integer greater than or equal to 2.

Embodiments of the present invention have the following beneficial effects:

The load monitor used in the embodiment of the present invention can regulate the working voltage of each core according to the load state of each core, and can meet the different voltage requirements of multiple cores in a multi-core access point, thereby reducing the number of multi-core access points. The overall power consumption of the point.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of the architecture of a multi-core access point disclosed in an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of a load monitor disclosed by an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of another load monitor disclosed by an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of a multi-core access point disclosed by an embodiment of the present invention;

Fig. 5 is a schematic flowchart of a power supply method based on a multi-core access point architecture disclosed by an embodiment of the present invention.

detailed description

In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or devices.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

The following describes the embodiments of the present invention in detail.

In order to better understand the embodiment of the present invention, a multi-core access point disclosed in the embodiment of the present invention is firstly described below.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of an architecture of a multi-core access point disclosed by an embodiment of the present invention. As shown in FIG. 1, the multi-core access point includes a voltage source 101, N cores (1031, 1032, 1033, ... 103N in FIG. 1021, 1022, ... 102N) and N load monitors (such as 1041, 1042, 1043, ... 104N in Figure 1).

The core here is an independent functional module, such as a central processing unit (English: Central Processing Unit, CPU for short), a modem, a radio frequency module, and the like. For example, a multi-core access point may be an access point with multiple CPUs.

The voltage source 101 provides power supply voltages for the DC stabilized power supplies 1021, 1022, ... 102N, and a load monitor (English: Load Monitor; LM for short) monitors the load status of a core, for example, the load monitor 1041 monitors the core 1031 The load status of the core 1032 is monitored by the load monitor 1042, and the load status of the core 103N is monitored by the load monitor 104N. The load state may include parameters such as core load rate, current, power, and frequency, and may also include parameters such as core wait for interrupt (English: Wait for interrupt; WFI for short) duration, cache hit rate, and idle time ratio. Generally speaking, the shorter the core's waiting time for interrupts, the higher the cache hit rate, and the smaller the proportion of idle time, the heavier the core's load. The load monitor generates a voltage control signal according to the load status of the core and sends it to the DC stabilized power supply. For example, the load monitor 1041 generates a voltage control signal according to the load status of the core 1031 and sends it to the DC stabilized power supply 1021. The load monitor 1042 generates a voltage control signal according to the core 1032 The load status generates a voltage control signal and sends it to the DC regulated power supply 1021, and the load monitor 1043 generates a voltage control signal according to the load status of the core 1033 and sends it to the DC regulated power supply 1022, ... The load monitor 104N generates a voltage control signal according to the load status of the core 103N The generated voltage control signal is sent to the DC stabilized voltage power supply 102N. The DC stabilized power supply outputs the voltage to the core according to the voltage control signal sent by the load monitor. Specifically, the DC stabilized power supply 1021 outputs the voltage corresponding to the voltage control signal generated by the load monitor 1041 according to the corresponding relationship between the voltage control signal and the output voltage. The target output voltage is sent to the core 1031; the DC stabilized power supply 1022 outputs the target output voltage corresponding to the voltage control signal generated by the load monitor 1042 to the core 1032 according to the corresponding relationship between the voltage control signal and the output voltage; the DC stabilized power supply 1023 according to the voltage According to the corresponding relationship between the control signal and the output voltage, the target output voltage corresponding to the voltage control signal generated by the load monitor 1043 is output to the core 1033. ... The DC stabilized voltage power supply 102N outputs the corresponding relationship between the voltage control signal and the output voltage. The load monitor 104N generates a target output voltage corresponding to the voltage control signal to the core 103N.

Wherein, the DC regulated power supply may include a low dropout linear regulator (English: Low Dropout Regulator; LDO for short) or a DC chopper (DC-DC).

The load monitor used in the embodiment of the present invention can regulate the working voltage of each core according to the load state of each core, and can meet the different voltage requirements of multiple cores in a multi-core access point, thereby reducing the number of multi-core access points. The overall power consumption of the point.

Please refer to FIG. 2. FIG. 2 is a schematic structural diagram of a load monitor disclosed by an embodiment of the present invention. The load monitor shown in FIG. 2 is applied to the multi-core access point in FIG. 1. As shown in FIG. 2, the first load The monitor 1041 is used to connect the first core 1031 and the first DC power supply 1021, the first core 1031 is a core in the multi-core access point; the load monitor 1041 is used to monitor the first load of the first core 1031 state, and control the first DC regulated power supply 1021 to output voltage to the first core 1031 according to the first load state.

Wherein, the first load monitor 1041 is used to monitor the first load status of the first core 1031, and generate a voltage control signal to the first DC regulated power supply 1021 according to the first load status, and the first DC regulated power supply 1021 according to The voltage control signal outputs a voltage to the first core 1031 .

In the embodiment of the present invention, the first load monitor 1041 can count the first load state of the first core 1031 in real time, and can periodically or non-periodically count the first load state of the first core 1031, the first load state It may include parameters such as the load rate, current, power, and operating frequency of the first core 1031, and may also include parameters such as the waiting interrupt duration, cache hit rate, and idle time ratio of the first core 1031.

The first load monitor 1041 can generate a voltage control signal to the first DC regulated power supply 1021 according to the first load state. For example, the first load state only includes the first load rate, and the first load monitor 1041 may generate a voltage control signal corresponding to the first load rate according to the correspondence between the load rate and the voltage control signal. For example, as shown in Table 1.

Table 1

Please refer to Table 1, Table 1 is the corresponding relationship between the load ratio and the voltage control signal disclosed in the embodiment of the present invention. Wherein, when the first load monitor 1041 detects that the first load rate of the first core 1031 is 90-100%, the corresponding voltage control signal is voltage control signal 1, and the first DC stabilized power supply 1021 receives the voltage control signal After signal 1, output a voltage of 5V to the first core 1031; when the first load monitor 1041 detects that the first load rate of the first core 1031 is 80-90%, the corresponding voltage control signal is voltage control signal 2, After receiving the voltage control signal 2, the first DC stabilized power supply 1021 outputs a voltage of 4.5V to the first core 1031; when the first load monitor 1041 detects that the first load rate of the first core 1031 is 70-80% , the corresponding voltage control signal is voltage control signal 3, and the first DC stabilized power supply 1021 outputs a voltage of 4V to the first core 1031 after receiving the voltage control signal 3; when the first load monitor 1041 detects that the first When the first load rate of the core 1031 is 60-70%, the corresponding voltage control signal is a voltage control signal 4, and the first DC stabilized power supply 1021 outputs a voltage of 3.5V to the first core after receiving the voltage control signal 4 1031; when the first load monitor 1041 detects that the first load rate of the first core 1031 is 50-60%, the corresponding voltage control signal is a voltage control signal 5, and the first DC stabilized voltage power supply 1021 receives the voltage control signal After the signal 5, output a voltage of 3V to the first core 1031; when the first load monitor 1041 detects that the first load rate of the first core 1031 is 30-50%, the corresponding voltage control signal is a voltage control signal 6, After receiving the voltage control signal 6, the first DC stabilized power supply 1021 outputs a voltage of 2.5V to the first core 1031; when the first load monitor 1041 detects that the first load rate of the first core 1031 is 10-30% , the corresponding voltage control signal is voltage control signal 7, and the first DC stabilized power supply 1021 outputs a voltage of 2V to the first core 1031 after receiving the voltage control signal 7; when the first load monitor 1041 detects the first When the first load rate of the core 1031 is less than 10%, the corresponding voltage control signal is the voltage control signal 8 , and the first DC regulated power supply 1021 outputs 1V to the first core 1031 after receiving the voltage control signal 8 .

The first load monitor 1041 can generate a voltage control signal to the first DC regulated power supply 1021 according to the first load state. The first load monitor 1041 can generate a voltage control signal corresponding to the first load state according to the corresponding relationship between the first load state and the voltage control signal. For example, as shown in Table 2.

Table 2

first load state voltage control signal Voltage (Volts) 9000-10000 Voltage control signal 1 5 8000-9000 Voltage control signal 2 4.5 7000-8000 Voltage control signal 3 4 6000-7000 Voltage control signal 4 3.5 5000-6000 Voltage control signal 5 3 3000-5000 Voltage control signal 6 2.5 1000-3000 Voltage control signal 7 2 less than 1000 Voltage control signal 8 1

Please refer to Table 2, Table 2 is the correspondence between the first load state and the voltage control signal disclosed in the embodiment of the present invention. Wherein, when the first load monitor 1041 calculates that the first load state is 9000-10000, the corresponding voltage control signal is voltage control signal 1, and the first DC stabilized power supply 1021 outputs 5V after receiving the voltage control signal 1 to the first core 1031; when the first load monitor 1041 calculates that the first load state is 8000-9000, the corresponding voltage control signal is voltage control signal 2, and the first DC stabilized power supply 1021 receives the voltage control signal After signal 2, output a voltage of 4.5V to the first core 1031; when the first load monitor 1041 calculates that the first load state is 7000-8000, the corresponding voltage control signal is voltage control signal 3, and the first DC stabilizer After receiving the voltage control signal 3, the piezoelectric power source 1021 outputs a voltage of 4V to the first core 1031; when the first load monitor 1041 calculates that the first load state is 6000-7000, the corresponding voltage control signal is the voltage control signal 4 After receiving the voltage control signal 4, the first DC stabilized power supply 1021 outputs a voltage of 3.5V to the first core 1031; when the first load monitor 1041 calculates that the first load state is 5000-6000, the corresponding voltage The control signal is a voltage control signal 5. After receiving the voltage control signal 5, the first DC stabilized power supply 1021 outputs a voltage of 3V to the first core 1031; when the first load monitor 1041 calculates that the first load state is 3000- When 5000, the corresponding voltage control signal is voltage control signal 6, and the first DC stabilized power supply 1021 outputs a voltage of 2.5V to the first core 1031 after receiving the voltage control signal 6; when the first load monitor 1041 calculates When the first load state is 1000-3000, the corresponding voltage control signal is voltage control signal 7, and the first DC stabilized power supply 1021 outputs a voltage of 2V to the first core 1031 after receiving the voltage control signal 7; when the first When the load monitor 1041 calculates that the first load state is less than 1000, the corresponding voltage control signal is a voltage control signal 8, and the first DC stabilized power supply 1021 outputs a voltage of 1V to the first core after receiving the voltage control signal 8 1031.

For example, if the first load state includes the first load rate, the first operating frequency, and the first idle time ratio, the first load state can be calculated according to the first load rate, the first operating frequency, and the first idle time ratio according to statistics. A certain calculation method is obtained. For example, you can set the weight of the first load rate, the first operating frequency and the first proportion of idle time, and calculate the first load status. For example, the first load rate is 60%, the first operating frequency is 800Mhz, the first idle time ratio is 50%, the weight value corresponding to the first load rate is 5000, and the weight value corresponding to the first operating frequency is 3. The weight value corresponding to the first idle time ratio is 2000, then the first load state L=60%*5000+800*3+50%*2000=6400. Then the voltage control signal corresponding to the first load state is the voltage control signal 4 , and the first DC stabilized power supply 1021 outputs a voltage of 3.5V to the first core 1031 after receiving the voltage control signal 4 .

The load monitor used in the embodiment of the present invention can regulate the working voltage of each core according to the load state of each core, and can meet the different voltage requirements of multiple cores in a multi-core access point, thereby reducing the number of multi-core access points. The overall power consumption of the point.

Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of another load monitor disclosed by an embodiment of the present invention. As shown in FIG. 3 , the first load monitor 20 is used to monitor the first load state of the first core 40, and generate a first voltage control signal to the first DC stabilized power supply 30 according to the first load state. The current regulated power supply 30 outputs a voltage to the core 40 according to the first voltage control signal, wherein the first load monitor 20 includes a control module 201 and at least one monitoring module (the first monitoring module 211 shown in FIG. 3 , the second monitoring module Module 212, ... Kth monitoring module 21K).

The monitoring terminal of a monitoring module is connected to an output terminal of the first core 40, for example, the monitoring terminal 2111 of the first monitoring module 211 is connected to the output terminal 401 of the first core 40, and the monitoring terminal 2121 of the second monitoring module 212 is connected to the first core The output terminal 402 of 40 , . . . the monitoring terminal 21K1 of the Kth monitoring module 21K is connected to the output terminal 40K of the first core 40 . The output end of a monitoring module is connected to an input end of the control module 201, for example, the output end 2112 of the first monitoring module 211 is connected to the input end 2011 of the control module 201, and the output end 2122 of the second monitoring module 212 is connected to the input of the control module 201 Terminal 2012 , . . . the output terminal 21K2 of the Kth monitoring module 21K is connected to the input terminal 201K of the control module 201 . The control terminal 2021 of the control module 201 is connected to the input terminal of at least one monitoring module (for example, the monitoring terminal 2113 of the first monitoring module 211, the monitoring terminal 2123 of the second monitoring module 212, ... the monitoring terminal 21K3 of the K monitoring module 21K ), the output terminal of the control module 201 is connected to the control terminal of the first DC regulated power supply 30, for example, the output terminal 2031 of the control module 201 is connected to the control terminal 301 of the first DC regulated power supply 30 and the output terminal of the control module 201 2032 is connected to the control terminal 302 of the first DC regulated power supply 30 . The output terminal 311 of the first DC stabilized power supply 30 is connected to the voltage input terminal 411 of the first core, wherein the control module 201 can control at least one monitoring module to work or shut down through the control terminal 2021 .

When a monitoring module is working, a monitoring module monitors a load state of the first core 40 . For example, when the first monitoring module 211, the second monitoring module 212, ... the Kth monitoring module 21K are all working, the first monitoring module 211 can monitor the voltage load state of the first The current load state of a core 40 , . . . the K-th monitoring module 21K monitors the idle time ratio of the first core 40 . These monitoring modules send the load state of the first core 40 to the control module 201, for example, the first monitoring module 211 sends the voltage load state of the first core to the control module 201, and the second monitoring module 212 sends the current load state of the first core The status is sent to the control module 201 . . . The Kth monitoring module 21K sends the proportion of idle time of the first core 40 to the control module 201 . The control module 201 generates a first voltage control signal to the first DC stabilized power supply 30 according to the received K load states of the first core 40 (ie, the first load state of the first core 40 ). Wherein, the first voltage control signal is used to control the first DC regulated power supply 30 to output a corresponding voltage to the first core 40, and the first DC regulated power supply 30 is used to output a corresponding voltage to the first core 40 according to the first voltage control signal. A core 40 power supply.

The load monitor used in the embodiment of the present invention can regulate the working voltage of each core according to the load state of each core, and can meet the different voltage requirements of multiple cores in a multi-core access point, thereby reducing the number of multi-core access points. The overall power consumption of the point.

Please refer to FIG. 4. FIG. 4 is a schematic structural diagram of a multi-core access point disclosed by an embodiment of the present invention. As shown in FIG. 4, the multi-core access point includes a voltage source and N cores (as shown in FIG. 4 1031, 1032, 1033, ... 103N), N DC power supplies (1021, 1022, ... 102N shown in Figure 4) and N load monitors (1041, 1042, 1043, ... 104N), where:

Each core is correspondingly connected to a DC stabilized power supply and a load monitor, as shown in Figure 4, the core 1031 is correspondingly connected to the DC stabilized power supply 1021 and the load monitor 1041; the core 1032 is correspondingly connected to the DC stabilized power supply 1022 and the load monitor 1042 ; the core 103i is correspondingly connected to the DC stabilized power supply 102k and the load monitor 104j; the core 103N is correspondingly connected to the DC stabilized power supply 102N and the load monitor 104N. Each core is only connected to a DC stabilized power supply and a load monitor, and each core is connected to a different DC stabilized power supply, and each core is connected to a different load monitor. Each DC regulated power supply corresponds to a load monitor and a core, and each DC regulated power supply is connected to different load monitors.

The voltage source 101 is connected to N DC regulated power supplies (1021, 1022, ... 102N shown in FIG. 4), and the first load monitor (for example, 1041 shown in FIG. For example, the first load state of 1031) shown in FIG. 1021), the first DC stabilized power supply outputs the target output voltage corresponding to the first voltage control signal to the first core according to the corresponding relationship between the voltage control signal and the output voltage; the first load monitor is among the N load monitors Any one of the N cores, the first core is any one of the N cores, and the first DC regulated power supply is any one of the N DC regulated power supplies.

Wherein, the first load state includes at least one of the load rate, current, power, frequency, idle time ratio, waiting interrupt duration, temperature and cache hit rate of the first core.

Wherein, the first DC regulated power supply includes a low dropout linear voltage regulator or a DC chopper.

In the multi-core access point of the embodiment of the present invention, the load monitor in the multi-core access point regulates the operating voltage of each core according to the load state of each core, which can meet the different requirements of multiple cores in the multi-core access point. The voltage requirements of the multi-core access point can be reduced, thereby reducing the overall power consumption of the multi-core access point.

Please refer to FIG. 5. FIG. 5 is a schematic flowchart of a power supply method based on a multi-core access point architecture disclosed by an embodiment of the present invention, wherein the multi-core access point includes at least two cores, at least two DC voltage sources and For at least two load monitors, as shown in FIG. 5 , the power supply method includes the following steps.

501. The first load monitor monitors the first load status of the first core, where the first load monitor is any one of at least two load monitors of the multi-core access point, and the first core is the Either of at least two cores.

In the embodiment of the present invention, the first load monitor can monitor the first load state of the first core in real time, and can monitor the first load state of the first core periodically or aperiodically.

The first load state includes at least one of the load rate, current, power, frequency, idle time ratio, waiting interrupt duration, temperature and cache hit rate of the first core.

502. The first load monitor generates a first voltage control signal corresponding to the first load state according to the correspondence between the load state and the voltage control signal, and outputs the first voltage control signal to the first DC regulated power supply.

Wherein, the first voltage control signal includes at least one voltage enable signal, and the manner in which the first load monitor outputs the first voltage control signal to the first DC regulated power supply is specifically:

The first load monitor outputs at least one voltage enable signal to the first DC regulated power supply; at least one voltage enable signal is used for the first DC regulated power supply to output according to the corresponding relationship between the voltage enable signal combination and the output voltage A target output voltage corresponding to at least one voltage enable signal to the first core.

In the embodiment of the present invention, the number of at least one voltage enable signal is M (M is greater than or equal to 1), if the voltage enable signal is "0" or "1", then there are 2 ^M voltage enable signal combinations (2 to the Mth power). For example, if the number of voltage enable signals is 2, the voltage enable signals can have four combinations of "00", "01", "10", and "11", that is, the first DC stabilized power supply can output 4 different voltages.

503. The first DC stabilized power supply outputs a target output voltage corresponding to the first voltage control signal to the first core according to the correspondence between the voltage control signal and the output voltage.

In the embodiment of the present invention, the load monitor may pre-store the corresponding relationship between the load state and the voltage control signal, and different load states correspond to different voltage control signals. The load monitor can output various voltage control signals to the first DC regulated power supply, so as to control the first DC regulated power supply to output different voltages to the first core. The voltage control signal here may include multiple enable signals, for example, if the voltage control signal may include 2 enable signals, then there may be 4 types of voltage control signals, that is, the first DC stabilized power supply may be controlled to output 4 different voltage; if the voltage control signal can include 3 enable signals, then there can be 8 kinds of voltage control signals, that is, the first DC regulated power supply can be controlled to output 8 different voltages; if the voltage control signal can include N enabling signals There are 2 ^N types of voltage control signals, that is, the first DC regulated power supply can be controlled to output 2 ^N different voltages.

The power supply method adopted in the embodiment of the present invention can regulate the operating voltage of each core according to the load status of each core, and can meet the different voltage requirements of multiple cores in the multi-core access point, thereby reducing the power consumption of the multi-core access point. the overall power consumption.

An embodiment of the present invention also provides a computer storage medium, wherein the computer storage medium can store a program, and the program includes some or all steps of any power supply method described in the above method embodiments when executed.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence. Because of the present invention, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or can be Integrate into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory. Several instructions are included to make a computer device (which may be a personal computer, server or network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above-mentioned embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash disk , Read-only memory (English: Read-Only Memory, abbreviated: ROM), random access device (English: Random Access Memory, abbreviated: RAM), magnetic disk or optical disk, etc.

The embodiments of the present invention have been described in detail above, and specific examples have been used in this paper to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only used to help understand the method and core idea of the present invention; at the same time, for Those skilled in the art will have changes in the specific implementation and scope of application according to the idea of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (10)

1. a kind of method of supplying power to based on multi-core access point architecture, it is characterised in that the multi-core access point is included at least Two cores, at least two direct voltage sources and at least two load monitors, the method for supplying power to include：

First load monitor monitors the first load condition of the first core, and first load monitor is described at least two Any one in load monitor, first core is any one at least two core；

Corresponding relation generation and described first load of first load monitor according to load condition and voltage control signal The corresponding first voltage control signal of state, and the first voltage control signal is exported to the first D.C. regulated power supply；Institute It is any one at least two direct voltage source to state the first D.C. regulated power supply, the first voltage of direct-flow voltage regulation correspondence Connect first load monitor and first core, the first core correspondence connection first load monitor；

Wherein, the first voltage control signal is used for first D.C. regulated power supply according to voltage control signal and output electricity The corresponding relation of pressure exports target output voltage corresponding with the first voltage control signal to first core.

2. method according to claim 1, it is characterised in that the first voltage control signal includes at least one voltage Signal is enabled, first load monitor exports to the first D.C. regulated power supply the first voltage control signal, including：

At least one voltage is enabled signal output to first D.C. regulated power supply by first load monitor；Institute State at least one voltage and enable signal for first D.C. regulated power supply according to voltage enable signal combination and output voltage Corresponding relation output enable the corresponding target output voltage of signal to first core with least one voltage.

3. method according to claim 2, it is characterised in that if the number that the voltage enables signal is M, the electricity Pressure enables signal combination 2^MIndividual, the M is the integer more than or equal to 1.

4. the method according to claim any one of 1-3, it is characterised in that first load monitor monitors the first core First load condition of the heart includes：

First load monitor periodically monitors the first load condition of first core.

5. the method according to claim any one of 1-4, it is characterised in that first load condition includes described first The load factor of core, electric current, power, frequency, free time accounting, etc. in duration to be interrupted, temperature and cache hit rate extremely Few one kind.

6. a kind of multi-core access point, it is characterised in that including a voltage source and N number of core, it is characterised in that the multinuclear Heart access point also includes N number of D.C. regulated power supply and N number of load monitor, wherein：

Each core correspondence connection one D.C. regulated power supply and a load monitor, the direct current of each core correspondence connection are steady Voltage source is differed, and the load monitor of each core correspondence connection is differed；

Each D.C. regulated power supply correspondence connection one load monitor and a core, each D.C. regulated power supply correspondence are connected Load monitor differ；

The voltage source connects N number of D.C. regulated power supply, the first core of the first load monitor monitoring correspondence connection First load condition, and it is straight that first for correspondingly connecting is sent to according to first load condition generation first voltage control signal Stream voltage-stabilized power supply, first D.C. regulated power supply according to the corresponding relation of voltage control signal and output voltage export with it is described The corresponding target output voltage of first voltage control signal is to the first core；First load monitor is N number of load Any one in monitor, first core is any one in N number of core, and first D.C. regulated power supply is institute Any one in N number of D.C. regulated power supply is stated, the N is the positive integer more than or equal to 2.

7. multi-core access point according to claim 6, it is characterised in that the load monitor include control module and Monitoring modular, wherein：

The monitoring side of the monitoring modular connects the signal output part of first core, the output end connection of the monitoring modular The input of the control module, the control end of the control module connects the input of the monitoring modular, the control mould The output end of block connects the control end of first D.C. regulated power supply, the output end connection institute of first D.C. regulated power supply The voltage input end of the first core is stated, the input connection voltage source of first D.C. regulated power supply, the control module is used In the control monitoring modular work or closing.

8. multi-core access point according to claim 7, it is characterised in that

When the monitoring modular works, the first load condition described in the monitoring module monitors, the monitoring modular will be described First load condition is sent to the control module, and the control module generates voltage control letter according to first load condition Number to first D.C. regulated power supply, the voltage control signal is used to control the first D.C. regulated power supply output corresponding Voltage to first core, first D.C. regulated power supply is used for different according to different voltage control signal output Voltage is powered to first core.

9. the multi-core access point according to claim any one of 6-8, it is characterised in that first load condition includes The load factor of first core, electric current, power, frequency, free time accounting, etc. duration to be interrupted, temperature and cache hit At least one in rate.

10. the multi-core access point according to claim any one of 6-9, it is characterised in that the first DC voltage-stabilizing electricity Source includes low pressure difference linear voltage regulator or dc chopper.