CN106793495A - A kind of groove pcb board structure and its manufacture method for bare chip test - Google Patents

Abstract

The invention provides a grooved PCB board structure and a manufacturing method thereof for bare chip testing. Firstly, a PCB board is processed, a groove having the same area and shape as the bare chip is processed on it, and flow guide grooves and solder joints are processed. Then add an insulating medium layer between the two PCB boards, and press the two PCB boards together, and the opposite side of the two PCB boards does not process the pads; use a drilling tool to open the connection on the pressed PCB board Through holes; finally bond the bare chip at the groove, and use the ultrasonic thermocompression welding bonding process to complete the gold wire bonding of the bare chip metal PAD and the pad on the PCB. The invention is simple in structure, low in cost, easy to process, reduces the difficulty of PCB board design, and can better avoid the pollution of bare chip metal PAD when the conductive glue overflows.

Description

A kind of groove PCB board structure and manufacturing method thereof for bare chip test

technical field

The invention relates to the field of semiconductor integrated circuit testing, in particular to a PCB board structure used for bare chip testing and a manufacturing method thereof.

Background technique

At present, after the chip tape-out is completed, the bare chip must be packaged in plastic material or ceramic material to provide environmental protection before it can be soldered on the PCB board for testing. As the competition in the electronic product market becomes more and more fierce, chip manufacturers need to launch chip products at a faster speed to occupy the early market and strive for more profits. However, the packaging cycle will take up valuable testing time and slow down the pace of product marketization. Wafer-level testing can test bare chips through wafer probes and special test benches, but only relatively simple testing tasks can be completed, and there are many limitations in testing the actual functions of chips. The current PCB boards are mostly used to carry the packaged chips, and there is no PCB board design and processing specifically for carrying bare chip tests. And the larger the area of the bare chip, the more conductive glue is needed for direct bonding on the PCB. If too much glue is used, when the bare chip is pressed on the PCB, the conductive glue will be on the side of the bare chip. Spill, it is easy to adhere to the metal PAD of the bare chip, causing a short circuit between the metal PADs, resulting in the scrapping of the bare chip.

Contents of the invention

In order to overcome the deficiencies of the prior art, the present invention provides a PCB board structure for bare chip testing and a manufacturing method thereof, so as to realize the testing of bare chips on the PCB board under laboratory conditions.

The technical solution adopted by the present invention to solve the technical problem is: a PCB board structure used for bare chip testing, the PCB board adopts a rigid board PCB, and a groove is formed on the surface of one side of the PCB board, the shape of the groove, The area is the same as that of the bare chip, the depth is equal to the thickness of the bare chip, and there are diversion grooves at the four corners of the groove; there are metal pads distributed around the groove, and the position and number of the metal pads are consistent with the metal PAD of the bare chip. The electrical connection between the bare chip and the PCB board; corresponding to each metal pad, there is a connection through hole through the PCB board, which leads the electrical connection of the bare chip metal PAD to the other side of the PCB board.

The PCB board is formed by bonding two PCB boards through an insulating medium layer.

The present invention also provides a method for preparing the above-mentioned PCB board structure for bare chip testing, comprising the following steps: firstly process a PCB board, process a groove on it with the same area and shape as the bare chip, and process the diversion groove and pads; then add an insulating dielectric layer between the two PCB boards, and press the two PCB boards, and the opposite side of the two PCB boards does not process the pads; use a drilling tool on the pressed PCB board Open the connection through hole; finally bond the bare chip at the groove, and use the ultrasonic thermocompression welding bonding process to complete the gold wire bonding between the metal PAD of the bare chip and the pad on the PCB.

The beneficial effects of the present invention are:

1. The present invention is simple in structure, low in cost, easy to process, and has better implementability in engineering applications;

2. The design of the ear-shaped conductive adhesive diversion structure can better avoid the pollution of the bare chip metal PAD when the conductive adhesive overflows;

3. The groove carrying the bare chip has a fixed position for the bonding of the bare chip, which is convenient for the bonding of the bare chip;

4. Divided into two independent plates to form the final PCB board, combined with the settings for connecting through holes on the front and back of the PCB board, it reduces the difficulty of PCB board design and avoids the difficulty of precision control of drill bit milling grooves.

Description of drawings

Fig. 1 is a kind of PCB board plan view that is used for bare chip test of the present invention;

Fig. 2 is the lamination schematic diagram of PCB board of the present invention;

Fig. 3 is a top view of the first PCB board of the PCB of the present invention;

Fig. 4 is the top view of the second PCB board of the PCB of the present invention;

Fig. 5 is a kind of PCB board preparation process flowchart that is used for bare chip test of the present invention;

6(a)-6(h) are schematic diagrams of a PCB board preparation process for bare chip testing according to the present invention.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings and embodiments, and the present invention includes but not limited to the following embodiments.

As shown in FIG. 1 , the present invention is composed of a PCB board 101 , a bare chip 102 , a groove 103 , an ear structure 104 , a metal pad 105 , a connection through hole 106 , and a bonding wire 107 . As shown in Figure 2, the PCB board 101 is made up of a first PCB board 201, a second PCB board 202, and an insulating medium layer 203, and the insulating medium layer 203 is used for bonding between the first PCB board 201 and the second PCB board 202, At the same time, electrical short circuit between the first PCB board 201 and the second PCB board 202 is avoided. As shown in FIG. 3 , the first PCB board 201 is provided with a through-hole copper-avoidance area 301, which is used to avoid the non-ground network communication between the metal ground layer of the first PCB board 201 and the connection through-hole 106 caused when the through-hole 106 is metallized. Short circuit between holes. As shown in FIG. 4 , the second PCB board 202 is provided with a groove 103 , an ear-shaped structure 104 , and a through-hole copper avoidance area 401 . The thickness of the groove 103 is equal to the thickness of the bare chip 102 , and the area and shape are consistent with the bare chip 102 , used to carry and fix the bare chip 102, the ear-shaped structure 104 is located on the four corners of the groove 103, the thickness is equal to the thickness of the bare chip 102, and is used to guide the excess conductive glue, and the copper-avoiding area 401 of the through hole is used The short circuit between the metal ground layer of the second PCB board 202 and the non-ground network via hole in the connection via hole 106 caused by the metallization of the via hole 106 is avoided.

The preparation process of a grooved PCB board structure used for bare chip testing provided by the present invention is shown in FIG. 5 .

The preparation process of a recessed PCB board structure for bare chip testing and its manufacturing method according to the present invention will be further described in detail with reference to FIGS. 6(a)-6(h).

A grooved PCB board structure for bare chip testing, the specific steps are as follows:

In step 1, the first PCB board 201 is processed, as shown in FIG. 6( a ).

(1a) cutting, cutting the double-sided copper-clad substrate to the required size;

(1b) Exposure, apply a photosensitive liquid on one side of the copper-clad substrate, dry at 80°C, and use a mask plate to expose with an ultraviolet exposure machine;

(1c) Etching, using a single-side etching process to form electrical traces and through-hole copper-avoiding regions 301 .

In step 2, the second PCB board 202 is processed, as shown in FIG. 6( b ).

(2a) cutting, cutting the double-sided copper-clad substrate to the required size;

(2b) Exposure, apply a photosensitive liquid on one side of the copper-clad substrate, dry at 80°C, and use a mask plate to expose with an ultraviolet exposure machine;

(2c) Etching, using a single-sided etching process to form electrical traces and through-hole copper-avoiding areas 401;

In step 3, the groove 103 and the ear-shaped structure 104 are processed, as shown in FIG. 6(c). The machining of the groove 103 and the ear-shaped structure 104 is completed by a drilling and milling process.

Step 4, the first PCB board 201 and the second PCB board 202 are pressed together, as shown in FIG. 6( d ).

(4a) Copper surface is roughened, and copper surface passivation is carried out to the bonding surface of first PCB board 201 and second PCB board 202 by using browning liquid medicine or blackening liquid medicine, to increase the surface area of resin and copper surface, increase The copper surface wets the resin flow to avoid adverse reactions.

(4b) Stacking boards, stacking the first PCB board 201 , the insulating medium layer 203 , and the second PCB board 202 together sequentially, and fixing them with rivets.

(4c) Pressing, pressing the first PCB board 201 , the insulating medium layer 203 , and the second PCB board 202 together by hot pressing to form the multilayer PCB board 101 .

(4d) Exposure, apply a photosensitive liquid on the top and bottom layers of the multilayer PCB board 101, dry at 80°C, and use a mask plate to expose with an ultraviolet exposure machine;

(4e) Etching, using the outer layer etching process to form electrical traces and metal pads 105;

Step 5, drilling through holes, as shown in Figure 6(e). Drilling tools are used to form connection vias 106 on the multi-layer PCB 101 , and the drilled areas should be within the through-hole copper-avoiding area 301 of the first PCB 201 and the through-hole copper-avoiding area 401 of the second PCB 202 .

Step 6, through-hole metallization, as shown in Figure 6(f).

(6a) Electroless copper deposition, depositing a layer of chemical thin copper on the wall of the connecting through hole 106 and other copper surfaces, for forming an electrical connection on the wall of the non-conductive connecting through hole 106;

(6b) electroplating copper, electroplating a layer of thin copper on the wall of the connecting through hole 106 and other copper surfaces, for protecting the deposited chemical thin copper;

(6c) electroplating nickel, electroplating a layer of metal nickel on the wall of the connection through hole 106 and other copper surfaces, used as a barrier layer between the copper layer and the gold layer, to prevent mutual diffusion of gold and copper;

(6d) Electroplating gold, electroplating a layer of soft gold on the wall of the connecting through hole 106 and other copper surfaces to form the metallization of the through hole and the gold-plated pad 105 .

Step 7, the bare chip 102 is bonded, as shown in FIG. 6(g). The bare chip 102 is bonded in the groove 103 of the multi-layer PCB 101 with conductive glue, and excess conductive glue will flow into the ear-shaped structure 104 .

Step 8, the bare chip 102 is bonded, as shown in FIG. 6(h). The gold wire 107 is used to complete the bonding of the metal PAD of the bare chip 102 and the metal pad 105 on the second PCB 202 through an ultrasonic thermocompression bonding process, and finally complete the grooved PCB structure for bare chip testing.

Claims (3)

1. a kind of groove pcb board structure for bare chip test, it is characterised in that：Described pcb board uses hardboard PCB, PCB The side surface of plate one is provided with groove, and the shape of groove, area are consistent with bare chip, and depth is equal to bare chip thickness, the corner of groove It is provided with guiding gutter；The groove surrounding is distributed with metal pad, and the position of metal pad and quantity keep with bare chip metal PAD Unanimously, for the electrical connection between bare chip and pcb board；Corresponding each metal pad has a connection through pcb board to lead to Hole, pcb board opposite side is caused by the electrical connection of bare chip metal PAD.

2. the groove pcb board structure for bare chip test according to claim 1, it is characterised in that：Described pcb board It is bonded by insulating medium layer using two pieces of pcb boards.

3. the manufacture method of the groove pcb board structure of bare chip test is used for described in a kind of claim 1, it is characterised in that including Following step：One piece of pcb board is processed first, thereon processing and bare chip area and equiform groove, and process water conservancy diversion Groove and pad；Then insulating medium layer is added between two pieces of pcb boards, and two pcb boards is pressed, two pieces of pcb boards are relative Pad is not processed simultaneously；Connection through hole is opened on pcb board using boring bar tool after pressing；It is last to bond naked core in groove Piece, the gold wire bonding of bare chip metal PAD and pad on pcb board is completed using ultrasonic-thermocompression welding bonding technology.