CN106783951B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN106783951B CN106783951B CN201611207152.4A CN201611207152A CN106783951B CN 106783951 B CN106783951 B CN 106783951B CN 201611207152 A CN201611207152 A CN 201611207152A CN 106783951 B CN106783951 B CN 106783951B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 9
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
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- 230000008569 process Effects 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
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- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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Abstract
The second groove for forming the pseudo gate region is filled with a dielectric material, so that a gate material and an isolation layer in a pseudo gate structure in the prior art are replaced, and the phenomenon that capacitance is formed among the gate material, the isolation layer and a collector in the pseudo gate structure in the prior art is avoided, so that the input capacitance of the semiconductor device is increased, the response speed of the semiconductor device is influenced, and the response speed of the semiconductor device is improved.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and more particularly, to a semiconductor device and a method for forming the same.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a Bipolar Transistor (BJT) and an Insulated Gate field effect Transistor (MOSFET), and has the advantages of both high input impedance of the MOSFET device and low on-state voltage drop of a power Transistor (i.e., a giant Transistor, GTR for short), so that the IGBT is widely used in various fields.
The structure of the IGBT device in the prior art is shown in fig. 1, and includes: the semiconductor device comprises a semiconductor substrate 100, wherein the semiconductor substrate 100 is sequentially provided with a collector region 101, a drift region 102, a charge accumulation layer 103 and a base region 104 from bottom to top; the upper surface of the semiconductor substrate 100 is provided with a gate region and a dummy gate region which penetrate through the base region 104 and the charge accumulation layer 103, the dummy gate region is located at a preset position on the side edge of the gate region, the gate region comprises a polysilicon layer 111 and isolation layers 112 and 113 which wrap the outer side of the polysilicon layer 111, and the dummy gate region comprises a polysilicon layer 121 and an isolation layer 122 which is located between the polysilicon layer 121 and the semiconductor substrate 100; and an emitter region 105 located within an upper surface of the semiconductor substrate 100; an emitter 106 covering the upper surface of the semiconductor substrate and a collector 107 covering the lower surface of the semiconductor substrate.
The side edge of the gate region is provided with the dummy gate region, so that the influence of an electric field in the base region 104 on the side, deviating from the gate region, of the dummy gate region on the gate region can be shielded, the electric field distribution is effectively improved, and the withstand voltage of the device is improved.
However, the IGBT device with this structure has a slow response speed.
Disclosure of Invention
In order to solve the above technical problem, embodiments of the present application provide a semiconductor device and a method for forming the same, which improve the response speed of the device.
In order to solve the above problems, the embodiments of the present invention provide the following technical solutions:
a semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, a first electrode, a second electrode and a control circuit, wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, a drift region of a first conduction type is arranged between the first surface and the second surface, a base region of a second conduction type is arranged between the drift region and the first surface, and a collector region of the second conduction type is arranged between the drift region and the second surface;
a plurality of first grooves and second grooves penetrating through the base region are formed in the first surface of the semiconductor substrate, and the first grooves comprise gate materials and isolating layers located between the gate materials and the semiconductor substrate; filling a dielectric material in the second groove;
a plurality of first conductive type emitting regions corresponding to the first grooves are arranged in the first surface of the semiconductor substrate, and the emitting regions are connected with the isolating layers of the first grooves;
an emitter and a gate electrode are arranged on the first surface of the semiconductor substrate, the emitter is electrically connected with the emitter region, and the gate electrode is electrically connected with the gate material;
and a collector electrode is arranged on the second surface of the semiconductor substrate and is electrically connected with the collector region.
Preferably, the opening size of the first trench is larger than the opening size of the second trench.
Preferably, the dielectric material is a material with a dielectric constant K less than or equal to 11.9.
Preferably, the dielectric material is silicon dioxide, silicon nitride, silicon oxynitride, or a material having a dielectric constant K less than or equal to 3.9.
Preferably, 2 adjacent first grooves are taken as a first groove group, and a preset number of second grooves are located at a preset position on one side of the first groove group;
the emitting regions and the first grooves are arranged in a one-to-one correspondence mode, and the emitting regions are located between 2 adjacent first grooves.
Preferably, in the preset number of second trenches, the dielectric material in at least 1 of the second trenches is grounded.
Preferably, the preset number is at least 2.
Preferably, in the preset number of second trenches, the base region between 2 adjacent second trenches is used as the first base region, and at least 1 first base region is grounded.
A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, a drift region of a first conduction type is arranged between the first surface and the second surface, a base region of a second conduction type is arranged between the drift region and the first surface, and a collector region of the second conduction type is arranged between the drift region and the second surface;
forming a plurality of first trenches and second trenches penetrating through the base region on the first surface of the semiconductor substrate;
filling a dielectric material in the second groove;
forming an isolation layer and a gate material in the first trench, the isolation layer being located between the gate material and the semiconductor substrate;
forming a plurality of first conductive type emitter regions corresponding to the first grooves in the first surface of the semiconductor substrate, wherein the emitter regions are connected with the isolation layers of the first grooves;
forming an emitter electrode and a gate electrode on the first surface of the semiconductor substrate, wherein the emitter electrode is electrically connected with the emitter region, and the gate electrode is electrically connected with the gate material;
and forming a collector electrode on the second surface of the semiconductor substrate, wherein the collector electrode is electrically connected with the collector region.
Preferably, the opening size of the first trench is larger than the opening size of the second trench.
Preferably, the filling of the dielectric material in the second trench includes:
depositing a dielectric material on the first surface of the semiconductor substrate until the second groove is completely filled with the dielectric material;
and etching the dielectric material on the first surface until the dielectric material in the first groove is completely removed.
Preferably, a plurality of first trenches and second trenches penetrating through the base region are formed in the first surface of the semiconductor substrate, wherein 2 adjacent first trenches are a first trench group, and a preset number of second trenches are located at preset positions on one side of the first trench group;
and forming a plurality of first-conductivity-type emitter regions corresponding to the first trenches in the first surface of the semiconductor substrate, wherein the emitter regions are arranged in one-to-one correspondence with the first trenches, and the emitter regions are positioned between 2 adjacent first trenches.
Preferably, the method further comprises the following steps:
and grounding the dielectric material in at least 1 second groove in the preset number of second grooves.
Preferably, the method further comprises the following steps:
the preset number is at least 2, and base regions between every two adjacent second trenches in the second trenches with the preset number are used as first base regions;
grounding at least 1 of the first base regions.
Compared with the prior art, the invention has the beneficial effects that:
according to the semiconductor device and the forming method of the semiconductor device, the second groove for forming the pseudo gate region is filled with the dielectric material, so that a gate material and an isolation layer in a pseudo gate structure in the prior art are replaced, and the phenomenon that capacitance is formed among the gate material, the isolation layer and a collector in the pseudo gate structure in the prior art is avoided, so that the input capacitance of the semiconductor device is increased, the response speed of the semiconductor device is influenced, and the response speed of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a schematic cross-sectional structure of a prior art IGBT device;
fig. 2 is a schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional structure diagram of a semiconductor device according to a second embodiment of the present invention;
fig. 4 is a flowchart of a method for forming a semiconductor device according to a third embodiment of the present invention;
fig. 5 to 7 are schematic cross-sectional structures of IGBT devices according to a third embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As described in the background art, in the IGBT device in the prior art, the dummy gate region is disposed at the preset position on the side of the gate region, so that the influence of the electric field in the base region 104 on the side of the dummy gate region away from the gate region on the gate region can be shielded, the electric field distribution can be effectively improved, and the withstand voltage of the device can be improved.
However, the inventors have sent that the response speed of the IGBT device with such a structure is slow. The reason is that the dummy gate structure generally includes a gate material (such as heavily doped polysilicon) and an isolation layer, and a capacitor is formed between the gate material and the isolation layer in the dummy gate structure and a collector of the device, and the capacitor contributes to an input capacitor in the device operation process, so that the input capacitor of the semiconductor device is increased, the response speed of the semiconductor device is affected, and the response speed of the conductor device is further increased.
In view of the above, the present invention provides a semiconductor device including:
the semiconductor device comprises a semiconductor substrate, a first electrode, a second electrode and a control circuit, wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, a drift region of a first conduction type is arranged between the first surface and the second surface, a base region of a second conduction type is arranged between the drift region and the first surface, and a collector region of the second conduction type is arranged between the drift region and the second surface;
a plurality of first grooves and second grooves penetrating through the base region are formed in the first surface of the semiconductor substrate, and the first grooves comprise gate materials and isolating layers located between the gate materials and the semiconductor substrate; filling a dielectric material in the second groove;
a plurality of first conductive type emitting regions corresponding to the first grooves are arranged in the first surface of the semiconductor substrate, and the emitting regions are connected with the isolating layers of the first grooves;
an emitter and a gate electrode are arranged on the first surface of the semiconductor substrate, the emitter is electrically connected with the emitter region, and the gate electrode is electrically connected with the gate material;
and a collector electrode is arranged on the second surface of the semiconductor substrate and is electrically connected with the collector region.
Specifically, the semiconductor substrate of the present invention may be a silicon substrate, a germanium substrate, or the like, so as to implement corresponding functions in the field, and the present invention is not limited thereto. Also, the first conductive type of the semiconductor substrate may be either a P type or an N type, and the second conductive type is another conductive type having a polarity opposite to that of the first conductive type. Specifically, when the first conductivity type is N-type, the second conductivity type is P-type; and when the first conduction type is a P type, the second conduction type is an N type.
In addition to the above structure, the semiconductor substrate of the present invention may further include a buffer layer, a charge accumulation layer, and other functional layers to further improve the electrical performance of the device.
And in the first surface of the semiconductor substrate, a plurality of first trenches penetrating the base region are used for forming a gate region, and a plurality of second trenches penetrating the base region are used for forming a dummy gate region. In a semiconductor device, a plurality of cells are generally included, and the plurality of cells include the same structure, thereby forming a semiconductor device having the same characteristics. Therefore, in the semiconductor device, different cell structures may form a semiconductor device of a different structure. In the embodiment of the present invention, the semiconductor device may include two types of structures, from the viewpoint of the structure of the cell, one is a gate formed by one gate region, the emitter regions are located on both sides of the gate region, the other is a gate formed by two gate regions, and two emitter regions connected to the gate regions respectively are located between the two gate regions. In the embodiments of the present application, these two structures will be specifically described.
According to the invention, the second trench for forming the dummy gate region is filled with the dielectric material, so that a gate material and an isolation layer in a dummy gate structure in the prior art are replaced, and the phenomenon that capacitance is formed among the gate material, the isolation layer and a collector in the dummy gate structure in the prior art is avoided, so that the input capacitance of the semiconductor device is increased, the response speed of the semiconductor device is influenced, and the response speed of the semiconductor device is improved.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Referring to fig. 2, fig. 2 is a schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present invention, including:
the semiconductor device includes a semiconductor substrate 200, where the semiconductor substrate 200 includes a first surface and a second surface opposite to the first surface, where the first surface is an upper surface and the second surface is a lower surface in fig. 2. A drift region 202 of the first conductivity type is included between the first surface and the second surface, a base region 204 of the second conductivity type is included between the drift region 202 and the first surface, and a collector region 201 of the second conductivity type is included between the drift region 202 and the second surface;
specifically, in this embodiment, a first conductivity type charge accumulation layer 203 is further included between the drift region 202 and the base region 204, and a first conductivity type buffer region 208 is further included between the drift region 202 and the collector region 201, so as to further improve the electrical performance of the device.
In an embodiment of the invention, the semiconductor substrate is a silicon substrate, the first conductivity type is N-type, and the second conductivity type is P-type. The N-type ions comprise phosphorus ions, arsenic ions, antimony ions and the like, and the P-type ions comprise boron ions and the like. The materials of the drift region 202, the charge accumulation layer 203 and the buffer region 208 are monocrystalline silicon doped with N-type ions, such as phosphorus ions; the material of the base region 204 and the collector region 201 is monocrystalline silicon doped with P-type ions, for example, boron ions.
A plurality of first trenches 210 and second trenches 220 are provided in the first surface of the semiconductor substrate 200 to penetrate the base region. The first groove is used for forming a gate region, and the second groove is used for forming a dummy gate region. In this embodiment, the opening size of the first trench is larger than the opening size of the second trench. The opening dimension refers to the dimension of the cross section (perpendicular to the paper) of the groove. By setting the opening size of the first trench to be larger than the opening size of the second trench, the size of the device can be reduced, and meanwhile, the specific operation in the process is easy.
In this embodiment, fig. 2 is a structural diagram of one cell. The first trench 210 comprises a gate material 211 and an isolation layer 212 between the gate material 211 and the semiconductor substrate; the gate material in this embodiment is covered with an insulating layer 213 to insulate the emitter 206. Specifically, the isolation layer 212 may be silicon oxide, and may be formed by a thermal oxidation method. The gate material 211 may be polysilicon, and the gate material may be formed by a deposition method. The insulating layer 213 may be silicon oxide, and may be formed by performing a thermal oxidation method on the gate electrode.
The second trench 220 is filled with a dielectric material 221, specifically, the dielectric material filled in the second trench may be silicon dioxide. In other embodiments of the present invention, the dielectric material may be a material having a dielectric constant K less than or equal to 11.9, specifically, the dielectric material is silicon dioxide, silicon nitride, silicon oxynitride, or a material having a dielectric constant K less than or equal to 3.9 (low-K material).
Further, in the present embodiment, a plurality of first conductive type emitter regions 205 corresponding to the first trenches 210 are disposed in the first surface of the semiconductor substrate 200, and the emitter regions are connected to the isolation layer in the first trenches. Specifically, in one cell in the embodiment, a gate is formed by one gate region, one gate corresponds to two emitter regions 205, and the two emitter regions 205 are respectively located at two sides of the gate region. The material of the emitter region 205 is monocrystalline silicon doped with N-type, such as arsenic ions and phosphorus ions.
In this embodiment, an emitter and a gate electrode are further disposed on the first surface of the semiconductor substrate 200, the emitter 206 is electrically connected to the emitter region 205, and the gate electrode 214 is electrically connected to the gate material 211; a collector electrode 207 is disposed on the second surface of the semiconductor substrate 200, and the collector electrode 207 is electrically connected to the collector region 201.
The emitter 206 and the collector 207 are metal electrodes, and may be formed by sputtering or depositing a metal material. The emitter is in direct contact with the emitter region to form electric connection; the collector electrode is in direct contact with the collector region 201, forming an electrical connection. In the embodiment, the emitter completely covers the first surface of the semiconductor substrate 200, so as to protect the semiconductor substrate 200, isolate the external air or moisture, and avoid the external air or moisture from corroding the semiconductor substrate 200.
In the semiconductor device, the second trench for forming the dummy gate region is filled with the dielectric material, so that a gate material and an isolation layer in a dummy gate structure in the prior art are replaced, and the phenomenon that capacitance is formed among the gate material, the isolation layer and a collector in the dummy gate structure in the prior art is avoided, so that the input capacitance of the semiconductor device is increased, the response speed of the semiconductor device is influenced, and the response speed of the semiconductor device is improved.
Example two
Referring to fig. 3, fig. 3 is a schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present invention.
In this embodiment, the semiconductor device includes:
a semiconductor substrate 300, wherein the semiconductor substrate 300 includes a first surface and a second surface opposite to the first surface, in fig. 3, the first surface is an upper surface of the semiconductor substrate, and the second surface is a lower surface of the semiconductor substrate. A drift region 302 of a first conductivity type is included between the first surface and the second surface, a base region 304 of a second conductivity type is included between the drift region and the first surface, and a collector region 301 of the second conductivity type is included between the drift region and the second surface;
specifically, in this embodiment, a first conductivity type charge accumulation layer 303 is further included between the drift region 302 and the base region 304, and a first conductivity type buffer region 308 is further included between the drift region 302 and the collector region 301, so as to further improve the electrical performance of the device.
In an embodiment of the invention, the semiconductor substrate is a silicon substrate, the first conductivity type is N-type, and the second conductivity type is P-type. The N-type ions comprise phosphorus ions, arsenic ions, antimony ions and the like, and the P-type ions comprise boron ions and the like. The materials of the drift region 302, the charge accumulation layer 303 and the buffer region 308 are monocrystalline silicon doped with N-type ions, such as phosphorus ions; the material of the base region 304 and the collector region 301 is monocrystalline silicon doped with P-type ions, for example, boron ions.
A plurality of first trenches 310 and second trenches 320 are provided in the first surface of the semiconductor substrate 300 to penetrate the base region. The first groove is used for forming a gate region, and the second groove is used for forming a dummy gate region. In this embodiment, the opening size of the first trench is larger than the opening size of the second trench. By setting the opening size of the first trench to be larger than the opening size of the second trench, the size of the device can be reduced, and the specific operation in the process is facilitated. Specifically, in this embodiment, the opening size of the first trench is 1.2 to 3 times the opening size of the second trench.
Fig. 3 is a structural diagram of a cell of the semiconductor device in this embodiment, in which the structure includes a gate formed by two gate regions, and two emitter regions connected to the gate regions respectively are located between the two gate regions. Specifically, in this embodiment, 2 adjacent first trenches are used as a first trench group, and a preset number of second trenches are located at a preset position on one side of the first trench group; specifically, the preset number is at least 2, and in this embodiment, the preset number is 4. The preset number of the second grooves can be set to be 1, 3, 5 or more by those skilled in the art according to actual requirements. The preset position is a position which is arranged on one side of the first groove group and is away from the first groove group by a preset distance. Note that the second groove cannot be provided between 2 first grooves of the first groove group.
The first trench 310 comprises a gate material 311 and an isolation layer 312 between the gate material 311 and the semiconductor substrate; specifically, the isolation layer 312 may be silicon oxide, and may be formed by a thermal oxidation method. The gate material 311 may be polysilicon, and the gate material may be formed by a deposition method.
The second trench 320 is filled with a dielectric material 321, specifically, the dielectric material filled in the second trench may be silicon dioxide. In other embodiments of the present invention, the dielectric material may also be a low-dielectric-constant material, and specifically, the low-dielectric-constant material has a dielectric constant K smaller than that of the semiconductor substrate material. Such as silicon dioxide, etc.
Further, in the present embodiment, a plurality of first conductive type emitter regions 305 corresponding to the first trenches 310 are disposed in the first surface of the semiconductor substrate 300, and the emitter regions are connected to the isolation layer in the first trenches. Specifically, in one cell in the embodiment, the emitting regions 305 and the first trenches 310 are arranged in a one-to-one correspondence, and the emitting regions 305 are located between 2 adjacent first trenches. The material of the emitter region 305 is single crystal silicon doped with N-type, for example, arsenic ions or phosphorous ions.
In another embodiment of the present invention, in the preset number of second trenches, at least 1 dielectric material in the second trench is grounded. Specifically, in this embodiment, 2 of the second trenches are grounded. And the dielectric material in the second groove is grounded, so that the input capacitance is further reduced, and the switching rate is improved.
Further, in another embodiment of the present invention, in the preset number of second trenches, the base region between 2 adjacent second trenches is used as the first base region 309, and at least 1 first base region is grounded. Specifically, in this embodiment, 2 of the first base regions are grounded. The first base region is grounded, so that the extraction of carriers during turn-off is facilitated, and the switching rate is further improved.
In this embodiment, in the preset number of second trenches, the dielectric material in at least 1 of the second trenches is electrically connected to the emitter 306; the base region between 2 adjacent second trenches is used as a first base region 309, and at least 1 first base region is electrically connected with the emitter 306 and grounded, so that extraction of carriers during turn-off is facilitated, and the switching rate is further improved.
In this embodiment, an emitter and a gate electrode are further disposed on the first surface of the semiconductor substrate 300, the emitter 306 is electrically connected to the emitter region 305, and the gate electrode 313 is electrically connected to the gate material 311; a collector electrode 307 is disposed on the second surface of the semiconductor substrate 300, and the collector electrode 307 is electrically connected to the collector region 301.
The emitter 306, the gate electrode 313, and the collector 307 are metal electrodes, and may be formed by sputtering or depositing a metal material. The emitter is in direct contact with the emitter region to form electric connection; the gate electrode 313 is in direct contact with the gate material 311, forming an electrical connection; the collector 307 is in direct contact with the collector region 301, forming an electrical connection. In this embodiment, the first surface of the semiconductor substrate 300 is further provided with an insulating layer 330 covering the first surface and exposing the gate electrode and the emitter, so as to protect the semiconductor substrate 300 from the external air or moisture, and prevent the semiconductor substrate 300 from being corroded by the external air or moisture.
In the semiconductor device, the second trench for forming the dummy gate region is filled with the dielectric material, so that a gate material and an isolation layer in a dummy gate structure in the prior art are replaced, and the phenomenon that capacitance is formed among the gate material, the isolation layer and a collector in the dummy gate structure in the prior art is avoided, so that the input capacitance of the semiconductor device is increased, the response speed of the semiconductor device is influenced, and the response speed of the semiconductor device is improved.
EXAMPLE III
The present embodiment provides a method for forming a semiconductor device, as shown in fig. 4, which is a flowchart of the method for forming a semiconductor device in the present embodiment, and includes:
step 101: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, a drift region of a first conduction type is arranged between the first surface and the second surface, a base region of a second conduction type is arranged between the drift region and the first surface, and a collector region of the second conduction type is arranged between the drift region and the second surface;
step 102: forming a plurality of first trenches and second trenches penetrating through the base region on the first surface of the semiconductor substrate;
step 103: filling a dielectric material in the second groove;
step 104: forming an isolation layer and a gate material in the first trench, the isolation layer being located between the gate material and the semiconductor substrate;
step 105: forming a plurality of first conductive type emitter regions corresponding to the first grooves in the first surface of the semiconductor substrate, wherein the emitter regions are connected with the isolation layers of the first grooves;
step 106: forming an emitter electrode and a gate electrode on the first surface of the semiconductor substrate, wherein the emitter electrode is electrically connected with the emitter region, and the gate electrode is electrically connected with the gate material;
step 107: and forming a collector electrode on the second surface of the semiconductor substrate, wherein the collector electrode is electrically connected with the collector region.
Fig. 5 to 7 show schematic cross-sectional structures of the IGBT device according to the embodiment of the invention.
Step 101 is executed, as shown in fig. 5, a semiconductor substrate is provided, where the semiconductor substrate 400 includes a first surface and a second surface opposite to the first surface, where the first surface is an upper surface and the second surface is a lower surface in fig. 5. A drift region 402 of a first conductivity type is included between the first surface and the second surface, a base region 404 of a second conductivity type is included between the drift region 402 and the first surface, and a collector region 401 of the second conductivity type is included between the drift region 402 and the second surface.
The semiconductor substrate may be a silicon substrate or a silicon carbide substrate. In this embodiment, the semiconductor substrate is a silicon substrate.
In addition, in this embodiment, a first conductivity type charge accumulation layer 403 is further included between the drift region 402 and the base region 404, and a first conductivity type buffer region 408 is further included between the drift region 402 and the collector region 401, so as to further improve the electrical performance of the device.
Specifically, the semiconductor substrate is a silicon substrate having ions of the first conductivity type, and in this embodiment, the semiconductor substrate is a silicon substrate having N-type ions.
Specifically, the silicon substrate of the present application may be implanted layer by means of ion implantation to form a corresponding functional layer.
Step 102 is executed, as shown in fig. 6, a plurality of first trenches 410 and second trenches 420 penetrating through the base region are formed on the first surface of the semiconductor substrate;
the first groove is used for forming a gate region, and the second groove is used for forming a dummy gate region. Specifically, a corresponding trench structure is formed according to a predetermined structure, and taking the trench structure in embodiment 2 of the present invention as an example, the structure includes a gate formed by two gate regions, and two emitter regions connected to the gate regions respectively are located between the two gate regions. Specifically, in this embodiment, 2 adjacent first trenches are used as a first trench group, and a preset number of second trenches are located at a preset position on one side of the first trench group; specifically, the preset number is at least 2, and in this embodiment, the preset number is 4. The preset number of the second grooves can be set to be 1, 3, 5 or more by those skilled in the art according to actual requirements. The preset position is a position which is arranged on one side of the first groove group and is away from the first groove group by a preset distance. Note that the second groove cannot be provided between 2 first grooves of the first groove group.
In this embodiment, the opening size of the first trench is larger than the opening size of the second trench. By setting the opening size of the first trench to be larger than the opening size of the second trench, the size of the device can be reduced, and the specific operation in the process is facilitated.
Specifically, the corresponding trench may be formed by etching. The method comprises the following specific steps:
and 21, forming a patterned mask on the first surface of the semiconductor substrate, wherein the mask exposes the semiconductor substrate at a preset position, and the preset position is a preset position for forming a first groove and a second groove.
And step 22, etching the semiconductor substrate to form a first groove and a second groove.
And step 23, removing the mask.
And etching the semiconductor substrate, wherein the etching depth is greater than the thickness of the base region.
Step 103 is executed to fill the second trench with a dielectric material 421.
The dielectric material filled in the second trench may be silicon dioxide. In other embodiments of the present invention, the dielectric material may also be a low dielectric constant material, and specifically, the low dielectric constant material is a material having a dielectric constant K less than or equal to 11.9. Such as silicon dioxide, etc.
Specifically, the method can comprise the following steps:
step 31, depositing a dielectric material on the first surface of the semiconductor substrate until the second trench is completely filled with the dielectric material;
and 32, etching the dielectric material on the first surface until the dielectric material in the first groove is completely removed.
The method comprises the steps of depositing a dielectric material on a first surface of a semiconductor substrate, filling the second groove with the dielectric material, enabling the first groove to be in a half-empty state, and etching the dielectric material. By reasonably controlling the etching time, the etching can obtain the result that only the second trench is completely filled with the dielectric material, and the dielectric material of the first trench is completely removed.
It can be seen that this step is technically easy to implement because the opening size of the first trench is larger than that of the second trench.
Next, step 104 is performed to form an isolation layer 412 and a gate material 411 within the first trench, the isolation layer being located between the gate material and the semiconductor substrate.
The first trench 410 comprises a gate material 411 and an isolation layer 412 between the gate material 411 and the semiconductor substrate; specifically, the isolation layer 412 may be silicon oxide, and may be formed by a thermal oxidation method. The gate material 411 may be polysilicon, and the gate material may be formed by a deposition method.
Step 105 is executed to form a plurality of emitter regions of the first conductivity type corresponding to the first trenches in the first surface of the semiconductor substrate, where the emitter regions are connected to the isolation layer of the first trenches.
In the present embodiment, a plurality of first conductive type emitter regions 405 corresponding to the first trenches 410 are disposed in the first surface of the semiconductor substrate 400, and the emitter regions are connected to the isolation layer in the first trenches. Specifically, in one cell in this embodiment, the emitting regions 405 and the first trenches 410 are disposed in a one-to-one correspondence, and the emitting region 305 is located between two adjacent first trenches. The material of the emitter region 405 is monocrystalline silicon doped with N-type, for example, arsenic ions or phosphorus ions.
Specifically, the corresponding emitter region 405 may be formed by ion implantation. The method comprises the following specific steps:
step 51, forming a patterned mask on the first surface of the semiconductor substrate, wherein the mask exposes the semiconductor substrate at a preset position, and the preset position is a preset position for forming the emitter region 405.
And step 52, performing ion implantation on the semiconductor substrate to form the emitter region.
Step 53, removing the mask.
And carrying out ion implantation on the semiconductor substrate, wherein the depth of the ion implantation is less than the thickness of the base region.
Next, step 106 and step 107 are performed, as shown in fig. 7, an emitter 406 and a gate electrode 413 are formed on the first surface of the semiconductor substrate, the emitter is electrically connected with the emitter region, and the gate electrode is electrically connected with the gate material; a collector electrode 407 is formed on the second surface of the semiconductor substrate and electrically connected to the collector region.
In this embodiment, an emitter and a gate electrode are formed on the first surface of the semiconductor substrate 400, the emitter 406 is electrically connected to the emitter region 405, and the gate electrode 413 is electrically connected to the gate material 411; a collector electrode 407 is disposed on the second surface of the semiconductor substrate 400, and the collector electrode 407 is electrically connected to the collector region 401.
The emitter 406, the gate electrode 413, and the collector 407 are metal electrodes, and may be formed by sputtering or depositing a metal material. The emitter is in direct contact with the emitter region to form electric connection; the gate electrode 413 is in direct contact with the gate material 411 to form an electrical connection; the collector electrode 407 is in direct contact with the collector region 401, forming an electrical connection. In this embodiment, the first surface of the semiconductor substrate 400 is further provided with an insulating layer 430 covering the first surface and exposing the gate electrode and the emitter, so as to protect the semiconductor substrate 400 from the external air or moisture, and prevent the semiconductor substrate 400 from being corroded by the external air or moisture.
In addition, in this embodiment, the method may further include:
step S108: and grounding the dielectric material in at least 1 second groove in the preset number of second grooves.
Specifically, in this embodiment, 2 of the second trenches are grounded. The dielectric material in the second groove is grounded, so that the input capacitance can be reduced, and the response speed of the semiconductor device is improved.
Step S109: the preset number is at least 2, and in the second trenches with the preset number, the base regions between the adjacent 2 second trenches are used as first base regions 409; grounding at least 1 of the first base regions.
Specifically, in this embodiment, 2 of the first base regions are grounded. The first base region is grounded, so that the extraction of carriers during the turn-off process is facilitated, and the switching rate of the device is further improved.
In addition, in this embodiment, the method may further include:
step S110: an insulating layer 430 is formed covering the first surface, which exposes the gate electrode 413 and the emitter 406.
The insulating layer 430 is used to protect the semiconductor substrate 300 from the external air or moisture, and prevent the semiconductor substrate 300 from being corroded by the external air or moisture.
In the forming method of the semiconductor device, the second groove for forming the pseudo gate region is filled with the dielectric material, so that a gate material and an isolation layer in a pseudo gate structure in the prior art are replaced, and the phenomenon that capacitance is formed among the gate material, the isolation layer and a collector in the pseudo gate structure in the prior art is avoided, so that the input capacitance of the semiconductor device is increased, the response speed of the semiconductor device is influenced, and the response speed of the semiconductor device is improved.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the device-like embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functions of the units may be implemented in the same software and/or hardware or in a plurality of software and/or hardware when implementing the invention.
The technical solutions provided by the present application are introduced in detail, and specific examples are applied in the description to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, a first electrode, a second electrode and a control circuit, wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, a drift region of a first conduction type is arranged between the first surface and the second surface, a base region of a second conduction type is arranged between the drift region and the first surface, and a collector region of the second conduction type is arranged between the drift region and the second surface;
a plurality of first grooves and second grooves penetrating through the base region are formed in the first surface of the semiconductor substrate, the first grooves comprise gate materials and isolating layers located between the gate materials and the semiconductor substrate, and the gate materials are polycrystalline silicon; filling a dielectric material in the second groove;
a plurality of first conductive type emitting regions corresponding to the first grooves are arranged in the first surface of the semiconductor substrate, and the emitting regions are connected with the isolating layers in the first grooves;
an emitter and a gate electrode are arranged on the first surface of the semiconductor substrate, the emitter is electrically connected with the emitter region, and the gate electrode is electrically connected with the gate material;
a collector electrode is arranged on the second surface of the semiconductor substrate and is electrically connected with the collector region;
the method comprises the following steps that 2 adjacent first grooves are used as a first groove group, and a preset number of second grooves are located at a preset position on one side of the first groove group;
the emitting regions and the first grooves are arranged in a one-to-one correspondence manner, and the emitting regions are positioned between 2 adjacent first grooves;
and in the preset number of second grooves, at least 1 dielectric material in the second groove is grounded.
2. The device of claim 1 wherein an opening size of the first trench is larger than an opening size of the second trench.
3. The device of claim 2, wherein the dielectric material is a material having a dielectric constant K less than or equal to 11.9.
4. The device of claim 2, wherein the dielectric material is silicon nitride, silicon oxynitride, or a material having a dielectric constant K less than or equal to 3.9.
5. The device of claim 1, wherein the predetermined number is at least 2.
6. The device according to claim 5, wherein a base region between 2 adjacent second trenches in the preset number of second trenches is used as a first base region, and at least 1 first base region is grounded.
7. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, a drift region of a first conduction type is arranged between the first surface and the second surface, a base region of a second conduction type is arranged between the drift region and the first surface, and a collector region of the second conduction type is arranged between the drift region and the second surface;
forming a plurality of first grooves and second grooves penetrating through the base region on the first surface of the semiconductor substrate, wherein 2 adjacent first grooves are a first groove group, and a preset number of second grooves are located at preset positions on one side of the first groove group;
forming a plurality of first-conductivity-type emitter regions corresponding to the first trenches in the first surface of the semiconductor substrate, wherein the emitter regions are arranged in one-to-one correspondence with the first trenches, the emitter regions are located between 2 adjacent first trenches, and the dielectric materials in at least 1 second trench in the preset number of second trenches are grounded;
filling a dielectric material in the second groove;
forming an isolation layer and a gate material in the first trench, wherein the isolation layer is located between the gate material and the semiconductor substrate, and the gate material is polysilicon;
forming a plurality of first conductive type emitter regions corresponding to the first grooves in the first surface of the semiconductor substrate, wherein the emitter regions are connected with the isolation layers of the first grooves;
forming an emitter electrode and a gate electrode on the first surface of the semiconductor substrate, wherein the emitter electrode is electrically connected with the emitter region, and the gate electrode is electrically connected with the gate material;
and forming a collector electrode on the second surface of the semiconductor substrate, wherein the collector electrode is electrically connected with the collector region.
8. The method of claim 7, wherein an opening size of the first trench is larger than an opening size of the second trench.
9. The method of claim 8, wherein filling the second trench with a dielectric material comprises:
depositing a dielectric material on the first surface of the semiconductor substrate until the second groove is completely filled with the dielectric material;
and etching the dielectric material on the first surface until the dielectric material in the first groove is completely removed.
10. The method of claim 7, further comprising:
the preset number is at least 2, and base regions between every two adjacent second trenches in the second trenches with the preset number are used as first base regions;
grounding at least 1 of the first base regions.
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| CN101048874A (en) * | 2004-10-29 | 2007-10-03 | 丰田自动车株式会社 | Iusulated gate semiconductor device and method for producing the same |
| CN103165604A (en) * | 2011-12-19 | 2013-06-19 | 英飞凌科技奥地利有限公司 | Semiconductor component with a space saving edge structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101048874A (en) * | 2004-10-29 | 2007-10-03 | 丰田自动车株式会社 | Iusulated gate semiconductor device and method for producing the same |
| CN103165604A (en) * | 2011-12-19 | 2013-06-19 | 英飞凌科技奥地利有限公司 | Semiconductor component with a space saving edge structure |
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