CN106783862B - A kind of STT-MRAM storage unit - Google Patents

Abstract

The invention discloses an STT-MRAM storage unit, comprising a transistor and an MTJ unit; the transistor is built on a substrate, and the drain of the transistor and the MTJ unit are in drain contact through a metal wire; the MTJ unit includes an inner electrode and a seed wrapped around the periphery of the inner electrode layer, ferromagnetic pinned layer, non-magnetic barrier layer, ferromagnetic free layer and external electrode; metal wire connected to internal electrode; seed layer, ferromagnetic pinned layer, non-magnetic barrier layer, ferromagnetic free layer and external electrode The electrodes are not parallel to the plane where the substrate is located; the seed layer, the ferromagnetic pinning layer, the non-magnetic barrier layer, the ferromagnetic free layer and the external electrodes are arranged at intervals from the metal wire. The arrangement form of the MTJ unit in the present invention weakens the relationship between the thermal stability coefficient Δ and the square change of the original plane structure size to a linear change, which can be compensated by height, which is beneficial to the miniaturization of the MTJ. The invention can effectively utilize space, ensure good thermal stability, improve storage density, provide multiple storage modes, and has application prospects for memories below the 20nm technology node.

Description

A kind of STT-MRAM storage unit

technical field

The invention relates to the technical field of STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory, spin transfer torque-magnetic random access memory) storage devices, in particular to a magnetic tunnel junction (Magnetic Tunnel Junction, MTJ) structure and preparation of the STT-MRAM device method.

Background technique

Magnetic random access memory (MRAM) is an advanced storage technology that can replace traditional memory. It has good non-volatility, that is, data is not lost after power failure, good thermal stability, storage information can be stored for more than ten years, and good read and write stability, the number of reads and writes can reach 10 ¹⁶ times. The early MRAM used a current to generate an external magnetic field to change the magnetic state of the free layer. Due to the large write current required and high energy consumption, miniaturization was limited. The spin-transfer torque magnetic random access memory (STT-MRAM), which controls the magnetic state through spin current, can effectively avoid this situation and is of great significance to the miniaturization of memory devices.

The read and write functions of STT-MRAM memory devices are controlled by their memory cells and spin-polarized currents. A typical STT-MRAM memory device consists of MTJ memory cells and selective transistors. The MTJ memory cell further includes a ferromagnetic pinned layer, an insulating tunneling layer, and a ferromagnetic free layer. With the advancement of semiconductor technology, the structure of the existing MTJ is a planar structure, that is, the planes of each layer of the MTJ are parallel to the surface of the wafer substrate, and the current flows in the direction perpendicular to the film surface. As nanotechnology nodes continue to be scaled down, the size of each part of the MTJ unit is decreasing, and its thermal stability is greatly challenged. The thermal stability of MTJ can be characterized by the formula Δ=KAt/kT. where Δ is the thermal stability factor, K is the anisotropy constant, A is the area of the magnetic free layer, t is the thickness of the free layer, k is the Boltzmann constant, and T is the temperature [A.V.Khvalkovskiy.J.Phys. D: Appl. Phys. 2013]. Generally, the storage unit is required to have thermal stability for storing information for more than 10 years, that is, the thermal stability factor Δ must be maintained at about 60-70. As the size of the device decreases, that is, the area A of the MTJ is decreasing, to maintain the value of thermal stability Δ, it needs to be maintained by increasing the anisotropy constant K or/and the thickness t of the film. According to the above thermal stability formula, when the device size decreases, the free layer area A will decrease with the square of the device size. At this time, in order to ensure thermal stability, Kt must increase with the square of the device size. On the one hand, the anisotropy constant K is usually determined by the interface process and material type of the magnetic thin film free layer and the oxide barrier layer, and it is difficult to adjust the anisotropy constant K in MTJ. It is technically very difficult to increase the compensation. On the other hand, increasing Δ by increasing the thickness t of the free layer is equally inefficient because Δ varies linearly with t much more slowly than the square of the MTJ dimension, and the switching current density is proportional to the film thickness t, increasing t makes The write energy rises sharply [A.Goyal.Appl.Phys.Lett.1996], so it is not feasible to compensate by adjusting t. Therefore, in order to maintain good thermal stability of the MTJ below the small-scale 10nm technology node, a new design of the MTJ structure is required.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an STT-MRAM storage unit to solve the above technical problems.

In order to achieve the above object, the present invention adopts the following technical solutions:

An STT-MRAM storage unit includes a transistor and an MTJ unit; the transistor is built on a substrate, and the drain of the transistor and the MTJ unit reach drain contact through a metal wire; the MTJ unit includes an inner electrode and a seed layer, an iron layer wrapped around the periphery of the inner electrode The magnetic pinned layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode; the metal wire is connected to the inner electrode; the seed layer, the ferromagnetic pinned layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode are all connected with the inner electrode. The plane on which the substrate is located is not parallel; the seed layer, the ferromagnetic pinning layer, the non-magnetic barrier layer, the ferromagnetic free layer and the external electrode are spaced apart from the metal wire.

Further, the MTJ unit is the inner electrode, the seed layer, the ferromagnetic pinning layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode in sequence from the inside to the outside, or the inner electrode, the seed layer, A ferromagnetic free layer, a nonmagnetic barrier layer, a ferromagnetic pinned layer, and an external electrode.

Further, the transistor includes a source electrode, a drain electrode and a gate stack; the source electrode and the drain electrode are arranged on the substrate at intervals, and the source electrode and the drain electrode are connected through the gate stack; the gate stack is connected to the first word line, The drain and the MTJ cell are in drain contact through metal lines.

Further, the MTJ unit has a cuboid columnar structure.

Further, the metal wire and the internal electrode have an integral structure, or the internal electrode is prepared on the metal wire.

Further, the MTJ unit is expressed from the inside to the outside as: the inner electrode of the cuboid column structure, the ferromagnetic pinning layer conformally surrounds the inner electrode along the side of the cuboid inner electrode, the non-magnetic barrier layer conformally surrounds the ferromagnetic pinning layer along the side, The ferromagnetic free layer conformally surrounds the non-magnetic barrier layer along the side, and the outer side of the ferromagnetic free layer is the outer electrode; or, the MTJ unit is expressed from the inside to the outside as: the inner electrode of the cuboid column structure, and the ferromagnetic free layer is along the side of the cuboid inner electrode. The inner electrode is conformally surrounded by the non-magnetic barrier layer, the ferromagnetic free layer is conformally surrounded by the non-magnetic barrier layer along the side, the ferromagnetic pinned layer is conformally surrounded by the non-magnetic barrier layer along the side, and the outer electrode is outside the ferromagnetic pinned layer.

Further, the upper part of the MTJ unit is a dielectric protection layer, the dielectric protection layer covers the seed layer, the ferromagnetic pinning layer, the non-magnetic barrier layer and the ferromagnetic free layer, and the external electrode is partially exposed outside the dielectric protection layer.

Further, the top dielectric protection layer of the MTJ is composed of one or more of Al ₂ O ₃ , CrO, and TaO, and its thickness is 0.5-2 nm.

Further, an insulating medium wrapping the transistor and the MTJ unit is provided on the substrate; the external electrode of the MTJ unit exposed to the outside of the dielectric protection layer is connected to the second word line.

Further, the seed layer, the ferromagnetic pinned layer, the non-magnetic barrier layer, the ferromagnetic free layer and the external electrode are all perpendicular to the plane where the substrate is located.

Further, the inner electrode of the MTJ structure has a length of 1-10 nm, a width of 1-10 nm and a height of 1-100 nm; the thickness of the seed layer is 0.5-3 nm; the thickness of the ferromagnetic pinning layer is 0.5-15 nm; the thickness of the barrier layer is 0.5-15 nm. is 0.5-5nm; the thickness of the free layer is 1-10nm; the thickness of the external electrode is 0.5-10nm.

Further, the material of the inner electrode is Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf, Ta, V, Cr, W, Nb, poly-Si and its alloys or semiconductor materials;

The material of the seed layer is NiFe, NiCr, NiFeCr, Cu, Ti, TiN, Ta, Ru or Rh;

The ferromagnetic pinning layer consists of an antiferromagnetic film and a ferromagnetic film, or a hard ferromagnetic film and a ferromagnetic film, or an antiferromagnetic, a coupling layer, and a It is composed of a layer of ferromagnetic film, or a hard ferromagnetic film, a coupling layer and a ferromagnetic film; the materials for preparing the antiferromagnetic film are IrMn, RhMn, RuMn, OsMn, FeMn, FeMnCr, FeMnRh, CrPtMn , TbMn, NiMn, PtMn, PtPdMn, NiO, CoNiO alloy and the multilayer film formed by the alloy containing the above-mentioned elements; the material for preparing the hard ferromagnetic film is Co, Fe, Pt, Pd and two or more of them. alloys, or CoPtB alloys; the materials for preparing ferromagnetic films are transition metals Fe, Co, Ni and their alloys, as well as with B, Zr, Pt, Pd, Hf, Ta, V, Zr, Ti, Cr, W, Mo , an alloy composed of Nb, and a multilayer film formed by the above elements or alloys;

The materials for preparing the ferromagnetic free layer are transition metals Fe, Co, Ni and their alloys, as well as alloys with B, Zr, Pt, Pd, Hf, Ta, V, Zr, Ti, Cr, W, Mo, Nb, And the multi-layer film formed by the above-mentioned elements or alloys;

The material of the non-magnetic barrier layer is MgO, Al ₂ O ₃ , Al ₂ MgO ₄ , ZnO, ZnMgO ₂ , TiO ₂ , HfO ₂ , TaO ₂ , Cd ₂ O ₃ , ZrO ₂ , Ga ₂ O ₃ , Sc ₂ O _3. V ₂ O ₅ , Fe ₂ O ₃ , Co ₂ O ₃ and NiO, and a mixture of one or more of the above compounds; or, the material of the non-magnetic barrier layer is nitride;

The external electrode materials are Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf, Ta, V, Cr, W, Nb, poly-Si and their alloys or semiconductor materials.

Compared with the prior art, the present invention has the following beneficial effects:

In the present invention, the MTJ unit is designed to be vertical or non-parallel to the substrate in the STT-MRAM memory cell, that is, each layer of the MTJ is vertical to the surface of the wafer substrate, and each layer is closed and is a rectangular parallelepiped in the shape of a back. Columnar structure, the length and width of the MTJ unit are respectively 5-50nm, and the height is between 1-100nm. In the structure provided by the present invention, as the size of the MTJ decreases, the thermal stability coefficient Δ=2LK(a+b)t/kT, where a, b and L are the length, width and height of the MTJ respectively, then Δ It will vary linearly with the length, width a, b of the plane dimension, and also linearly with the height. This MTJ structure can weaken the relationship between Δ and the square change of the original planar structure size to a linear change, which can be compensated by height, which is beneficial to the miniaturization of the MTJ unit structure. The well-established Self-Alignment Double Patterning (SADP) in the semiconductor industry today produces a rectangular structure [Zigang Xiao, IEEE, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013] , therefore, the square MTJ cell structure design in the present invention is easily realized by SADP technology.

The middle of the MTJ structure is a cuboid columnar inner electrode, which extends laterally from the inside to the outside along the side of the inner electrode to the periphery, followed by a ferromagnetic pinning layer, a non-magnetic barrier layer, a ferromagnetic free layer and an outer electrode; or iron Magnetic free layer, nonmagnetic barrier layer, ferromagnetic pinned layer and external electrodes. In this MTJ structure, the free electrons generate spin-polarized current from the inner electrode through the pinning layer in the lateral direction, and then pass through the barrier layer to reach the free layer, causing the magnetization direction of the free layer to turn to the electron spin polarization direction, achieving two magnetic The layer magnetic moment is in the parallel state, that is, the data "1". The free electrons are generated by the external electrode through the free layer in the lateral direction, and then pass through the barrier layer to reach the pinned layer. The electrons with the same polarization direction as the pinned layer pass through, and the opposite polarization is reflected back and then acts on the free layer to achieve two magnetic properties. The layer magnetic moment is in the antiparallel state, that is, the data "0".

The cuboid columnar inner electrode of the magnetic memory cell of STT-MRAM is formed on the bottom electrode, the cuboid columnar MTJ structure is prepared laterally along the side surface of the inner electrode, and then the outer electrode is prepared along the side surface. The content of the invention also includes the preparation method of the inner electrode. The cuboid columnar inner electrode is prepared on the metal wire, and then a layer of insulating medium is covered to expose the inner electrode part, and then the MTJ structure is prepared along the side of the exposed part. The lateral side of the electrode includes a seed layer, a pinned layer, a barrier layer and a free layer or a seed layer, a free layer, a barrier layer and a pinned layer from the inside to the outside, and an external electrode is prepared outside the MTJ.

The memory cell of the present invention exhibits a three-dimensional magnetic tunnel junction (MTJ) structure in the shape of a rectangular parallelepiped column, the length and width are respectively 5-50 nm, and the height is 1-100 nm; The layer (free layer), the barrier layer and the free layer (pinning layer) form a three-dimensional MTJ structure around the sides of the inner electrode. The advantage of this structure is that it can effectively use space, ensure good thermal stability, improve storage density, provide multiple storage modes, and have application prospects for memories below the 20nm technology node.

Description of drawings

The accompanying drawings are used to assist in describing the embodiments, for illustration only and not for limitation.

1 is a schematic side view of a three-dimensional STT-MRAM memory cell structure proposed in an embodiment of the present invention;

Figure 2 is a schematic diagram of MTJ200; wherein, Figure 2 (a) is a top view, Figure 2 (b) is a schematic cross-sectional view;

3 is a schematic diagram of the MTJ inner electrode proposed in the embodiment of the present invention; wherein, FIG. 3(a) is a top view, and FIG. 3(b) is a schematic cross-sectional view;

4-13 are schematic diagrams of the specific preparation process of the MTJ unit proposed in the embodiment of the present invention.

Figure 14 is a schematic diagram of the second form of MTJ200; wherein, Figure 14 (a) is a top view, Figure 14 (b) is a schematic cross-sectional view;

Figure 15 is a schematic structural diagram of the second form of MTJ200;

16-19 are schematic diagrams of a preparation method of the MTJ inner electrode proposed in the embodiment of the present invention;

20-22 are schematic diagrams of another preparation method of the MTJ inner electrode proposed in the embodiment of the present invention.

Detailed ways

Embodiment aspects of the invention are disclosed in the following description and related drawings directed to specific examples of the invention. Alternative embodiments are contemplated without departing from the scope of the present invention. In addition, well-known technical methods will not be described in detail to avoid confusion with the present invention. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any example described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the recited feature, advantage or mode of operation.

The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The invention describes a magnetic storage unit structure of a spin transfer torque memory STT-MRAM.

An STT-MRAM storage unit includes a magnetic tunnel junction MTJ structural unit (Magnetic Tunnel Junction), the MTJ unit includes a pinned layer, a potential barrier layer and a free layer, and its geometric structure is a rectangular columnar body. The writing and modification of information is achieved by changing the orientation of the magnetic moment of the free layer in the MTJ cell by a spin-polarized current. Changes in the magnetic moment cause changes in the resistance of the MTJ cells, and the difference in resistance states can be used to program or erase information in the memory cells.

Example 1

Figure 1 is a structural diagram of an STT-MRAM memory cell. A transistor 101 and MTJ cell 200 are included. Transistor 101 is built on substrate 100 and includes source 103a, drain 103b and gate stack 102. The gate stack 102 is connected to the word line 105 , the drain electrode 103 b is in drain contact with the MTJ cell 200 through the metal line 106 , and the source electrode 103 a is in source contact with the source node region 104 . The MTJ cell 200 is connected to the word line 107 . The MTJ unit 200 is formed by adding a tunnel layer between the pinned layer and the free layer, and is perpendicular to the upper plane of the metal line 106 .

Various technical descriptions related to this show that the fabrication of MTJ cells can be achieved by conformal deposition techniques such as atomic layer deposition (ALD) to fabricate MTJ cell structures. 1-2 disclose the detailed structure of the invention related to the magnetic recording element. The first part of the invention is the transistor 101 . The transistor 101 is fabricated on the substrate 100 and includes a source electrode 103 a , a drain electrode 103 b and a gate stack 102 . The gate stack 102 is connected to the word line 105 , the drain electrode 103 b is in drain contact with the magnetic recording unit 200 through the metal line 106 , and the source electrode 103 a is in source contact with the source node region 104 . The second part of the invention is the MTJ cell 200 located above and connected to transistor 101 via 106 . The metal wire 106 is connected to the inner electrode 204 , wherein the inner electrode 204 is perpendicular to the metal wire 106 , the inner electrode 204 is a rectangular parallelepiped column, and the bottom of the inner electrode 204 is buried in the 206 . The MTJ structure is prepared by the conformal deposition technology on the side of the leakage part of the inner electrode 204 . Outside the free layer is the outer electrode 205 . Above the MTJ unit 200 is a dielectric protection layer 207 . FIG. 2( a ) is a top view of the MTJ unit 200 .

In the MTJ unit in FIG. 2 , electrons are spin-polarized through the pinned layer 203 , and then pass through the barrier layer 202 to reach the free layer 201 , causing the direction of the magnetic moment of the free layer 201 to change. This process is Spin-transfer Torque Switching (STS), which can transfer information from the pinned layer 203 to the free layer 201 through a spin-polarized current. In this process, the pinned layer 203 acts as a spin filter, the spin-filtered electrons tunnel through the barrier layer 202, and then the spin electrons act on the magnetic moment of the free layer 201, so that the state of the MTJ changes from anti-parallel "1" becomes parallel "0". Conversely, by reversing the current, the state of the MTJ can be changed from a parallel "0" to an anti-parallel "1". Using the transistor 101 as a selection device again, the binary storage information can be written or changed on the STT-MRAM chip by controlling the current.

FIG. 3 is a schematic diagram of the preparation of the MTJ inner electrode proposed in the embodiment of the present invention. First, a layer of metal electrodes is prepared by magnetron sputtering or atomic layer deposition (ALD), and its thickness is about 10-50 nm. The metal layer is then etched according to Figure 3(a) using ion beam etching or electron beam etching. During the etching, the metal layer is not completely etched to obtain an inverted T-shaped electrode as shown in FIG. 3(b). Finally, another insulating layer is plated, and the unetched part of the bottom is buried under the insulating layer. The exposed cuboid columnar metal is the inner electrode 204 .

4-12 are the specific preparation process of the MTJ unit proposed in the embodiment of the present invention. A seed layer 212 is prepared on the prepared inner electrode, and a layer of seed layer is prepared by magnetron sputtering or atomic layer deposition (ALD) as shown in FIG. 4 . The desired seed layer 212 is obtained by ion beam etching or electron beam etching as shown in FIG. 5 . After that, magnetron sputtering or atomic layer deposition (ALD) and ion beam etching or electron beam etching are repeatedly used to prepare the ferromagnetic pinning layer 201 , the insulating barrier layer 202 and the free layer 203 .

Example 2

FIG. 14 is a structural diagram of another three-dimensional STT-MRAM memory cell. A transistor 101 and MTJ cell 200 are included. The transistor structure is the same as that of Embodiment 1. Partial adjustments were made at the MTJ unit 200: the corresponding structure of the MTJ was changed from inside to outside to inner electrode, free layer, barrier layer, pinned layer, and outer electrode. The materials and preparation methods used for each layer structure are similar to those in Example 1. The specific structure of its MTJ is shown in Figure 15.

Two methods of making the inner electrode 204 of the MTJ 200.

In the first preparation method, the inner electrode 204 is directly prepared on the 106 by ion beam etching or electron beam etching, as shown in FIGS. 16 and 17 . Then, magnetron sputtering or atomic layer deposition (ALD) is used to prepare a layer of insulating medium 206 on the basis of FIG. 17 to obtain the structure of FIG. 18 . The insulating medium around 204 is removed by ion beam etching or electron beam etching, as shown in FIG. 19 , and then the device is prepared through the process of preparing the MTJ in Examples 1 and 2.

In the second preparation method, a layer of insulating medium 206 is firstly covered on 106 by magnetron sputtering or atomic layer deposition (ALD), as shown in FIG. 20 . A cuboid-shaped groove is etched on the insulating medium 206 by using ion beam etching or electron beam etching technology, and the depth reaches 106 . Then, magnetron sputtering or atomic layer deposition (ALD) is used to fill the groove with the material for preparing the inner electrode 204, as shown in FIG. 21 . The insulating medium around the inner electrode 204 is etched into the structure shown in FIG. 22 by using ion beam etching or electron beam etching technology to obtain the desired electrode. Devices were then prepared through the procedures for preparing MTJs in Examples 1 and 2.

Claims (2)

1. a preparation method of STT-MRAM storage unit is characterized in that, described STT-MRAM storage unit comprises transistor (101) and MTJ unit (200); The transistor (101) is built on the substrate (100), and the drain (103b) of the transistor (101) is in drain contact with the MTJ unit (200) through a metal wire (106); the transistor (101) includes a source (103a), a drain The electrode (103b) and the gate stack (102); the source (103a) and the drain (103b) are arranged on the substrate (100) at intervals, and the source (103a) and the drain (103b) pass through the gate stack ( 102) connection; the gate stack (102) is connected to the first word line (105), and the drain (103b) is in drain contact with the MTJ cell (200) through the metal line (106); The MTJ unit (200) is, from inside to outside, an inner electrode (204), a seed layer (212) wrapped around the outer periphery of the inner electrode (204), a ferromagnetic pinning layer (203), a nonmagnetic barrier layer (202), a ferromagnetic free layer (201) and an external electrode (205), wherein the ferromagnetic pinned layer (203) and the ferromagnetic free layer (201) can exchange order; The seed layer (212), the ferromagnetic pinned layer (203), the non-magnetic barrier layer (202), the ferromagnetic free layer (201) and the external electrode (205) are not parallel to the plane of the substrate (100); the seed layer (212), a ferromagnetic pinning layer (203), a non-magnetic barrier layer (202), a ferromagnetic free layer (201), and an external electrode (205) and a metal wire (106) spaced apart; The MTJ unit (200) is located above the transistor (101) and is connected to the transistor (101) through a metal wire (106); the metal wire (106) is connected to an internal electrode (204), wherein the internal electrode (204) is perpendicular to the metal wire (106) ) and the inner electrode (204) is in the shape of a rectangular parallelepiped column; MTJ cells are prepared on the side of the leakage part of the inner electrode (204) by a conformal deposition technique; The inner electrode of the MTJ structure is 1-10nm long, 1-10nm wide and 1-100nm high; the thickness of the seed layer is 0.5-3nm; the thickness of the ferromagnetic pinning layer is 0.5-15nm; the thickness of the barrier layer is 0.5- 5nm; the thickness of the free layer is 1-10nm; the thickness of the external electrode is 0.5-10nm; The preparation method comprises the following steps: The preparation process of the MTJ unit (200): a layer of seed layer is prepared on the prepared internal electrode, and then the desired seed layer (212) is obtained by etching; after that, the atomic layer deposition technology and ion beam etching or electron beam are repeatedly used Etching to prepare a ferromagnetic pinned layer, a non-magnetic barrier layer (202) and a ferromagnetic free layer; The preparation method of the inner electrode (204) includes: firstly covering a layer of insulating medium (206) on the metal wire (106) by using atomic layer deposition technology; using ion beam etching or electron beam etching technology on the insulating medium (206) A groove in the shape of a cuboid is etched, and the depth reaches the metal line (106); then the material for preparing the internal electrode (204) is filled in the groove by the atomic layer deposition technology; then the insulation around the internal electrode (204) is Dielectric etching to obtain the inner electrode (204); or, firstly, a layer of metal electrode is prepared by using atomic layer deposition technology; then the metal electrode is etched, and during the etching, the metal electrode is not completely etched to obtain an inverted T-shaped electrode ; Finally, another layer of insulating layer is plated, and the unetched part of the bottom is buried under the insulating layer; the exposed cuboid columnar metal is the inner electrode (204); The MTJ unit is expressed from the inside to the outside as: the inner electrode of the cuboid column structure, the ferromagnetic pinning layer conformally surrounds the inner electrode along the side of the cuboid inner electrode, the non-magnetic barrier layer conformally surrounds the ferromagnetic pinning layer along the side, and the ferromagnetic free The layer conformally surrounds the non-magnetic barrier layer along the side, and the outer side of the ferromagnetic free layer is the outer electrode; or, the MTJ unit is expressed from the inside to the outside as: the inner electrode of the cuboid column structure, and the ferromagnetic free layer conforms to the side of the cuboid inner electrode. In the inner electrode, the non-magnetic barrier layer conformally surrounds the ferromagnetic free layer along the side, the ferromagnetic pinning layer conformally surrounds the non-magnetic barrier layer along the side, and the outside of the ferromagnetic pinned layer is the outer electrode; The upper part of the MTJ unit is a dielectric protection layer (207), and the dielectric protection layer (207) covers the seed layer (212), the ferromagnetic pinning layer (203), the nonmagnetic barrier layer (202) and the ferromagnetic free layer (201) ), the outer electrode (205) is partially exposed outside the dielectric protection layer (207); The substrate (100) is provided with an insulating medium wrapping the transistor (101) and the MTJ unit (200); the MTJ unit (200) is exposed to the external electrode (205) and the second word line (107) outside the dielectric protection layer (207) ) connected; The seed layer (212), the ferromagnetic pinned layer (203), the non-magnetic barrier layer (202), the ferromagnetic free layer (201) and the external electrode (205) are all perpendicular to the plane of the substrate (100). 2. the preparation method of a kind of STT-MRAM memory cell according to claim 1 is characterized in that, the material of inner electrode is Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf , Ta, V, Cr, W, Nb and their alloys, or semiconductor materials; The material of the seed layer is NiFe, NiCr, NiFeCr, Cu, Ti, TiN, Ta, Ru or Rh; The ferromagnetic pinning layer consists of an antiferromagnetic film and a ferromagnetic film, or a hard ferromagnetic film and a ferromagnetic film, or an antiferromagnetic, a coupling layer, and a layer of ferromagnetic film, or a layer of hard ferromagnetic film, a layer of coupling layer and a layer of ferromagnetic film; The antiferromagnetic film is a single-layer film or a multi-layer film, and the material of each film is IrMn, RhMn, RuMn, OsMn, FeMn, FeMnCr, FeMnRh, CrPtMn, TbMn, NiMn, PtMn, PtPdMn, NiO or CoNiO; The material for preparing the hard ferromagnetic thin film is Co, Fe, Pt, Pd and an alloy formed by two or more of them, or a CoPtB alloy; The ferromagnetic film is a single-layer film or a multi-layer film, and the material of each film is transition metal Fe, Co, Ni and its alloys, or Fe, Co, Ni and B, Zr, Pt, Pd, Hf, Ta, V, Alloys composed of Zr, Ti, Cr, W, Mo, Nb; The ferromagnetic free layer is a single-layer film or a multi-layer film, and the material of each film is transition metal Fe, Co, Ni and their alloys, or Fe, Co, Ni and B, Zr, Pt, Pd, Hf, Ta, V , alloys composed of Zr, Ti, Cr, W, Mo, Nb; The material of the non-magnetic barrier layer is MgO, Al ₂ O ₃ , Al ₂ MgO ₄ , ZnO, ZnMgO ₂ , TiO ₂ , HfO ₂ , TaO ₂ , Cd ₂ O ₃ , ZrO ₂ , Ga ₂ O ₃ , Sc ₂ O _3. V ₂ O ₅ , Fe ₂ O ₃ , Co ₂ O ₃ and NiO, and a mixture of one or more of the above compounds; or, the material of the non-magnetic barrier layer is nitride; The external electrode materials are Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf, Ta, V, Cr, W, Nb and their alloys, or semiconductor materials.

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