CN106783622A - High pressure low heat budget K post growth annealings high - Google Patents

Abstract

A kind of method of insertion SiGe during there is provided manufacture PMOS device.Multilayer can be formed has the SiGe layer of different Ge contents, to cause to increase to (crowd) intermediate layer Ge contents from (crowd) bottom, and reduces from (crowd) intermediate layer to (crowd) top layer Ge contents.In certain embodiments, the embedded SiGe has the SiGe transition zones on the SiGe Seed Layers of substrate, the SiGe Seed Layers, the SiGe intermediate layers on a SiGe transition zones and the 2nd SiGe transition zones on the SiGe intermediate layers.First SiGe transition zones can have the Ge contents of the top increase from the bottom of a SiGe transition zones toward a SiGe transition zones.2nd SiGe transition zones can have the Ge contents that the top from the bottom of the 2nd SiGe transition zones toward the 2nd SiGe transition zones reduces.

Description

High pressure low heat budget high K post annealing process

technical field

The present invention relates to semiconductor technology and devices.

Background technique

Since the early days when Dr. Jack Kilby of Texas Instruments invented the integrated circuit, scientists and engineers have made numerous inventions and improvements in semiconductor devices and processes. Over the past 50 years, there has been a significant reduction in the size of semiconductors, which translates into ever-increasing processing speeds and ever-decreasing power consumption. So far, the development of semiconductors has roughly followed Moore's Law, which roughly states that the number of transistors in a dense integrated circuit doubles about every two years. Now, the semiconductor process is developing below 20nm, and some companies are working on the 14nm process. Here is just a reference, a silicon atom is about 0.2nm, which means that the distance between two independent components manufactured by a 20nm process is only about a hundred silicon atoms.

Semiconductor device fabrication is thus becoming increasingly challenging and pushed towards the limits of what is physically possible. Huali Microelectronics Co., ^LtdTM is one of the leading semiconductor manufacturing companies dedicated to the research and development of semiconductor devices and processes.

Conventional device structures based on silicon germanium (SiGe) technology have been developed to produce field effect transistors (FETs). For example, SiGe technology for p-channel metal oxide semiconductor (PMOS) transistors has been developed by depositing a buried pseudomorphic strained SiGe layer capped with an unstrained silicon (Si) layer. Portions of the silicon cap are oxidized to form a gate dielectric. Due to the shift in the valence band, holes can be confined to the SiGe channel. In this design, dislocations in the SiGe film can be avoided if the SiGe film thickness is made very thin. The fabrication of this device is compatible with state-of-the-art complementary metal-oxide-semiconductor (CMOS) processing.

Contents of the invention

A brief summary of one or more aspects is presented below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all contemplated aspects and is intended to neither identify key or critical elements of all aspects nor attempt to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

According to an aspect of the present invention, there is provided a method for forming a p-channel metal-oxide-semiconductor (PMOS) device, the method comprising: forming a substrate comprising a silicon material; etching the substrate to form a cavity and depositing silicon germanium in the cavity to form a SiGe seed layer above the surface of the substrate, a first SiGe transition layer above the SiGe seed layer, a SiGe intermediate layer above the first SiGe transition layer, and A second SiGe transition layer above the SiGe intermediate layer, wherein the first SiGe transition layer has a germanium Ge content that increases from the bottom of the first SiGe transition layer to the top of the first SiGe transition layer, wherein the first SiGe transition layer the Ge content of the bottom of the SiGe transition layer is the same as or higher than the Ge content of the SiGe seed layer; the SiGe intermediate layer has the same or higher Ge content than the Ge content of the top of the first SiGe transition layer; and the second The second SiGe transition layer has a Ge content that decreases from the bottom of the second SiGe transition layer to the top of the second SiGe transition layer, wherein the Ge content of the bottom of the second SiGe transition layer is the same as the Ge content of the SiGe intermediate layer or lower.

According to another aspect of the present invention, there is provided a p-channel metal oxide semiconductor (PMOS) device comprising: a substrate comprising a silicon material; an HKMG gate stack formed over the substrate; and embedded SiGe regions on opposite sides of the HKMG gate stack, each SiGe region comprising a SiGe seed layer over the surface of the substrate, a first SiGe transition layer over the SiGe seed layer , the SiGe interlayer on the first SiGe transition layer, and the second SiGe transition layer on the SiGe interlayer, wherein the first SiGe transition layer has a Ge content of germanium Ge content increased at the top of the transition layer, wherein the Ge content of the bottom of the first SiGe transition layer is the same as or higher than the Ge content in the SiGe seed layer; the SiGe intermediate layer has the same the Ge content at the top is the same or higher; and the second SiGe transition layer has a Ge content that decreases from the bottom of the second SiGe transition layer to the top of the second SiGe transition layer, wherein the second SiGe transition layer The Ge content at the bottom of SiGe is the same as or lower than that in the SiGe interlayer.

Description of drawings

FIG. 1A illustrates that an embedded SiGe process according to the present disclosure may include depositing a hard mask over the entire substrate.

FIG. 1B illustrates that an embedded SiGe process according to the present disclosure may include forming a sigma-shaped cavity on each side of the PMOS after the hard mask formation.

FIG. 1C illustrates that an embedded SiGe process according to the present disclosure can grow a SiGe seed layer 114 in the cavity after cavity formation.

FIG. 1D illustrates the formation of a first transitional SiGe layer in a process that may follow the formation of the SiGe seed layer.

FIG. 1E illustrates that an embedded SiGe process according to the present disclosure can grow a SiGe interlayer after the formation of the first SiGe transition layer.

1F illustrates that a second transitional SiGe layer may be formed after the formation of the SiGe interlayer in an embedded SiGe process according to the present disclosure.

FIG. 1G illustrates that a capping layer may be formed over the second SiGe transition layer in an embedded SiGe process according to the present disclosure.

A further understanding of the nature and advantages of various embodiments may be realized with reference to the following figures. In the figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference number by a dash and a sublabel to distinguish among similar components. If only a first reference number is used in the description, the description applies to any one of similar components having the same first reference number regardless of the sub-reference number.

detailed description

The present disclosure relates to the fabrication of high-k/metal gate (HKMG) stacks for semiconductors, and more particularly to reducing the diffusion of _O2 into the IL after formation of the HKMG stack.

The following description is given to enable a person skilled in the art to make and use the invention and incorporate it into a specific application context. Various modifications, and various uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not limited to the embodiments given herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present invention. It will be apparent, however, to one skilled in the art that the practice of the present invention need not be limited to these specific details. In other words, well-known structures and devices are shown in block diagram form and not in detail in order to avoid obscuring the invention.

Readers are invited to pay attention to all documents and documents submitted simultaneously with this specification and open to public inspection of this specification, and the contents of all such documents and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is only one example of an equivalent or similar set of features.

Moreover, any component in a claim that does not expressly state a means for performing a specified function, or a step for performing a specified function, shall not be construed as a means or step clause as defined in paragraph 6 of Section 112 of 35 USC. In particular, the use of "the step of ..." or "the act of ..." in the claims herein does not imply reference to the provisions of paragraph 6 of Chapter 112 of 35USC.

Note that where used, the symbols left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used for convenience only and do not imply any specific fixed direction. In fact, they are used to reflect the relative position and/or orientation between various parts of the object.

In an embedded SiGe process for fabricating PMOS devices, cavities are typically formed in the source/drain regions of the PMOS devices. Formation of the cavity is typically achieved by a multi-step dry etch process followed by a wet etch process. The first dry etch step is the first anisotropic dry etch to etch through the deposited hard mask layer (e.g., silicon nitride) to initiate the etch of the cavity in the substrate (e.g., silicon) , followed by an isotropic dry lateral etch (dry lateral etch) to expand (including laterally towards the MOS transistor channel) the cavity, followed by a second anisotropic dry etch to define the bottom wall of the cavity.

1A-1G illustrate the process flow of incorporating embedded SiGe in PMOS according to the present disclosure. As shown in FIG. 1A , the process may include depositing a hard mask 104 over the entire substrate 102 . In various implementations, hardmask 104 may be formed of SiN to a thickness depending on the application of the device comprising PMOS 100 . As shown, a hard mask 104 may be deposited over a work function metal 108 , such as titanium nitride (TiN), which may be provided over a high-k dielectric layer 110 on a substrate 102 . As will be appreciated by those skilled in the art, the structure shown in FIG. 1 is a gate-first HKMG stack, which may generally include spacers 106a and 106b as shown in FIG. 1 . The substrate 102 can be, for example, a silicon material commonly used in the semiconductor industry, such as relatively pure silicon and silicon mixed with other elements such as germanium and carbon. Alternatively, the semiconductor material may be germanium, gallium arsenide, or the like. The semiconductor material may be provided as a bulk semiconductor substrate, or may be provided on a silicon-on-insulator (SOI) substrate comprising a support substrate, an insulator layer on the support substrate, and a silicon-on-insulator layer. material layer. Additionally, the substrate 102 may be silicon-on-insulator (SOI). In some examples, substrate 102 may include a doped epitaxial (epi) layer. In other examples, the substrate 102 may include a multilayer compound semiconductor structure.

In various embodiments, the substrate 102 may include various doped regions (eg, p-type well or n-type well) depending on design requirements. These doped regions may be doped with p-type dopants, such as boron or BF2, and/or n-type dopants, such as phosphorus or arsenic. These doped regions can be directly formed on the substrate 102 in a P-well structure, in an N-well structure, in a double-well structure, or using a raised structure. The semiconductor substrate 102 may also include various active regions, such as regions configured for N-type metal-oxide-semiconductor transistor devices (referred to as NMOS) and regions configured for P-type metal-oxide-semiconductor transistor devices (referred to as PMOS). Area. For example, substrate 102 may have doped regions and epitaxial layers formed to define source and drain regions.

FIG. 1B illustrates that an embedded SiGe process according to the present disclosure may include forming Σ-shaped cavities 112a - b on each side of the PMOS 100 after the hardmask 100 is formed. In some implementations, cavities 112a - b may be formed by wet etching with tetramethylammonium hydroxide (TMAH) in substrate 102 on each side of the PMOS 100 gate stack. Although other shapes are possible, the Σ-shaped cavity allows for very close proximity and thus maximum stress inside the transistor channel region. Wet etchants used for crystal etching are crystallographically selective to the substrate material, such as etchants comprising TMAH, which can be used to etch the substrate from the U-shaped recesses provided by the multi-step dry etch process. During the wet crystal etching process, the etch rate of the <111> crystal orientation is lower than that of other crystal orientations such as <100>. As a result, the U-shaped recess becomes a diamond-shaped recess.

As shown, after forming the cavities 112a-b, SiGe 113 may be grown in the cavities 112a-b. In some implementations, SiGe 113 is grown in cavities 112 a - b , eg, by a low pressure chemical vapor deposition (LPCVD) process as an in-situ graded boron doped deposition for deep source/drain regions of PMOS 100 . In-situ doping can be used to obtain high and uniform doping levels, which in turn reduces parasitic and contact resistances, thereby allowing higher drive currents. Also, by doping the source/drain regions of the PMOS during epitaxy, dedicated source/drain implants can be eliminated, thereby saving process costs for masks and implants, reducing cycle time, and reducing Stress relief from injection damage. Furthermore, the boron dopant is activated by epitaxy, thus no additional anneal is required. The slight overgrowth may contribute to a more robust package and a margin for subsequent cleaning processes that encroach on active open silicon areas. The overgrowth also provides additional margin for forming a robust salicide, such as nickel silicide (NiSi), with better contact resistance.

During the embedded SiGe process according to the present disclosure, the concentration of Ge in the SiGe 114 grown in the cavities 112a-b can be controlled to increase the compressive stress in the channel region of the PMOS device to improve device performance. However, it has been observed that as the concentration of Ge between the substrate 102 and the SiGe layer increases, the lattice mismatch between the two layers also increases. This can cause interface misalignment between the substrate and the SiGe layer, and thus degrade PMOS device performance.

In addition, due to the above-mentioned orientation selectivity of SiGe epitaxial growth (SiGe on <100> grows fastest, SiGe on <110> grows second fastest, and SiGe on <111> grows slowest), when the SRAM region When the SiGe epitaxial layer is higher than the substrate plane, <111> crystal planes will be formed on both sides of the epitaxial layer. However, the <111> crystal planes can negatively affect subsequent cap layer growth such that the SiGe cap layer in the SRAM region may not grow uniformly (e.g., the cap layer may not grow sufficiently crystalline on <111> to have sufficient thickness, or do not grow at all). Also, SiGe regions with high germanium content on the epitaxial layer may not react or react insufficiently with metallic nickel to form NiSi or NiGeSi. This can lead to poor contact between subsequent CTs and SiGe layers leading to leakage, increased resistance, increased resistance control difficulty, and/or any other problems.

In order to solve the above-mentioned problems, the embedded SiGe process according to the present disclosure proposes a new approach, under which the Ge content in the source and drain regions of the embedded SiGe can be increased. Under this new approach, the dislocation between the substrate and the embedded SiGe can be eliminated or reduced. In addition, under this new approach, the above-mentioned cap layer content can also be improved to help the growth of NiSi.

According to an aspect of the present disclosure, when embedding SiGe in the cavities 112a-b, multiple SiGe layers with different Ge contents can be formed such that the Ge content increases from the bottom layer(s) towards the middle layer(s), and The Ge content decreases from the middle(s) layer to the top(s) layer. In some embodiments, one or more seed layers of SiGe may first be grown on the bottom and sidewalls of the cavities 112a-b. One or more layers of germanium can then be grown on the SiGe seed layer(s) to form one or more first SiGe transition layers. The first SiGe transition layer(s) may have a Ge content that increases from the bottom of the first SiGe transition layer(s) to the top of the first SiGe transition layer(s). Also in these embodiments, one or more SiGe intermediate layers having a high Ge content may be formed over the first SiGe transition layer(s). The SiGe interlayer(s) may have a Ge content equal to or higher than the highest Ge content in the first SiGe transition layer. Finally, in these embodiments, one or more second transitional SiGe layers may be grown over the SiGe interlayer(s). The second SiGe transition layer(s) may have a Ge content that decreases from the bottom of the transition layers to the top of the transition layers. Finally, a capping layer may be formed over the second SiGe transition layer(s).

Additional aspects and other features of the disclosure will be set forth in the specification that follows, and in part will become apparent to those of ordinary skill in the art upon analysis of the following disclosure, or may be learned by practice of the disclosure. The advantages of the disclosure may be realized and obtained as particularly pointed out in the appended claims.

1C-F illustrate the stepwise growth of embedded SiGe in an embedded SiGe process according to the present disclosure. They will be described with reference to Figures 1A-1B. FIG. 1C illustrates that the process can grow a SiGe seed layer 114 in the cavities 112a-b after the cavities 112a-b are formed, and the Ge content in the SiGe seed layer 114 can be between 1%-28%. In some implementations, the thickness of the SiGe seed layer 114 may be between 100-300 Angstroms. FIG. 1D illustrates that the first transitional SiGe layer 116 may be formed in a process subsequent to the formation of the SiGe seed layer 114 . The content of Ge in the first SiGe transition layer 116 may be between 20% and 50%. As shown, the Ge content in the first SiGe transition layer 116 may gradually increase from the bottom 116b of the first SiGe transition layer to the top 116a of the first SiGe transition layer. For example, near the bottom 116b, the Ge content may be about 30%, while near the top 116a, the Ge content may be about 50%. In some implementations, the Ge content of the first transition layer 116 at the bottom 116 b may be the same or substantially similar to the Ge content of the SiGe seed layer 114 . For example, SiGe seed layer 114 and bottom 116b may both have a Ge content of about 20%. In some implementations, the thickness of the first SiGe transition layer 116 may be between 30-500 Angstroms.

FIG. 1E illustrates that the process can grow the SiGe interlayer 118 after the first SiGe transition layer 116 is formed. The Ge content in the SiGe interlayer 118 may be between 30%-50%. The Ge content in the SiGe interlayer 118 may be the same or substantially similar to the Ge content in the top 116 a of the first SiGe transition layer 116 . For example, near the top 116a, the first SiGe transition layer may have 40% Ge, and the SiGe intermediate layer 118 may also have a Ge content of about 40%. In some implementations, the SiGe interlayer 118 may have a thickness between 100-800 Angstroms. In some implementations, the top of the SiGe interlayer 118 may be deposited in the cavities 112a - b level or substantially level with the surface of the substrate 102 . However, this is not restrictive. In some other implementations, the top of the SiGe interlayer 118 may be deposited in the cavities 112a - b below or above the surface of the substrate 102 .

FIG. 1F illustrates that a second transitional SiGe layer 120 may be formed after the SiGe interlayer 118 is formed in this process. The content of Ge in the second SiGe transition layer 120 may be between 0% and 50%. As shown, the Ge content in the second SiGe transition layer 120 may gradually decrease from the bottom 120b of the second SiGe transition layer to the top 120a of the second SiGe transition layer. For example, near the bottom 120b, the Ge content may be about 50%, while near the top 120a, the Ge content may be about 0%. In some implementations, the Ge content of the second transition layer 120 at the bottom 120 b may be the same or substantially similar to the Ge content of the SiGe interlayer 118 . For example, SiGe interlayer 118 may have a Ge content of 50%. In some implementations, the thickness of the second SiGe transition layer may be between 100-300 Angstroms.

In some implementations, embedded SiGe as shown in Figures 1C-1F can be grown by any suitable process, implantation chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure CVD (LPCVD), or art Any other process known to be suitable for growing embedded SiGe. Gases that can be used to grow embedded SiGe as shown in Figures 1C _- 1F can include _SiH4 , _SiH2Cl2 , HCL, _H2 , _GeH4 , _{B2H6 ,} and/or any other gas. When using H ₂ , the flow rate of H ₂ can be controlled between 1000 sccm and 60000 sccm, and the flow rate of gaseous gas can be controlled between 0.1 sccm and 1200 sccm. When using GeH ₄ , and SiH ₄ or SiH ₂ Cl ₂ , the flow ratio of GeH ₄ , SiH ₄ or SiH ₂ Cl ₂ can be controlled from 1:0.01 to 1:100. When GeH ₄ and HCl are used, their flow ratio can be controlled from 1:0.05 to 1:50. In various embodiments, the reaction temperature can be controlled at 500-1000° C., and the pressure of the reaction chamber can be controlled at 1-800 Torr.

FIG. 1G illustrates that a capping layer 122 may be formed over the second SiGe transition layer 120 . The thickness of the capping layer 122 can be controlled between 10 and 300 angstroms. The content of the capping layer may contain Ge in some embodiments, or may not contain Ge in some other embodiments. In some implementations, each or more of layers 116 , 118 , 120 , and 122 may include a SiGe in-situ doping of B at a concentration of less than 2×10 ²¹ cm ⁻³ .

As explained throughout various parts of this application, embodiments of the present invention may provide a number of advantages over prior art technologies and approaches. It should be appreciated that embodiments of the present invention are compatible with existing systems and processes. For example, forming cavities described in accordance with embodiments of the present invention may be fabricated using existing equipment. The molding cavity according to the embodiments of the present invention can be easily used to manufacture various types of devices such as CMOS, PMOS, NMOS, and the like.

While the above is a full description of specific embodiments, various modifications, alternative constructions, and equivalents may also be used. In addition to the above, other embodiments exist. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention as defined by the appended claims.

Claims (19)

1. A method for forming a p-channel metal oxide semiconductor (PMOS) device, the method comprising: forming a substrate comprising a silicon material; etching the substrate to form a cavity; and Depositing silicon germanium in the chamber to form a SiGe seed layer over the surface of the substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe interlayer over the first SiGe transition layer , and the second SiGe transition layer above the SiGe intermediate layer, wherein The first SiGe transition layer has a germanium-Ge content increasing from the bottom of the first SiGe transition layer to the top of the first SiGe transition layer, wherein the Ge content of the bottom of the first SiGe transition layer is the same as the The Ge content in the SiGe seed layer is the same or higher; the SiGe intermediate layer has a Ge content equal to or higher than that of the top of the first SiGe transition layer; and The second SiGe transition layer has a Ge content that decreases from the bottom of the second SiGe transition layer to the top of the second SiGe transition layer, wherein the Ge content of the bottom of the second SiGe transition layer is the same as that of the SiGe transition layer. The Ge content in the intermediate layer is the same or lower. 2. The method according to claim 1, wherein the percentage of Ge content in the first SiGe transition layer is between 20% and 50%. 3. The method according to claim 1, characterized in that the percentage of Ge content in the SiGe intermediate layer is between 30% and 50%. 4. The method of claim 1, wherein the percentage of Ge content in the second SiGe transition layer is between 0% and 50%. 5. The method of claim 1, wherein the Ge content at the top of the second SiGe transition layer is zero. 6. The method of claim 1, further comprising forming a capping layer over the second SiGe transition layer. 7. The method of claim 1, wherein the first SiGe transition layer is characterized as having a thickness between 30 angstroms and 500 angstroms. 8. The method of claim 1, wherein the SiGe interlayer is characterized as having a thickness between 100 angstroms and 800 angstroms. 9. The method of claim 1, wherein the second SiGe transition layer is characterized as having a thickness between 100 angstroms and 300 angstroms. 10. The method of claim 1, wherein a top of the SiGe interlayer is level or substantially level with the surface of the substrate. 11. A p-channel metal oxide semiconductor (PMOS) device comprising: a substrate comprising a silicon material; an HKMG gate stack formed over the substrate; and embedded silicon germanium regions on opposite sides of the HKMG gate stack, each of the silicon germanium regions comprising a SiGe seed layer over the surface of the substrate, a first SiGe seed layer over the SiGe seed layer a SiGe transition layer, a SiGe intermediate layer on the first SiGe transition layer, and a second SiGe transition layer on the SiGe intermediate layer, wherein The first SiGe transition layer has a germanium-Ge content increasing from the bottom of the first SiGe transition layer to the top of the first SiGe transition layer, wherein the Ge content of the bottom of the first SiGe transition layer is the same as the The Ge content in the SiGe seed layer is the same or higher; the SiGe intermediate layer has a Ge content equal to or higher than that of the top of the first SiGe transition layer; and The second SiGe transition layer has a Ge content that decreases from the bottom of the second SiGe transition layer to the top of the second SiGe transition layer, wherein the Ge content of the bottom of the second SiGe transition layer is the same as that of the SiGe transition layer. The Ge content in the intermediate layer is the same or lower. 12. The PMOS device according to claim 11, characterized in that the percentage of Ge content in the first SiGe transition layer is between 20% and 50%. 13. The PMOS device according to claim 11, characterized in that the percentage of Ge content in the SiGe intermediate layer is between 30% and 50%. 14. The PMOS device according to claim 11, wherein the percentage of Ge content in the second SiGe transition layer is between 0% and 50%. 15. The PMOS device according to claim 11, wherein the Ge content at the top of the second SiGe transition layer is zero. 16. The PMOS device of claim 11, wherein the first SiGe transition layer is characterized by a thickness between 30 angstroms and 500 angstroms. 17. The PMOS device of claim 11, wherein the SiGe interlayer is characterized by a thickness between 100 angstroms and 800 angstroms. 18. The PMOS device of claim 11, wherein the second SiGe transition layer is characterized by a thickness between 100 angstroms and 300 angstroms. 19. The PMOS device according to claim 11, wherein the top of the SiGe interlayer is flat or substantially flat with the surface of the substrate.