CN106776188A - Bus failure injected system based on DSP and FPGA - Google Patents

Abstract

The invention discloses a bus fault injection system based on DSP and FPGA, comprising DSP main processor, FPGA, upper computer, Ethernet interface module, DA module, RS422 interface module, RS485 interface module, relay network, resistance network and storage module; through serial connection in the bus system to configure the required failure mode, the RS422/RS485 interface module is used to receive the serial signal on the bus, which is converted into a parallel signal by the FPGA, and after DSP processing, the DA module and the The relay network outputs the signal after the injected fault. The invention adopts hardware fault injection, which can realize the fault injection function of physical layer, electrical layer and protocol layer, more realistically simulate the faults of hardware in the actual operation process, and add various faults in real time in the normal communication of bus equipment.

Description

Bus Fault Injection System Based on DSP and FPGA

technical field

The invention relates to fault injection technology, in particular to a bus fault injection system based on DSP and FPGA.

Background technique

In recent years, RS-422 and RS-485 buses have been widely used because of their high real-time and high flexibility, but in practical applications, to ensure the high reliability of the bus system, bus testing is essential.

Most of the existing test methods adopt the forward test mode to test the output response to the input stimulus; even if some existing test methods adopt fault injection, they only perform fault simulation at the physical level and protocol level. Inject short circuit, open circuit, series/parallel impedance, signal replacement, signal delay and other digital part faults, and the fault injection coverage of the analog part of the signal is not comprehensive, and the actual bus operation will face various states and environmental changes .

Contents of the invention

The purpose of the present invention is to provide a bus fault injection system based on DSP and FPGA, capable of simulating the faults of hardware during actual operation during bus communication.

The technical solution that realizes the object of the present invention is: a kind of bus fault injection system based on DSP and FPGA, comprises DSP main processor, FPGA, upper computer, Ethernet interface module, DA module, RS422 interface module, RS485 interface module, relay networks, resistor networks and memory modules;

Described RS422 interface module and RS485 interface module are arranged between serial port bus and FPGA, are used for receiving the data on the serial port bus, and send to FPGA;

The FPGA is connected to the DSP main processor through a data bus and an address bus, and sends the received data to the DSP main processor;

The DSP main processor is connected with the upper computer through the Ethernet interface module, receives the fault instruction sent by the upper computer, carries out fault injection to the received data according to the corresponding fault instruction, and generates the data after the fault injection;

The FPGA is connected to the device end through a DA module, and the DA module is used to convert the data after the fault injection into an analog output;

The relay network and the resistance network are arranged between the DA module and the equipment end, and the disconnection and connection of the relay are controlled by the FPGA, and the resistance network is used to simulate serial impedance or parallel impedance.

Compared with the prior art, the present invention has the following significant advantages: 1) the present invention performs all fault injection units connected in series in the bus system under the premise of not changing the signals of the test equipment and the equipment under test that provide the excitation source. Need the disposition of fault, change the communication signal, realize the function that adds various faults in the normal communication of bus equipment; 2) The present invention adopts the hardware fault injection method, the signal after the fault injection is output by the analog quantity, simulates the hardware in the actual running process 3) The present invention can set the serial receiving baud rate through the upper computer man-machine interaction interface according to the agreed baud rate in application, and can be directly used as a module flexibly in different baud rate communication systems, It has very strong flexibility; 4) the present invention has a good visual interface, can transmit fault injection commands through Ethernet communication, and can inject faults in real time; 5) the present invention directly controls each module through FPGA, which reduces system cost, It simplifies the circuit design and has high cost performance.

Description of drawings

Fig. 1 is the overall structural diagram of the bus fault injection system based on DSP and FPGA of the present invention.

Fig. 2 is a hardware structural diagram of the bus fault injection system based on DSP and FPGA of the present invention.

Fig. 3 is a schematic diagram of the RS422 interface module of the bus fault injection system based on DSP and FPGA in the present invention.

Fig. 4 is a schematic diagram of the relay output of the bus fault injection system based on DSP and FPGA of the present invention.

Fig. 5 is a schematic diagram of relays and resistor networks of the bus fault injection system based on DSP and FPGA of the present invention.

Fig. 6 is a schematic diagram of the DA module of the bus fault injection system based on DSP and FPGA in the present invention.

Fig. 7 is a flow chart of the upper and lower computers of the bus fault injection system based on DSP and FPGA in the present invention.

detailed description

In conjunction with Fig. 1 and Fig. 2, a kind of bus fault injection system based on DSP and FPGA of the present invention includes DSP main processor, FPGA, upper computer, Ethernet interface module, DA module, RS422 interface module, RS485 interface module, relay networks, resistor networks and memory modules;

Described RS422 interface module and RS485 interface module are arranged between serial port bus and FPGA, are used for receiving the data on the serial port bus, and send to FPGA;

The FPGA is connected to the DSP main processor through a data bus and an address bus, and sends the received data to the DSP main processor;

The DSP main processor is connected with the host computer through the Ethernet interface module, receives the fault command sent by the host computer, performs fault injection to the received data according to the corresponding fault command, and generates data after the fault injection;

The FPGA is connected to the device end through a DA module, and the DA module is used to convert the data after the fault injection into an analog output;

The relay network and the resistance network are arranged between the DA module and the equipment end, and the disconnection and connection of the relay are controlled by the FPGA, and the resistance network is used to simulate serial impedance or parallel impedance.

Further, the Ethernet interface module adopts W5300 chip, and the DSP embedded processor adopts ADSP-BF532 chip.

Furthermore, both the RS422 interface module and the RS485 interface module include a 65LBC184 interface chip and an optocoupler chip 6N137, the 65LBC184 interface chip is used for RS422 level and TTL level conversion, and the optocoupler chip 6N137 is used for signal isolation from the FPGA.

Further, the DA module includes a 4-channel AD5544 conversion chip and an OP2177 operational amplifier, the 4-channel AD5544 conversion chip is used for digital-to-analog conversion, and the OP2177 operational amplifier is used for voltage amplitude adjustment and common-mode voltage adjustment.

Furthermore, the relay network is driven by the TPIC6B595 chip to achieve parallel output; the on-off of the relay is controlled by the FPGA to realize the fault injection of short circuit, open circuit, and series/parallel impedance at the physical level.

Furthermore, the FPGA directly controls the RS422/RS485 module, DA module, and relay network to realize the reception of RS422/RS485 serial signals, and converts them into parallel signals for DSP processing; Serial data conversion clock, chip select signal of TPIC6B595 and serial output data, realize parallel output through TPIC6B595 chip; FPGA adopts four-wire serial mode to control DA module, output serial data clock, chip select signal of AD5544, serial output data and serial data load signals.

The present invention configures the required faults by serially connecting them in the bus. The RS422/RS485 interface module receives the signals on the bus. After DSP processing, the FPGA controls the DA module to output the signal after the fault is injected, and realizes that the bus equipment is normal. Various faults are added to the communication in real time.

In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be described in detail with reference to the accompanying drawings and embodiments.

Example

As shown in Figure 1, the bus fault injection system based on DSP and FPGA, under the premise of not changing the signal of the test equipment and the device under test that provide the excitation source, implements the required fault injection unit through the fault injection unit connected to the bus system. The configuration of the mode changes the communication signal and realizes the function of adding various faults in real time during the normal communication of the bus device.

As shown in Figure 2 and Figure 7, the bus fault injection system based on DSP and FPGA includes two parts: the upper computer and the lower computer. Send the fault command to the lower computer. After the lower computer is powered on, first initialize the DSP, FPGA, W5300, etc., then set the serial signal receiving baud rate according to the actual communication baud rate, wait for the fault injection command of the upper computer, and after receiving the fault command, pass the control DA according to the fault requirements. The module, the relay network, outputs the signal after fault injection.

As shown in Figure 2, a RS422/RS485 bus fault injection system based on DSP and FPGA, including DSP main processor, FPGA coprocessor, host computer, Ethernet interface module, DA module, RS422 interface module, RS485 interface module , relay network and resistor network. The DSP main processor is connected with the upper computer through the Ethernet interface module, receives the fault command sent by the upper computer, and connects with FPGA through data bus and address bus; Between the buses; RS422 interface module, RS485 interface module and FPGA are connected through level conversion chip LVC4245A to realize 5V and 3.3V level conversion; relay network, resistor network and DA module are connected to FPGA, and the output is controlled by FPGA.

Combined with Figure 2, Figure 3 and Figure 6, the RS422/RS485 interface module uses the 65LBC184 interface chip to complete the RS422 level and TTL conversion, and realizes the signal isolation from the FPGA through the optocoupler chip 6N137; the DA module uses the 4-channel AD5544 conversion chip , to complete the digital-to-analog conversion, select the OP2177 operational amplifier, and complete the voltage amplitude adjustment and common-mode voltage adjustment, so as to realize the fault injection at the electrical level; the relay network is driven by the TPIC6B595 chip to achieve parallel output, and the on-off of the relay is controlled by the FPGA to realize the physical Layered short circuit, open circuit, series/parallel impedance fault injection.

Combined with Figure 2-Figure 4, the software design of the RS422/RS485 module inside the FPGA includes a serial baud rate generating unit, a serial receiving unit and a serial sending unit to realize the function of the serial transceiver module and receive the serial signal baud rate, According to the baud rate of the actual received signal, it can be set by the man-machine interface of the upper computer, and realized by dividing the frequency of the clock signal. The serial receiving unit is connected in series with multi-level D flip-flops to convert the received input serial data stream into parallel data for subsequent processing; the internal output module of the FPGA uses a three-wire serial mode to control the output state and output serial data Convert the clock, TPIC6B595 chip select signal and serial output data, and drive the relay through the TPIC6B595 chip to output in parallel; through the FPGA to control the on-off of different relays, you can connect resistors between different parts of the line, so as to realize RS422/RS485 bus short circuit, open circuit, Fault injection at the physical level such as series/parallel impedance.

Combined with Figure 2 and Figure 5, the DA module inside the FPGA uses a four-wire serial method to control the DA module, output serial data clock, chip select signal of AD5544, serial output data and serial data loading signal, and control the two channels of AD5544 Different voltage values are output as differential signal pairs, and the voltage value can be set flexibly, so as to realize fault injection at the electrical level such as RS422/RS485 bus voltage amplitude adjustment, common mode voltage adjustment, and input voltage threshold adjustment. At the same time, through FPGA, store the received data into its FIFO module to realize delay failure; replace the received data with different data, such as flipping the first data bit, and then output it by DA to realize data replacement; or change the output of DA module The rate realizes the adjustment of the transmission rate and performs fault injection at the protocol level.

Claims (5)

1. A bus fault injection system based on DSP and FPGA, characterized in that: comprise DSP main processor, FPGA, upper computer, Ethernet interface module, DA module, RS422 interface module, RS485 interface module, relay network, resistance network and memory modules; Described RS422 interface module and RS485 interface module are arranged between serial port bus and FPGA, are used for receiving the data on the serial port bus, and send to FPGA; The FPGA is connected to the DSP main processor through a data bus and an address bus, and sends the received data to the DSP main processor; The DSP main processor is connected with the upper computer through the Ethernet interface module, receives the fault instruction sent by the upper computer, carries out fault injection to the received data according to the corresponding fault instruction, and generates the data after the fault injection; The FPGA is connected to the device end through a DA module, and the DA module is used to convert the data after the fault injection into an analog output; The relay network and the resistance network are arranged between the DA module and the equipment end, and the disconnection and connection of the relay are controlled by the FPGA, and the resistance network is used to simulate serial impedance or parallel impedance. 2. the bus fault injection system based on DSP and FPGA according to claim 1, is characterized in that, Ethernet interface module adopts W5300 chip, and DSP embedded processor is ADSP-BF532 chip. 3. the bus fault injection system based on DSP and FPGA according to claim 1, is characterized in that, RS422 interface module, RS485 interface module all comprise 65LBC184 interface chip and optocoupler chip 6N137, 65LBC184 interface chip is used for RS422 level and TTL Level conversion, optocoupler chip 6N137 is used for signal isolation from FPGA. 4. the bus fault injection system based on DSP and FPGA according to claim 1, it is characterized in that, DA module comprises AD5544 conversion chip and OP2177 operational amplifier of 4 channels, the AD5544 conversion chip of 4 channels is used for digital-to-analog conversion, OP2177 Operational amplifiers are used for voltage amplitude regulation, common-mode voltage regulation. 5. the RS422/RS485 bus fault injection system based on DSP and FPGA according to claim 1, is characterized in that, relay network is driven relay by TPIC6B595 chip, realizes parallel output; By the on-off of FPGA control relay, realizes physical level Fault injection for short circuit, open circuit, series/parallel impedance.