CN106774027A - A kind of power network data intelligence processing system - Google Patents
A kind of power network data intelligence processing system Download PDFInfo
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- CN106774027A CN106774027A CN201710121423.2A CN201710121423A CN106774027A CN 106774027 A CN106774027 A CN 106774027A CN 201710121423 A CN201710121423 A CN 201710121423A CN 106774027 A CN106774027 A CN 106774027A
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- 238000000034 method Methods 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000005070 sampling Methods 0.000 claims description 9
- 238000013500 data storage Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
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- 238000006243 chemical reaction Methods 0.000 claims description 3
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- 238000004891 communication Methods 0.000 abstract description 4
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- 230000006870 function Effects 0.000 description 8
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
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Abstract
The invention discloses a kind of power network data intelligence processing system, including detail programming unit, JTAG modules, dsp controller, FPGA module and crystal oscillator and reset circuit, detail programming unit sets software by JTAG modules to dsp controller, after system electrification, dsp controller, FPGA module are respectively by respective FLASH loading procedures.The present invention coordinates dsp controller, the making space on the one hand reducing pcb board and the reliability for substantially increasing system using one piece of ultra-large field programmable gate array；On the other hand, being combined with DSP by FPGA carries out operation control, improves the transmission speed and processing speed of data, and then ensure that the real-time of system；Interface module is increased, whole system can carry out modularized production, applied widely；By USB controller complete with the communication of PC, with hot plug, easy to use, transmission rate is high the features such as；Increased radio function simultaneously；Whole system constitute rationally, implementation method it is simple, with practical value.
Description
Technical field
The present invention relates to a kind of data handling system, specifically a kind of power network data intelligence processing system.
Background technology
In Electric Grid Data Processing System, it is often necessary to high speed signal is acquired and treatment.For example, in light sensing skill
To the measurement of light pulse scattered signal in art, to measurement of electromagnetic pulse signal etc. in radar engineering, it is required for believing high speed
Number be acquired and computing, and such high speed signal measurement, often data Collection ＆ Processing System is proposed it is strict will
Ask.In existing Electric Grid Data Processing System, it is substantially list data are processed using dsp controller or single-chip microcomputer,
By itself hardware of DSP or single-chip microcomputer is limited, processing speed is limited；Additionally there are the problem of narrow application range, one
Individual Electric Grid Data Processing System may be only available for an occasion, to another occasion, need to re-start design again.
The content of the invention
It is an object of the invention to provide a kind of power network data intelligence processing system, to solve to be proposed in above-mentioned background technology
Problem.
To achieve the above object, the present invention provides following technical scheme：
A kind of power network data intelligence processing system, including detail programming unit, JTAG modules, dsp controller, FPGA module
With crystal oscillator and reset circuit, detail programming unit sets software by JTAG modules to dsp controller, after system electrification, DSP controls
, respectively by respective FLASH loading procedures, system brings into operation for device processed, FPGA module, and signal is input into from signal input part, through putting
Big circuit completes A/D conversions after amplifying in A/D modules, and 0 is interrupted to dsp controller transmission from FPGA module applies for signal, DSP controls
Device processed reads data from A/D FIFO RAM modules, and carries out Wavelet denoising, treatment terminate rear dsp controller to
USB controller is sent and interrupts application signal, and USB controller is shown the data is activation after treatment to PC by PC application program
Registration evidence；The dsp controller is also respectively connected with interface module and wireless module chip, and wireless module chip is also connected with channel radio
Letter antenna；The amplifying circuit includes resistance R1, electric capacity C1, triode VT1, diode D1 and triode VT2, the resistance R1
One end connects resistance R2, input signal Vi and triode VT1 base stages respectively, and the resistance R1 other ends connect electric capacity C1 and electric capacity respectively
C5, electric capacity the C5 other end connect resistance R5, diode D1 positive poles and electric capacity C6 respectively, and the electric capacity C6 other ends connect output end respectively
Vo, triode VT2 emitter stages and triode VT3 emitter stages, triode VT3 colelctor electrodes connect electric capacity C2, resistance R3 and electricity respectively
The resistance R2 other ends are simultaneously grounded, and the electric capacity C2 other ends connect the resistance R3 other ends and triode VT1 emitter stages, triode VT1 respectively
Colelctor electrode connects diode D1 negative poles, electric capacity C4 and triode VT3 base stages respectively, and it is another that the electric capacity C4 other ends connect resistance R5 respectively
One end, resistance R4 and triode VT2 base stages, triode VT2 colelctor electrodes connect resistance R6 and power supply VCC respectively, and resistance R6 is another
End connects the resistance R4 other ends and the electric capacity C1 other ends respectively.
As further scheme of the invention：The PC application program can also be controlled to the system, specifically
Including：The data after USB controller treatment are received, the data of USB controller before processing are received, the sampling of A/D modules is set frequently
Rate and sampling number.
As further scheme of the invention：The dsp controller is also connected with data storage.
As further scheme of the invention：The dsp controller is also connected with crystal oscillator and reset circuit.
As further scheme of the invention：Pass through two USB FIFO between the dsp controller and USB controller
RAM module exchange data.
As further scheme of the invention：The dsp controller uses TMS320VC33.
As further scheme of the invention：The FPGA module uses XC3090.
As further scheme of the invention：The USB controller uses AN2136SC.
As further scheme of the invention：The interface module include digital interface, A/D interfaces, 485 interfaces and
HART interfaces.
Compared with prior art, the beneficial effects of the invention are as follows：The present invention is patrolled using one piece of ultra-large field-programmable
Collect gate array and coordinate dsp controller, the making space on the one hand reducing pcb board and the reliability for substantially increasing system
Property；On the other hand, being combined with DSP by FPGA carries out operation control, improves the transmission speed and processing speed of data, and then
Ensure that the real-time of system；Interface module is increased, whole system can carry out modularized production, applied widely；By
USB controller complete with the communication of PC, with hot plug, easy to use, transmission rate is high the features such as；Increased simultaneously wireless
Function；Whole system constitute rationally, implementation method it is simple, with practical value.
Brief description of the drawings
Fig. 1 is the structural representation of power network data intelligence processing system.
Fig. 2 is the program flow diagram of dsp controller in power network data intelligence processing system.
Fig. 3 is the circuit diagram of amplifying circuit in power network data intelligence processing system.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Fig. 1~3 are referred to, in the embodiment of the present invention, a kind of power network data intelligence processing system, including detail programming list
Unit, JTAG modules, dsp controller, FPGA module and crystal oscillator and reset circuit, detail programming unit is by JTAG modules to DSP
Controller sets software, and after system electrification, respectively by respective FLASH loading procedures, system is opened for dsp controller, FPGA module
Begin operation, signal is input into from signal input part, and amplified circuit completes A/D conversions after amplifying in A/D modules, from FPGA module to
Dsp controller sends and interrupts 0 application signal, and dsp controller reads data from A/D FIFO RAM modules, and carries out small echo change
Denoising is changed, treatment terminates rear dsp controller and sends interruption application signal to USB controller, and USB controller is by after treatment
Data is activation to PC, by PC application program display data；The dsp controller is also respectively connected with interface module and wireless mould
Block chip, wireless module chip is also connected with radio antenna.The PC application program can also be controlled to the system
System, specifically includes：The data after USB controller treatment are received, the data of USB controller before processing are received, setting A/D modules
Sample frequency and sampling number.The dsp controller is also connected with data storage.The dsp controller is also connected with crystal oscillator and answers
Position circuit.
Fig. 3 is the circuit diagram of amplifying circuit of the invention, including resistance R1, electric capacity C1, triode VT1, diode D1 and
Triode VT2, described resistance R1 one end connects resistance R2, input signal Vi and triode VT1 base stages, the resistance R1 other ends respectively
Electric capacity C1 and electric capacity C5 is connected respectively, and the electric capacity C5 other ends connect resistance R5, diode D1 positive poles and electric capacity C6, electric capacity C6 respectively
The other end connects output end vo, triode VT2 emitter stages and triode VT3 emitter stages respectively, and triode VT3 colelctor electrodes connect respectively
Connect electric capacity C2, resistance R3 and the resistance R2 other ends and be grounded, the electric capacity C2 other ends connect the resistance R3 other ends and triode respectively
VT1 emitter stages, triode VT1 colelctor electrodes connect diode D1 negative poles, electric capacity C4 and triode VT3 base stages respectively, and electric capacity C4 is another
One end connects the resistance R5 other ends, resistance R4 and triode VT2 base stages respectively, and triode VT2 colelctor electrodes connect resistance R6 respectively
With power supply VCC, the resistance R6 other ends connect the resistance R4 other ends and the electric capacity C1 other ends respectively；Letters of the input signal Vi from Fig. 1
The input of number input, output end vo connection A/D modules.
(1) when input signal Vi is direct current signal, after power supply VCC is connected, triode VT1, VT2 and VT3 are not same
When turn on, power supply VCC turns on VT2 through R6, R4 for VT2 provides base current first, after VT2 conductings, its emitter stage
Electric current turns on VT1 through R1 for VT1 provides base current all the way, and after VT1 conductings, the base current of VT3 could be by VT1's
C-E poles, R3 are turned on to ground, so that VT3 is turned on, the direct current signal that output end vo output is amplified.
(2) when input signal Vi is AC signal, AC signal is sent to VT1 base stages, is exported from colelctor electrode after amplification, by
In colelctor electrode and base stage be inverted relationship, so signal and the base signal opposite polarity of the output of VT1 colelctor electrodes, when the positive half cycles of Vi
After signal amplifies through VT1, negative half-cycle signal is changed into from colelctor electrode output, the signal declines A points voltage, after D1 and R5, B points
Voltage also declines, VT2 cut-offs, and A points voltage declines can make VT3 conductings deep, into normal magnifying state, there is the electric current of amplification
From output end vo output；The negative half-cycle signal flow of Vi is similar with above-mentioned flow, so, when the positive-negative half-cycle signal of Vi adds electricity
Lu Shi, VT2 and VT3 alternation, the signal for having complete amplification are exported from output end vo.
The dsp controller that the system is used is the TMS320VC33 of TI (Texas Instrument) company, and it is that TI companies release
32 high floating point number signal processing chips of cost performance, be current Floating-point DSP the most widely used at home and abroad it
One.
TMS320VC33 has the characteristics that：Harvard structure；Pile line operation；Special hardware multiplier；Special DSP
Instruction；The quick instruction cycle.In addition, TMS320VC33 also has powerful floating-point operation ability, arithmetic speed is reachable
150MFLOPS (million floating point operations per second), disposal ability reaches 75MIPS (per second million instruction cycles).And, it
Lower power consumption to 200mW is also made using 3.3V I/O voltages and 1.8V processor core voltages.
The circuit design of dsp controller is mainly the periphery circuit design for TMS320VC33.The STRB0 of TMS320VC33
Connect the piece choosing of data storage respectively with pin and enable pin, realize the extension of data storage, TMS320VC33's
INT2 pins are connected to low level, program bootstrap loading after electricity in realization；By the TMS of TMS320VC33, TDI, TDO, TCK, EMU0,
The pins such as EMU1 composition download program mouthful, to facilitate the program debugging of dsp controller.
Present system carries interface module, and interface module connects including digital interface, A/D interfaces, 485 interfaces and HART
Mouthful, the present invention is possessed very strong versatility by these interfaces, these are corresponding much to need data to be processed to only need to access
Interface in, you can processed accordingly, and corresponding result exported in PC.
Because the logic of the system is more complicated, in order to efficiently reduce the volume of hardware, improve the reliability of hardware system
Property, the address decoding circuitry of all of logic control circuit, various memories can all be compiled with one piece of ultra-large scene here
Journey logic gate array (FPGA) XC3090 is realized.Logic control circuit includes：Command register, sampling number/sample frequency
Setting register, control circuit, the USB and its FIFO and A/ for interrupting application signal generator, A/D results being write FIFO RAM
D fifo status detect circuit.
By two USB FIFO RAM module exchange datas between TMS320VC33 and USB controller AN2136SC, hold
Hand signal uses PC mouthfuls of AN2136SC, and when USB is to receive buffer, dsp controller is read, and AN2136SC writes；When USB is hair
During sending buffer, dsp controller is write, and AN2136SC reads.PC is used as the read/write channel of the two, and direction is programmable to be determined；PC
Apply interrupting to AN2136SC for TMS320VC33；PC is used for AN2136SC resets USB and receives buffer；PC is used for
USB receiver full scale will, forbids AN2136SC further to receive buffer to USB if receiver has been expired and writes；PC is used for
The empty mark of USB transmission buffers, forbids AN2136SC further to be read to USB transmission buffers if buffer sky.
Data after TMS320VC33 treatment can also be sent to outer by wireless module chip and radio antenna
The wireless terminal in portion, realizes radio function.
Systems soft ware mainly includes that five is most of：DSP programs are (total for A/D controlling of sampling, data processing, DSP and USB
Information between line is exchanged), usb bus driver, USB firmware programs are (for the data exchange between PC and DSP and place
Reason), PC application program, program is realized to the translator of address and each register in FPGA.
DSP programs are initialized to dsp controller first (interrupts initialization, the outer gating signal initialization of piece, setting system
Sampling number/the sample frequency etc. for acquiescence of uniting), it is then etc. to be interrupted (to interrupt the reading that 0 program is mainly used in A/D data
And treatment, and to the data after PC transmission processe；The program of interruption 1 is mainly used in analyzing the order of PC, for PC
Sampling number/the sample frequency of order initialization system, and send the data of PC needs), as shown in Figure 2.
USB firmware program codes are processed by reinforced 8051 single-chip microcomputer of USB integrated chips.When EZ-USB equipment is connected to
During USB port, main frame carries out bus enumeration, firmware is downloaded into chip internal using system program according to device id first, then
Re-enumeration is carried out, firmware starts to perform as the function device of user.The firmware program framework that CYPRESS companies provide, is used for
Complete controlling transmission work and the work of most data transfer.The firmware program of this interface circuit is namely based on this firmware frame
Exploitation, and be compiled using Keil C.
In order to realize the communication with driver, application program creates an event and a line to PC application program first
Journey, then passes to WDM by event handler, and the event message of WDM transmissions is waited with thread, after receiving event message, attends school
Take the data of driver, display data.
In WINDOWS, the api function of Win32 application calls has five：CreateFile()、ReadFile
(), WriteFile (), DeviceIoControl () and CloseHandle ().
Application program uses CreateFile () function to open a WDM device driver.Its first parameter
It is a symbolic link name.If creating a WDM driver with DriverWorks, it will usually use class KUnitizedName
One device symbols link name of generation.There are a numeral, usually one 0 behind this name.If for example, symbolic link name
It is L " USBDevice " that then pass to CreateFile () is " .USBDevice0 ".
Once application program obtains effective handle of equipment, it can just call Win32 functions, and this will produce and corresponds to this
The corresponding IRP of device object, is sent to driver, completes corresponding function.
In sum, the present invention coordinates dsp controller, a side using one piece of ultra-large field programmable gate array
Face reduces the making space of pcb board and substantially increases the reliability of system；On the other hand, joined by FPGA and DSP
Conjunction carries out operation control, improves the transmission speed and processing speed of data, and then ensure that the real-time of system；Increased and connect
Mouth mold block, whole system can carry out modularized production, applied widely；Communication with PC, tool are completed by USB controller
Have hot plug, the features such as easy to use, transmission rate is high；Increased radio function simultaneously；Whole system constitutes reasonable, realization side
Method is simple, with practical value.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be in other specific forms realized.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit requires to be limited rather than described above, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as the claim involved by limitation.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each implementation method is only wrapped
Containing an independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art should
Specification an as entirety, the technical scheme in each embodiment can also be formed into those skilled in the art through appropriately combined
May be appreciated other embodiment.
Claims (8)
1. a kind of power network data intelligence processing system, including detail programming unit, JTAG modules, dsp controller, FPGA module and
Crystal oscillator and reset circuit, it is characterised in that detail programming unit sets software by JTAG modules to dsp controller, in system
After electricity, respectively by respective FLASH loading procedures, system brings into operation for dsp controller, FPGA module, and signal is from signal input
End input, amplified circuit completes A/D conversions after amplifying in A/D modules, is sent to dsp controller from FPGA module and interrupts 0 Shen
Please signal, dsp controller reads data from A/D FIFO RAM modules, and carries out Wavelet denoising, and treatment terminates
Afterwards dsp controller to USB controller send interrupt application signal, USB controller by the data is activation after treatment to PC, by PC
Machine application program display data；The dsp controller is also respectively connected with interface module and wireless module chip, wireless module chip
It is also connected with radio antenna；The amplifying circuit includes resistance R1, electric capacity C1, triode VT1, diode D1 and triode
VT2, described resistance R1 one end connects resistance R2, input signal Vi and triode VT1 base stages respectively, and the resistance R1 other ends connect respectively
Electric capacity C1 and electric capacity C5 is met, the electric capacity C5 other ends connect resistance R5, diode D1 positive poles and electric capacity C6, the electric capacity C6 other ends respectively
Output end vo, triode VT2 emitter stages and triode VT3 emitter stages are connected respectively, and triode VT3 colelctor electrodes connect electric capacity respectively
C2, resistance R3 and the resistance R2 other ends are simultaneously grounded, and the electric capacity C2 other ends connect the resistance R3 other ends and triode VT1 transmittings respectively
Pole, triode VT1 colelctor electrodes connect diode D1 negative poles, electric capacity C4 and triode VT3 base stages, electric capacity C4 other ends difference respectively
The connection resistance R5 other ends, resistance R4 and triode VT2 base stages, triode VT2 colelctor electrodes connect resistance R6 and power supply respectively
VCC, resistance the R6 other end connect the resistance R4 other ends and the electric capacity C1 other ends respectively, and the built-in program of dsp controller is right first
Dsp controller is initialized, and then etc. to be interrupted, the PC application program can also be controlled to the system, tool
Body includes：The data after USB controller treatment are received, the data of USB controller before processing are received, the sampling of A/D modules is set
Frequency and sampling number.
2. power network data intelligence processing system according to claim 1, it is characterised in that the dsp controller is also connected with
Data storage.
3. power network data intelligence processing system according to claim 1, it is characterised in that the dsp controller is also connected with
Crystal oscillator and reset circuit.
4. power network data intelligence processing system according to claim 1, it is characterised in that the dsp controller is controlled with USB
Pass through two USB FIFO RAM module exchange datas between device processed.
5. power network data intelligence processing system according to claim 1, it is characterised in that the dsp controller is used
TMS320VC33。
6. power network data intelligence processing system according to claim 1, it is characterised in that the FPGA module is used
XC3090。
7. power network data intelligence processing system according to claim 1, it is characterised in that the USB controller is used
AN2136SC。
8. power network data intelligence processing system according to claim 1, it is characterised in that the interface module includes numeral
Interface, A/D interfaces, 485 interfaces and HART interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710121423.2A CN106774027A (en) | 2017-03-02 | 2017-03-02 | A kind of power network data intelligence processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710121423.2A CN106774027A (en) | 2017-03-02 | 2017-03-02 | A kind of power network data intelligence processing system |
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| Publication Number | Publication Date |
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| CN106774027A true CN106774027A (en) | 2017-05-31 |
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ID=58959614
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| Application Number | Title | Priority Date | Filing Date |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109902955A (en) * | 2019-02-27 | 2019-06-18 | 苏州浪潮智能科技有限公司 | A kind of the electric network data monitoring processing system and method for the flexibly configurable based on FPGA |
| CN112596818A (en) * | 2020-12-30 | 2021-04-02 | 上海众源网络有限公司 | Application program control method, system and device |
-
2017
- 2017-03-02 CN CN201710121423.2A patent/CN106774027A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109902955A (en) * | 2019-02-27 | 2019-06-18 | 苏州浪潮智能科技有限公司 | A kind of the electric network data monitoring processing system and method for the flexibly configurable based on FPGA |
| CN112596818A (en) * | 2020-12-30 | 2021-04-02 | 上海众源网络有限公司 | Application program control method, system and device |
| CN112596818B (en) * | 2020-12-30 | 2023-12-05 | 上海众源网络有限公司 | Application program control method, system and device |
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