CN106712524B - Full-bridge converter circuit and liquid crystal display device - Google Patents
Full-bridge converter circuit and liquid crystal display device Download PDFInfo
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- CN106712524B CN106712524B CN201710090941.2A CN201710090941A CN106712524B CN 106712524 B CN106712524 B CN 106712524B CN 201710090941 A CN201710090941 A CN 201710090941A CN 106712524 B CN106712524 B CN 106712524B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a full-bridge converter circuit, which comprises a full-bridge converter unit, a first delay gating unit, a second delay gating unit and a controller, wherein the full-bridge converter unit comprises a first electric switch, a second electric switch, a third electric switch, a fourth electric switch, a transformer and a rectifier, the first electric switch, the fourth electric switch, the second electric switch and the third electric switch are respectively a diagonal switch, the first electric switch, the second electric switch, the third electric switch and the fourth electric switch are respectively connected between a voltage input end and the ground in series, a first end and a second end of a primary coil of the transformer are respectively connected to a node between the first electric switch and the second electric switch and a node between the third electric switch and the fourth electric switch, a first end and a fourth end of the controller are respectively connected to the first electric switch and the third electric switch through the first delay gating unit and the second delay gating unit, the controller controls the two diagonal switches to be sequentially conducted, the first electric switch and the third electric switch are conducted when, the conversion efficiency of the full-bridge converter circuit is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a full-bridge converter circuit and liquid crystal display equipment.
Background
The full-bridge inverter is the type with the highest power output, so the loss of the power switch of the full-bridge inverter becomes a particular concern. In a normal full-bridge converter, the diagonal power switches are operated simultaneously. This causes the primary winding input of the transformer in the full-bridge converter to no longer be a low impedance loop, resulting in noise caused by the leakage inductance of the transformer and the excitation inductance of the full-bridge converter. This noise can currently only be reduced by lossy absorption networks. But this reduces the output efficiency of the full bridge converter.
Disclosure of Invention
The invention aims to provide a full-bridge converter circuit to improve the output efficiency of the full-bridge converter.
Another object of the present invention is to provide a liquid crystal display device.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
the invention provides a full-bridge converter circuit, which comprises a full-bridge converter unit, a first time-delay gating unit, a second time-delay gating unit and a controller, wherein the full-bridge converter unit comprises a first electric switch, a second electric switch, a third electric switch, a fourth electric switch, a transformer and a rectifier, the first electric switch and the fourth electric switch are first diagonal switches, the second electric switch and the third electric switch are second diagonal switches, the first electric switch and the second electric switch are connected in series between a voltage input end and ground, the third electric switch and the fourth electric switch are connected in series between the voltage input end and the ground, a first end of a primary coil of the transformer is connected to a node between the first electric switch and the second electric switch, and a second end of the primary coil of the transformer is connected to a node between the third electric switch and the fourth electric switch, the two ends of the secondary coil of the transformer are connected to the two input ends of the rectifier, the two output ends of the rectifier are used as voltage output ends, the first end of the controller is connected to the second electric switch, the second end of the controller is connected to the first electric switch through a first time delay gating unit, the third end of the controller is connected to the third electric switch through the second time delay gating unit, the fourth end of the controller is connected to the fourth electric switch, the controller controls the first diagonal switch and the second diagonal switch to be sequentially conducted, and the first electric switch and the third electric switch are conducted when the drain voltage of the first electric switch and the third electric switch is zero.
Wherein the controller controls the second electrical switch to conduct when the voltage at its source is equal to the voltage at its drain, and controls the fourth electrical switch to conduct when the voltage at its source is equal to the voltage at its drain.
The first time-delay gating unit comprises a fifth electric switch, a sixth electric switch, a first resistor, a second resistor and a first capacitor, wherein the first resistor and the second resistor are sequentially connected between the second end of the controller and the ground in series, the first capacitor is connected to two ends of the second resistor in parallel, the control end of the fifth electric switch is connected to a node between the first resistor and the second resistor, the first end of the fifth electric switch is connected to the control end of the sixth electric switch, the second end of the fifth electric switch is grounded, the first end of the sixth electric switch is connected to the first electric switch so as to control the on-off of the first electric switch, and the second end of the sixth electric switch is connected to the second end of the controller.
The second time-delay gating unit comprises a seventh electric switch, an eighth electric switch, a third resistor, a fourth resistor and a second capacitor, the third resistor and the fourth resistor are sequentially connected between the third end of the controller and the ground in series, the second capacitor is connected to two ends of the fourth resistor in parallel, the control end of the seventh electric switch is connected to a node between the third resistor and the fourth resistor, the first end of the seventh electric switch is connected to the control end of the eighth electric switch, the second end of the seventh electric switch is grounded, the first end of the eighth electric switch is connected to the third electric switch to control the third electric switch to be switched on and off, and the second end of the eighth electric switch is connected to the third end of the controller.
Wherein the control terminal of the first electrical switch is connected to the first terminal of the sixth electrical switch, the first terminal of the first electrical switch is connected to the second terminal of the second electrical switch, the second terminal of the first electrical switch is grounded, the control terminal of the second electrical switch is connected to the first terminal of the controller, the first terminal of the second electrical switch is connected to the voltage input terminal, the control terminal of the third electrical switch is connected to the first terminal of the eighth electrical switch, the first terminal of the third electrical switch is connected to the second terminal of the fourth electrical switch, the second terminal of the third electrical switch is grounded, the control terminal of the fourth electrical switch is connected to the fourth terminal of the controller, and the first terminal of the fourth electrical switch is connected to the voltage input terminal.
Wherein, the full-bridge converter circuit still includes fifth resistance, sixth resistance, seventh resistance and eighth resistance, the control end of first electric switch passes through the fifth resistance is connected to the first end of sixth electric switch, the control end of second electric switch passes through the sixth resistance is connected to the second end of controller, the control end of third electric switch passes through the seventh resistance is connected to the first end of eighth electric switch, the control end of fourth electric switch passes through the eighth resistance is connected to the fourth end of controller.
The first electric switch, the second electric switch, the third electric switch and the fourth electric switch are all NPN type field effect transistors, and control ends, first ends and second ends of the first electric switch, the second electric switch, the third electric switch and the fourth electric switch are respectively a grid electrode, a drain electrode and a source electrode.
The fifth electric switch and the seventh electric switch are NPN-type triodes, control ends, first ends and second ends of the fifth electric switch and the seventh electric switch are bases, collectors and emitters respectively, the sixth electric switch and the eighth electric switch are PNP-type triodes, and the control ends, the first ends and the second ends of the sixth electric switch and the eighth electric switch are bases, collectors and emitters respectively.
The full-bridge converter circuit further comprises an inductor and a third capacitor, wherein one output end of the rectifier is connected to the first end of the inductor, the second end of the inductor serves as the voltage output end, the other output end of the rectifier is grounded, the anode of the third capacitor is connected to the second end of the inductor, and the cathode of the third capacitor is grounded.
The invention also provides a liquid crystal display device which comprises the full-bridge inverter circuit.
The embodiment of the invention has the following advantages or beneficial effects:
the invention discloses a full-bridge converter circuit, which comprises a full-bridge converter unit, a first time-delay gating unit, a second time-delay gating unit and a controller, wherein the full-bridge converter unit comprises a first electric switch, a second electric switch, a third electric switch, a fourth electric switch, a transformer and a rectifier, the first electric switch and the fourth electric switch are first diagonal switches, the second electric switch and the third electric switch are second diagonal switches, the first electric switch and the second electric switch are connected in series between a voltage input end and ground, the third electric switch and the fourth electric switch are connected in series between the voltage input end and the ground, a first end of a primary coil of the transformer is connected to a node between the first electric switch and the second electric switch, and a second end of the primary coil of the transformer is connected to a node between the third electric switch and the fourth electric switch, the two ends of the secondary coil of the transformer are connected to the two input ends of the rectifier, the two output ends of the rectifier are used as voltage output ends, the first end of the controller is connected to the second electric switch, the second end of the controller is connected to the first electric switch through a first time delay gating unit, the third end of the controller is connected to the third electric switch through the second time delay gating unit, the fourth end of the controller is connected to the fourth electric switch, the controller controls the first diagonal switch and the second diagonal switch to be sequentially conducted, and the first electric switch and the third electric switch are conducted when the drain voltage of the first electric switch and the third electric switch is zero. Because the first electric switch and the third electric switch are conducted at zero potential, the power consumption of the first electric switch and the third electric switch is zero, and therefore the conversion efficiency of the full-bridge converter circuit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a circuit diagram of a full-bridge inverter circuit according to a first embodiment of the present invention;
FIG. 2 is a waveform diagram of the drive of the controller of FIG. 1 to drive a first electrical switch, a second electrical switch, a third electrical switch, and a fourth electrical switch;
fig. 3 is a voltage waveform diagram of upper and lower tube conduction in the full-bridge converter cell of fig. 1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Furthermore, the following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. Directional phrases used in this disclosure, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the invention, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified. In the present specification, the term "step" is used to mean not only an independent step but also an independent step unless clearly distinguished from other steps, as long as the intended function of the step is achieved. In the present specification, the numerical range represented by "to" means a range including numerical values before and after "to" as a minimum value and a maximum value, respectively. In the drawings, structures that are similar or identical are denoted by the same reference numerals.
Referring to fig. 1, a full-bridge inverter circuit 100 according to a first embodiment of the present invention is provided. The full-bridge inverter circuit 100 includes a full-bridge inverter unit 10, a first time-delay gating unit 20, a second time-delay gating unit 30, and a controller 40. The full-bridge inverter unit 10 comprises a first electrical switch Q1, a second electrical switch Q2, a third electrical switch Q3, a fourth electrical switch Q4, a transformer T and a rectifier Z, the first and fourth electrical switches Q1 and Q4 are first diagonal switches, the second and third electrical switches Q2 and Q3 are second diagonal switches, the first and second electrical switches Q1 and Q2 are connected in series between a voltage input Vin and ground, the third and fourth electrical switches Q3 and Q4 are connected in series between the voltage input Vin and ground, a first end of a primary coil of the transformer T is connected to a node between the first and second electrical switches Q1 and Q2, a second end of the primary coil of the transformer T is connected to a node between the third and fourth electrical switches Q3 and Q4, two ends of a secondary coil of the transformer T are connected to two inputs of the rectifier Z, two output ends of the rectifier Z are used as voltage output ends, a second end of the controller 40 is connected to the first electric switch Q1 through a first time delay gating unit 20, a first end of the controller 40 is connected to the second electric switch Q2, a fourth end of the controller 40 is connected to the fourth electric switch Q4, a third end of the controller 40 is connected to the third electric switch Q3 through the second time delay gating unit 30, the controller 40 controls the first diagonal switch and the second diagonal switch to be sequentially switched, and the first electric switch Q1 and the third electric switch Q3 are turned on when drain voltages thereof are zero.
It should be noted that, with continued reference to fig. 2, the controller 40 controls the conduction time of the electric switches in each diagonal switch to be the same. That is, when the controller 40 controls the first and fourth electric switches Q1 and Q4 to be turned on, the first and fourth electric switches Q1 and Q4 are turned on for the same time. Since the first time-delay gating unit 20 is connected to the first electric switch Q1, the fourth electric switch Q4 is turned off first, and the first electric switch Q1 is then turned off. By controlling the second and third electrical switches Q2, Q3 to conduct when the controller 40 controls the second and third electrical switches Q2, Q3 to conduct for the same time. Since the second time-delay gating unit 30 is connected to the third electric switch Q3, the second electric switch Q2 is turned off first, and the third electric switch Q1 is then turned off. The controller 40 first controls one pair of diagonal switches to be turned on, and controls the other pair of diagonal switches to be turned on when the last turned-off one of the turned-on diagonal switches is to be turned off.
In the present embodiment, the first and third electrical switches Q1, Q3 are in a down tube position. The second and fourth electrical switches Q2, Q4 are in a top tube position. Due to the existence of the first time-delay gating unit 20 and the second time-delay gating unit 30, the parasitic capacitance of the pair of diagonal switches in the conducting state and the leakage inductance of the transformer T form a resonant structure, so that oscillation voltage is generated at two ends of the primary coil of the transformer, and through setting the time delay of the first time-delay gating unit 20 and the second time-delay gating unit 30, when the oscillation voltage at the drain of the electric switch connected with the first time-delay gating unit 20 or the second time-delay gating unit 30 is zero, the electric switch is conducted, and the electric switch is conducted at zero voltage.
For example, when the controller 40 controls the first electrical switch Q1 and the fourth electrical switch Q4 to be turned on first, the fourth electrical switch Q4 is turned on due to the existence of the first time-delay gating unit 20, and the first electrical switch Q1 is turned on in a time-delay manner, so that a resonant structure is formed among the first electrical switch Q1, the fourth electrical switch Q4 and the transformer T. An oscillating voltage is generated across the primary coil of the transformer T, and the first electric switch Q1 is turned on when the oscillating voltage at the drain of the first electric switch Q1 is zero by adjusting the parameters of the first time delay gating unit 20. Then, the first electrical switch Q1 is turned on for zero voltage. Similarly, the second switch Q2, the third switch Q3 and the transformer T may form a resonant structure. The third electrical switch Q3 is turned on when the oscillating voltage at the drain of the third electrical switch Q3 is zero by adjusting the parameters of the second time-delay gating unit 30. Then, the third electrical switch Q3 is turned on for zero voltage. The power consumption of the first and third electrical switches Q1 and Q3 in the full-bridge inverter unit at the down tube position is zero, thereby improving the conversion efficiency of the full-bridge inverter circuit 100.
Further low, the controller 40 controls the second electrical switch Q2 to conduct when the voltage at its source is equal to the voltage at its drain, and controls the fourth electrical switch Q4 to conduct when the voltage at its source is equal to the voltage at its drain.
When the controller 40 controls the first switch Q1 and the fourth switch Q4 to be turned on, the first switch Q1, the fourth switch Q4 and the transformer T form a resonant structure, and an oscillating voltage is generated across the primary coil of the transformer T. When the oscillating voltage at the source of the fourth electrical switch Q4 is the voltage at the voltage input, the controller 40 controls the fourth electrical switch Q4 to be turned on, and since the voltages at the source and the drain of the fourth electrical switch Q4 are equal, the voltage of the fourth electrical switch Q4 is zero, and the power consumption of the fourth electrical switch Q4 is zero (see fig. 3). Similarly, when the controller 40 controls the second and third electric switches Q2 and Q3 to be turned on, the second and third electric switches Q2 and Q3 and the transformer T form a resonant structure, and an oscillating voltage is generated across the primary coil of the transformer T. When the oscillating voltage at the source of the second electrical switch Q2 is the voltage at the voltage input, the controller 40 controls the second electrical switch Q2 to be turned on, and since the voltages at the source and the drain of the second electrical switch Q2 are equal, the voltage of the second electrical switch Q2 is zero, and the power consumption of the second electrical switch Q2 is zero (see fig. 3). Therefore, the power consumption of the second and fourth switches Q2 and Q4 in the full-bridge inverter unit at the top-tube position is zero, and the conversion efficiency of the full-bridge inverter circuit 100 is further improved.
It should be noted that the controller 40 can detect the oscillating voltage at the drains of the first and third electrical switches Q1, Q3 and the oscillating voltage at the sources of the second and fourth electrical switches Q2, Q4.
In this embodiment, the first, second, third and fourth electric switches Q1, Q2, Q3 and Q4 are NPN field effect transistors, and the control, first and second ends of the first, second, third and fourth electric switches Q1, Q2, Q3 and Q4 are gates, drains and sources, respectively. In other embodiments, the first electrical switch Q1, the second electrical switch Q2, the third electrical switch Q3 and the fourth electrical switch Q4 can be adjusted to other types of transistors according to actual needs.
Further, the first time delay gating unit 20 includes a fifth electric switch Q5, a sixth electric switch Q6, a first resistor R1, a second resistor R2, and a first capacitor C1, the first resistor R1 and the second resistor R2 are sequentially connected in series between the second end of the controller 40 and ground, the first capacitor C1 is connected in parallel to two ends of the second resistor R2, a control end of the fifth electric switch Q5 is connected to a node between the first resistor R1 and the second resistor R2, a first end of the fifth electric switch Q5 is connected to a control end of the sixth electric switch Q6, a second end of the fifth electric switch Q5 is grounded, a first end of the sixth electric switch Q6 is connected to the first electric switch Q1 to control the first electric switch Q1, and a second end of the sixth electric switch Q6 is connected to the second end of the controller 40.
In this embodiment, the fifth electric switch Q5 is an NPN transistor, and the sixth electric switch Q6 is a PNP transistor. The control terminal, the first terminal and the second terminal of the fifth electric switch Q5 are a base, a collector and an emitter, respectively, and the control terminal, the first terminal and the second terminal of the sixth electric switch Q6 are a base, a collector and an emitter, respectively. The signal output from the second terminal of the controller 40 first charges the first capacitor C1 through the first resistor R1 and the second resistor R2 with a charging time constant t ═ R2 × C1, where in this equation, R2 represents the resistance value of the second resistor R2, and C1 represents the capacitance value of the first capacitor C1. After the charging is completed, the base voltage of the fifth electric switch Q5 rises, the fifth electric switch Q5 is turned on, the fifth electric switch Q5 is turned on, and then the base voltage of the sixth electric switch Q6 is pulled down, the sixth electric switch Q6 is turned on, so that the first electric switch Q1 is turned on. The charging time of the first capacitor C1, i.e., the time for the first switch Q1 to be turned on, is changed by adjusting the resistance of the second resistor R2 and the capacitance of the first capacitor C1.
The second time-delay gating unit 30 includes a seventh electric switch Q7, an eighth electric switch Q8, a third resistor R3, a fourth resistor R4, and a second capacitor C2, the third resistor R3 and the fourth resistor R4 are sequentially connected in series between the third terminal of the controller 40 and the ground, the second capacitor C2 is connected in parallel to both ends of the fourth resistor R4, a control end of the seventh electric switch Q7 is connected to a node between the third resistor R3 and the fourth resistor R4, a first end of the seventh electric switch Q7 is connected to a control end of the eighth electric switch Q8, a second end of the seventh electric switch Q7 is grounded, a first end of the eighth electric switch Q8 is connected to the third electric switch Q3 to control on/off of the third electric switch Q3, and a second end of the eighth electric switch Q8 is connected to the third terminal of the controller 40.
In this embodiment, the seventh electric switch Q7 is an NPN transistor, and the eighth electric switch Q8 is a PNP transistor. The control terminal, the first terminal and the second terminal of the seventh electric switch Q7 are a base, a collector and an emitter, respectively, and the control terminal, the first terminal and the second terminal of the eighth electric switch Q8 are a base, a collector and an emitter, respectively. The signal output from the third terminal of the controller 40 is first charged into the second capacitor C2 through the third resistor R3 and the fourth resistor R4 with a charging time constant t ═ R4 × C2, where in this equation, R4 represents the resistance value of the fourth resistor R2, and C2 represents the capacitance value of the second capacitor C2. After the charging is completed, the base voltage of the seventh electric switch Q7 rises, the seventh electric switch Q7 is turned on, the seventh electric switch Q7 is turned on, and then the base voltage of the eighth electric switch Q8 is pulled down, the eighth electric switch Q7 is turned on, so that the third electric switch Q3 is turned on. The charging time of the second capacitor C2, i.e., the time for the third switch Q3 to be turned on, is changed by adjusting the resistance of the fourth resistor R4 and the capacitance of the second capacitor C2.
Further, a control terminal of the first electrical switch Q1 is connected to a first terminal of the sixth electrical switch Q6, a first terminal of the first electrical switch Q1 is connected to a second terminal of the second electrical switch Q2, a second terminal of the first electrical switch Q1 is grounded, a control terminal of the second electrical switch Q2 is connected to a first terminal of the controller 40, a first terminal of the second electrical switch Q2 is connected to the voltage input terminal Vin, a control terminal of the third electrical switch Q3 is connected to a first terminal of the eighth electrical switch Q8, a first terminal of the third electrical switch Q3 is connected to a second terminal of the fourth electrical switch Q4, a second terminal of the third electrical switch Q3 is grounded, a control terminal of the fourth electrical switch Q4 is connected to a fourth terminal of the controller 40, and a first terminal of the fourth electrical switch Q4 is connected to the voltage input terminal Vin.
Further, the full-bridge inverter circuit 100 further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8, the control terminal of the first electrical switch Q1 is connected to the first terminal of the sixth electrical switch Q6 through the fifth resistor R5, the control terminal of the second electrical switch Q2 is connected to the second terminal of the controller 40 through the sixth resistor R6, the control terminal of the third electrical switch Q3 is connected to the first terminal of the eighth electrical switch Q8 through the seventh resistor R7, and the control terminal of the fourth electrical switch Q4 is connected to the fourth terminal of the controller 40 through the eighth resistor R8.
The fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 all function to limit current.
Further, the full-bridge converter circuit 100 further includes an inductor L and a third capacitor C3, an output terminal of the rectifier Z is connected to a first terminal of the inductor L, a second terminal of the inductor L is used as the voltage output terminal, and another output terminal of the rectifier Z is grounded. The anode of the third capacitor C3 is connected to the second end of the inductor L, and the cathode of the third capacitor C3 is grounded.
Wherein the inductor L functions to suppress a pulse component of the dc voltage output from the rectifier Z. The third capacitor C3 is used for storing energy.
The embodiment of the second scheme of the invention also provides a liquid crystal display device. The liquid crystal display device includes the full-bridge inverter circuit 100 in the first scheme embodiment described above. Since the structure and function of the full-bridge inverter circuit 100 have been described in detail, they are not described in detail herein.
In the present embodiment, the liquid crystal display device includes the full bridge inverter circuit 100. The full-bridge inverter circuit 100 includes a full-bridge inverter unit 10, a first time-delay gating unit 20, a second time-delay gating unit 30, and a controller 40. The full-bridge inverter unit 10 comprises a first electrical switch Q1, a second electrical switch Q2, a third electrical switch Q3, a fourth electrical switch Q4, a transformer T and a rectifier Z, the first and fourth electrical switches Q1 and Q4 are first diagonal switches, the second and third electrical switches Q2 and Q3 are second diagonal switches, the first and second electrical switches Q1 and Q2 are connected in series between a voltage input Vin and ground, the third and fourth electrical switches Q3 and Q4 are connected in series between the voltage input Vin and ground, a first end of a primary coil of the transformer T is connected to a node between the first and second electrical switches Q1 and Q2, a second end of the primary coil of the transformer T is connected to a node between the third and fourth electrical switches Q3 and Q4, two ends of a secondary coil of the transformer T are connected to two inputs of the rectifier Z, two output ends of the rectifier Z are used as voltage output ends, a second end of the controller 40 is connected to the first electric switch Q1 through a first time delay gating unit 20, a first end of the controller 40 is connected to the second electric switch Q2, a fourth end of the controller 40 is connected to the fourth electric switch Q4, a third end of the controller 40 is connected to the third electric switch Q3 through the second time delay gating unit 30, the controller 40 controls the first diagonal switch and the second diagonal switch to be sequentially switched, and the first electric switch Q1 and the third electric switch Q3 are turned on when drain voltages thereof are zero. Since the first switch Q1 and the third switch Q3 are turned on at zero potential, the power consumption of the first switch Q1 and the third switch Q3 is zero, thereby improving the conversion efficiency of the full-bridge converter circuit 100.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.
Claims (10)
1. A full-bridge converter circuit comprising a full-bridge converter unit, a first time-delay gating unit, a second time-delay gating unit and a controller, wherein the full-bridge converter unit comprises a first electric switch, a second electric switch, a third electric switch, a fourth electric switch, a transformer and a rectifier, the first electric switch and the fourth electric switch are first diagonal switches, the second electric switch and the third electric switch are second diagonal switches, the first electric switch and the second electric switch are connected in series between a voltage input terminal and ground, the third electric switch and the fourth electric switch are connected in series between the voltage input terminal and ground, a first end of a primary coil of the transformer is connected to a node between the first electric switch and the second electric switch, a second end of the primary coil of the transformer is connected to a node between the third electric switch and the fourth electric switch, two ends of a secondary coil of the transformer are connected to two input ends of the rectifier, two output ends of the rectifier are used as voltage output ends, a first end of the controller is connected to the second electric switch, a second end of the controller is connected to the first electric switch through a first time delay gating unit, a third end of the controller is connected to the third electric switch through the second time delay gating unit, a fourth end of the controller is connected to the fourth electric switch, the controller can detect an oscillating voltage at drain electrodes of the first electric switch and the third electric switch and an oscillating voltage at source electrodes of the second electric switch and the fourth electric switch, when the oscillating voltage at the source electrode of the fourth electric switch is the voltage at the voltage input end, the controller controls the fourth electric switch to be conducted, and when the oscillating voltage at the source electrode of the second electric switch is the voltage at the voltage input end, the controller controls the second electric switch to be conducted.
2. The full-bridge inverter circuit of claim 1, wherein the controller controls the second electrical switch to conduct when the voltage at its source is equal to the voltage at its drain, and controls the fourth electrical switch to conduct when the voltage at its source is equal to the voltage at its drain.
3. The full-bridge inverter circuit according to claim 2, wherein the first time-delay gating unit comprises a fifth electric switch, a sixth electric switch, a first resistor, a second resistor and a first capacitor, the first resistor and the second resistor are sequentially connected in series between the second end of the controller and the ground, the first capacitor is connected in parallel with two ends of the second resistor, the control end of the fifth electric switch is connected to a node between the first resistor and the second resistor, the first end of the fifth electric switch is connected to the control end of the sixth electric switch, the second end of the fifth electric switch is connected to the ground, the first end of the sixth electric switch is connected to the first electric switch to control the on/off of the first electric switch, and the second end of the sixth electric switch is connected to the second end of the controller.
4. The full-bridge inverter circuit according to claim 3, wherein the second time-delay gating unit comprises a seventh electric switch, an eighth electric switch, a third resistor, a fourth resistor and a second capacitor, the third resistor and the fourth resistor are sequentially connected in series between the third terminal of the controller and the ground, the second capacitor is connected in parallel with two terminals of the fourth resistor, the control terminal of the seventh electric switch is connected to a node between the third resistor and the fourth resistor, the first terminal of the seventh electric switch is connected to the control terminal of the eighth electric switch, the second terminal of the seventh electric switch is grounded, the first terminal of the eighth electric switch is connected to the third electric switch to control the on-off of the third electric switch, and the second terminal of the eighth electric switch is connected to the third terminal of the controller.
5. The full-bridge inverter circuit according to claim 4, wherein the control terminal of the first electrical switch is connected to the first terminal of the sixth electrical switch, the first terminal of the first electrical switch is connected to the second terminal of the second electrical switch, the second terminal of the first electrical switch is grounded, the control terminal of the second electrical switch is connected to the first terminal of the controller, the first terminal of the second electrical switch is connected to the voltage input terminal, the control terminal of the third electrical switch is connected to the first terminal of the eighth electrical switch, the first terminal of the third electrical switch is connected to the second terminal of the fourth electrical switch, the second terminal of the third electrical switch is grounded, the control terminal of the fourth electrical switch is connected to the fourth terminal of the controller, and the first terminal of the fourth electrical switch is connected to the voltage input terminal.
6. The full-bridge inverter circuit according to claim 5, wherein the full-bridge inverter circuit further comprises a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein the control terminal of the first electrical switch is connected to the first terminal of the sixth electrical switch through the fifth resistor, the control terminal of the second electrical switch is connected to the second terminal of the controller through the sixth resistor, the control terminal of the third electrical switch is connected to the first terminal of the eighth electrical switch through the seventh resistor, and the control terminal of the fourth electrical switch is connected to the fourth terminal of the controller through the eighth resistor.
7. The full-bridge inverter circuit according to claim 5, wherein the first, second, third and fourth electrical switches are NPN FETs, and the control terminals, the first terminals and the second terminals of the first, second, third and fourth electrical switches are gates, drains and sources, respectively.
8. The full-bridge inverter circuit according to claim 4, wherein the fifth and seventh electrical switches are NPN type transistors, the control, first and second terminals of the fifth and seventh electrical switches are bases, collectors and emitters, respectively, the sixth and eighth electrical switches are PNP type transistors, and the control, first and second terminals of the sixth and eighth electrical switches are bases, collectors and emitters, respectively.
9. The full-bridge inverter circuit according to claim 1, wherein the full-bridge inverter circuit further comprises an inductor and a third capacitor, one output terminal of the rectifier is connected to a first terminal of the inductor, a second terminal of the inductor is used as the voltage output terminal, the other output terminal of the rectifier is grounded, an anode of the third capacitor is connected to the second terminal of the inductor, and a cathode of the third capacitor is grounded.
10. A liquid crystal display device comprising a full bridge inverter circuit as claimed in any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710090941.2A CN106712524B (en) | 2017-02-20 | 2017-02-20 | Full-bridge converter circuit and liquid crystal display device |
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| CN201710090941.2A CN106712524B (en) | 2017-02-20 | 2017-02-20 | Full-bridge converter circuit and liquid crystal display device |
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| CN106712524A CN106712524A (en) | 2017-05-24 |
| CN106712524B true CN106712524B (en) | 2020-02-07 |
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| CN100511953C (en) * | 2006-01-27 | 2009-07-08 | 尼克森微电子股份有限公司 | Conversion circuit for driving full-bridge type commutation by using push-pull type pulse wave controller |
| US7570087B2 (en) * | 2007-03-23 | 2009-08-04 | System General Corp. | Switching drive circuit for soft switching |
| CN103036405B (en) * | 2011-09-30 | 2015-06-17 | 雅达电源制品（深圳）有限公司 | Synchronous rectification switching tube driving method and device of phase-shifted full-bridge circuit |
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