CN106688084A - Manufacturing method of nitride semiconductor laminated body and nitride semiconductor laminated body - Google Patents

Abstract

This method for producing a nitride semiconductor laminate comprises: a first nitride semiconductor layer formation step wherein a first nitride semiconductor layer (12) is formed on top of a substrate within a reactor; a second nitride semiconductor layer formation step wherein a second nitride semiconductor layer (13) is formed on top of the first nitride semiconductor layer (12); and a third nitride semiconductor layer formation step wherein a third nitride semiconductor layer (14), which has a larger band gap than the second nitride semiconductor layer (13), is formed on the upper surface of the second nitride semiconductor layer (13). The second nitride semiconductor layer formation step and the third nitride semiconductor layer formation step are carried out without interruption, and the third nitride semiconductor layer formation step follows the second nitride semiconductor layer formation step.

Description

Manufacturing method of nitride semiconductor laminated body and nitride semiconductor laminated body

technical field

The present invention relates to a method for manufacturing a nitride semiconductor laminate represented by a semiconductor switching element such as a HEMT (High Electron Mobility Transistor: High Electron Mobility Transistor), and the nitride semiconductor laminate.

Background technique

Nitride semiconductors, which are group III-V compound semiconductors represented by GaN (gallium nitride), are expected to be applied to switching elements used in power devices and the like in recent years. This is because the nitride semiconductor has a band gap as large as about 3.4eV, an insulation breakdown electric field about 10 times higher, and an electron saturation speed about 2.5 times higher than the conventional semiconductor using Si (silicon). It is suitable for power devices. characteristic. A switching element having a GaN/AlGaN heterostructure provided on a substrate such as SiC (silicon carbide), Al ₂ O ₃ (sapphire), or Si has been proposed (see, for example, US Patent No. 6,849,882 (Patent Document 1)) . In addition, AlGaN is a mixture of GaN and AlN (aluminum nitride).

In the above-mentioned switching element, in addition to the spontaneous polarization caused by the asymmetric structure in the c-axis direction of the wurtzite structure which is the crystal structure of GaN, piezoelectricity caused by the lattice mismatch between AlGaN and GaN The polarization caused by the effect produces a two-dimensional electron gas with a high electron density of about 1×10 ¹² cm ^-2 to 1×10 ¹³ cm ^-2 . The switching element switches between a state in which predetermined electrodes are electrically connected (on state) and a state in which predetermined electrodes are not electrically connected (off state) by controlling the electron density of the two-dimensional electron gas.

Hereinafter, an example of a typical structure of the switching element as described above will be described with reference to FIGS. 7 and 8 . 7 and 8 are schematic cross-sectional views showing a typical structure of a conventional switching element 1000 . In addition, FIG. 7 shows the switching element 1000 in the on state. On the other hand, FIG. 8 shows the switching element 1000 in the OFF state.

As shown in FIG. 7 and FIG. 8, the switching element 1000 includes: a substrate 1001; a buffer layer 1002 formed on the upper surface of the substrate 1001; electron transit layer 1003 ; electron supply layer 1004 formed on the upper surface of electron transit layer 1003 and composed of AlGaN; source electrode 1005 ; drain electrode 1006 ; and gate electrode 1007 . The source electrode 1005 , drain electrode 1006 and gate electrode 1007 are formed on the upper surface of the electron supply layer 1004 . In addition, the gate electrode 1007 is located between the source electrode 1005 and the drain electrode 1006 .

The switching element 1000 is a normally-on type. Therefore, as shown in FIG. 7, even if the potential of the gate electrode 1007 is the same as the potential of the source electrode 1005, even if the gate electrode 1007 is open, an electric shock occurs near the interface where the electron transit layer 1003 and the electron supply layer 1004 join. The two-dimensional electron gas layer 1008 and the switching element 1000 are also turned on. In the switching element 1000 in the ON state, if the potential of the drain electrode 1006 is higher than the potential of the source electrode 1005 , a current flows between the source electrode 1005 and the drain electrode 1006 .

On the other hand, as shown in FIG. 8, when the potential of the gate electrode 1007 is lower than the threshold voltage with reference to the potential of the source electrode 1005, under the gate electrode 1007, in the electron transit layer 1003 and the electron supply layer The two-dimensional electron gas layer 1008 is no longer generated near the interface joined by 1004 . That is, a depletion region 1009 located below the gate electrode 1007 is formed. As a result, the switching element 1000 is turned off, and no current flows between the source electrode 1005 and the drain electrode 1006 .

As a method of reducing the on-resistance by increasing the electron density and mobility in the above-mentioned two-dimensional electron gas layer 1008, it may be considered to use an electron supply layer composed of AlGaN and AlN instead of the electron supply layer 1004 composed of AlGaN. Methods.

Hereinafter, an example of a switching element having an electron supply layer made of AlGaN and AlN will be described with reference to FIG. 9 . FIG. 9 is a schematic cross-sectional view for explaining a switching element 2000 having an electron supply layer 2004 made of AlGaN and AlN. In addition, regarding the switching element 2000 shown in FIG. 9 , the same parts as those of the switching element 1000 shown in FIGS. 7 and 8 are denoted by the same reference numerals and overlapping descriptions are omitted.

As shown in FIG. 9 , the switching element 2000 includes a substrate 1001 , a buffer layer 1002 , an electron transit layer 1003 , an electron supply layer 2004 , a source electrode 1005 , a drain electrode 1006 , and a gate electrode 1007 . The electron supply layer 2004 includes a spacer layer 2004A made of AlN and a barrier layer 2004B made of AlGaN.

The difference between the bandgap of the spacer layer 2004A and the bandgap of the electron transit layer 1003 is greater than the difference between the bandgap of the spacer layer 2004A and the bandgap of the barrier layer 2004B. In addition, the lattice mismatch between the spacer layer 2004A and the electron transit layer 1003 is larger than the lattice mismatch between the spacer layer 2004A and the barrier layer 2004B. As a result, the electron density and mobility in the two-dimensional electron gas layer 1008 increase, and the on-resistance decreases.

prior art literature

patent documents

Patent Document 1: Specification of US Patent No. 6,849,882

Contents of the invention

The technical problem to be solved by the invention

However, in the switching element 2000 described above, when the spacer layer 2004A is formed, the underlying electron transit layer 1003 is decomposed, and unevenness occurs on the upper surface of the electron transit layer 1003 (the interface between the electron transit layer 1003 and the spacer layer 2004A). . Furthermore, since the spacer layer 2004A formed on the upper surface of the electron transit layer 1003 is extremely thin at 5 nm or less, its thickness becomes uneven due to the unevenness of the upper surface of the electron transit layer 1003 . Furthermore, when the states of the electron transit layer 1003 and the spacer layer 2004A in the in-plane direction become uneven in this way, the characteristics of the switching element 2000 deteriorate, such as a reduction in electron mobility.

In this way, the unevenness of the upper surface of the electron transit layer 1003 causes deterioration of the characteristics of the switching element 2000, which is a problem.

Here, a phenomenon in which unevenness occurs on the upper surface of the electron transit layer 1003 will be described with reference to FIG. 10 . FIG. 10 is a schematic cross-sectional view for explaining a phenomenon in which unevenness is generated on the upper surface of the electron transit layer 1003 in the switching element 2000 . 10 shows that the formation method of the spacer layer 2004A made of AlN is the MOCVD (Metal Organic Chemical Vapor Deposition) method most widely used as a mass production method of semiconductor elements. Furthermore, FIG. 10 shows a case where the carrier gas for transporting the liquid organometallic material to the reaction furnace is H ₂ (hydrogen), which is most widely used from the viewpoint of preventing oxidation of raw materials and products.

As shown in FIG. 10, when it is desired to form a spacer layer 2004A composed of AlN on the upper surface of an electron transit layer 1003 composed of GaN, GaN constituting the electron transit layer 1003 is decomposed into Ga (gallium) and N ( nitrogen). This is because the substrate temperature (900° C. or higher) required to grow AlN constituting the spacer layer 2004A is higher than the substrate temperature (800° C. or higher) at which GaN constituting the electron transit layer 1003 thermally decomposes. N generated by thermal decomposition of GaN is desorbed as gaseous N ₂ (nitrogen), or reacts with surrounding H ₂ to become NH ₃ (ammonia) and desorbs.

In this way, when the above-mentioned N desorbs from the electron transit layer 1003, there is abundant H ₂ as a carrier gas around GaN, and H (hydrogen) is easily combined with N generated by thermal decomposition. Therefore, the consumption of N is suppressed. Promoted, thermal decomposition is promoted.

In addition, from the viewpoint of suppressing the reaction of the raw materials in the gas phase and accelerating the reaction of the raw materials on the substrate 1001, it is preferable to grow the above-mentioned AlN by keeping the inside of the reaction furnace at a low pressure (for example, 0.1 atmosphere or less). At low pressure, the detachment of _N2 and _NH3 is promoted, thus, thermal decomposition is promoted.

Such thermal decomposition is promoted, thereby causing unevenness on the upper surface of the electron transit layer 1003 .

Therefore, the technical problem to be solved by the present invention is to provide a method for producing a nitride semiconductor laminate and a nitride semiconductor laminate capable of suppressing the occurrence of unevenness on the upper surface of a specific nitride semiconductor layer.

In addition, as an example of the above-mentioned nitride semiconductor stacked body, there is a nitride semiconductor stacked substrate including a substrate and a plurality of nitride semiconductor layers stacked on the substrate.

In addition, as another example of the aforementioned nitride semiconductor stacked body, there is a nitride semiconductor stacked device (for example, a switching element) formed using the aforementioned nitride semiconductor stacked substrate.

In addition, the switching element 2000 in FIG. 9 is shown for the sake of clarifying the technical problem to be solved by the present invention and for convenience, and is not a known technology.

Means used to solve technical problems

In order to solve the above-mentioned technical problems, the method for manufacturing a nitride semiconductor laminate of the present invention is characterized by comprising:

A first nitride semiconductor layer forming step of forming a first nitride semiconductor layer above a substrate in a reaction furnace;

a second nitride semiconductor layer forming step of forming a second nitride semiconductor layer above the first nitride semiconductor layer; and

a third nitride semiconductor layer forming step of forming a third nitride semiconductor layer having a larger bandgap than that of the second nitride semiconductor layer on the upper surface of the second nitride semiconductor layer,

There is no interruption between the second nitride semiconductor layer forming step and the third nitride semiconductor layer forming step, and the third nitride semiconductor layer forming step and the second nitride semiconductor layer forming step are performed continuously.

In the method of manufacturing a nitride semiconductor laminate according to one embodiment,

The above-mentioned second nitride semiconductor layer forming step has:

a fourth nitride semiconductor layer forming step of forming a fourth nitride semiconductor layer; and

a fifth nitride semiconductor layer forming step of forming a fifth nitride semiconductor layer above the fourth nitride semiconductor layer,

The substrate temperature in the step of forming the fifth nitride semiconductor layer is higher than the temperature of the substrate in the step of forming the fourth nitride semiconductor layer,

The furnace pressure in the fifth nitride semiconductor layer forming step is lower than the furnace pressure in the fourth nitride semiconductor layer forming step.

In the method of manufacturing a nitride semiconductor laminate according to one embodiment,

The second nitride semiconductor layer forming step includes a sixth nitride semiconductor layer forming step of forming a sixth nitride semiconductor layer between the fourth nitride semiconductor layer and the fifth nitride semiconductor layer,

The substrate temperature in the sixth nitride semiconductor layer forming step is gradually changed from the same substrate temperature as in the fourth nitride semiconductor layer forming step to the same substrate temperature as in the fifth nitride semiconductor layer forming step. temperature,

The pressure in the furnace in the sixth nitride semiconductor layer forming step is gradually changed from the same pressure in the furnace in the fourth nitride semiconductor layer forming step to the same furnace pressure in the fifth nitride semiconductor layer forming step as described above. pressure.

In the method of manufacturing a nitride semiconductor laminate according to one embodiment,

The second nitride semiconductor layer is made of GaN,

The third nitride semiconductor layer is composed of AlxGa1 _{- xN} (0<x<1).

The nitride semiconductor laminate of the present invention is characterized by comprising:

Substrate;

a first nitride semiconductor layer formed over the substrate;

a second nitride semiconductor layer formed above the first nitride semiconductor layer; and

a third nitride semiconductor layer having a larger bandgap than that of the second nitride semiconductor layer is formed on the upper surface of the second nitride semiconductor layer,

The second nitride semiconductor layer and the third nitride semiconductor layer are formed without interruption between the formation of the second nitride semiconductor layer and the formation of the third nitride semiconductor layer. The formation is carried out continuously with the formation of the above-mentioned second nitride semiconductor layer.

In the nitride semiconductor stacked body of one embodiment,

The above-mentioned second nitride semiconductor layer has:

a fourth nitride semiconductor layer having a carbon concentration of less than 5×10 ¹⁶ /cm ³ ; and

A fifth nitride semiconductor layer having a carbon concentration of 5×10 ¹⁶ /cm ³ to less than 1×10 ¹⁸ /cm ³ is formed on the fourth nitride semiconductor layer.

A nitride semiconductor laminate according to one embodiment includes a sixth nitride semiconductor layer formed between the fourth nitride semiconductor layer and the fifth nitride semiconductor layer,

The carbon concentration of the sixth nitride semiconductor layer is substantially equal to the carbon concentration of the fourth nitride semiconductor layer in the vicinity of the interface between the fourth nitride semiconductor layer and the sixth nitride semiconductor layer, and in the vicinity of the interface of the fifth nitride semiconductor layer. The vicinity of the interface between the compound semiconductor layer and the sixth nitride semiconductor layer is substantially equal to the carbon concentration of the fifth nitride semiconductor layer, and the carbon concentration increases from the lower side of the sixth nitride semiconductor layer to the sixth nitride semiconductor layer. The upper side advances and gradually increases.

In the nitride semiconductor stacked body of one embodiment,

The second nitride semiconductor layer is made of GaN,

The third nitride semiconductor layer is composed of AlxGa1 _{- xN} (0<x<1).

In the nitride semiconductor stacked body of one embodiment,

On the upper surface of the third nitride semiconductor layer, the surface roughness obtained by an atomic force microscope is 0.5 nm or less in a scanning range of 1 μm square.

Invention effect

In the method for producing a nitride semiconductor laminate of the present invention, there is no interruption between the step of forming the second nitride semiconductor layer and the step of forming the third nitride semiconductor layer, and the step of forming the third nitride semiconductor layer and the step of forming the second nitride semiconductor layer Since the forming process is performed continuously, it is possible to suppress occurrence of unevenness on the upper surface of the second nitride semiconductor. Therefore, it is possible to suppress occurrence of unevenness on the upper surface of a specific nitride semiconductor layer.

In the nitride semiconductor laminate of the present invention, the formation of the second nitride semiconductor layer and the third nitride semiconductor layer are not interrupted between the formation of the second nitride semiconductor layer and the formation of the third nitride semiconductor layer, and the third nitride semiconductor layer Since the formation of the semiconductor layer and the formation of the second nitride semiconductor layer are performed consecutively, it is possible to suppress the occurrence of unevenness on the upper surface of the second nitride semiconductor layer. Therefore, it is possible to suppress occurrence of unevenness on the upper surface of a specific nitride semiconductor layer.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a switching element according to a first embodiment of the present invention.

2 is a timing chart for explaining an electron transit layer forming step and an electron supply layer forming step according to the first embodiment of the present invention.

3 is a schematic cross-sectional view of a switching element according to a second embodiment of the present invention.

4 is a timing chart for explaining an electron transit layer forming step and an electron supply layer forming step according to the second embodiment of the present invention.

5 is a schematic cross-sectional view of a switching element according to a third embodiment of the present invention.

6 is a timing chart for explaining an electron transit layer forming step and an electron supply layer forming step according to a third embodiment of the present invention.

7 is a schematic cross-sectional view of a conventional switching element in an on state.

FIG. 8 is a schematic cross-sectional view of a conventional switching element in an off state.

9 is a schematic cross-sectional view of a switching element of a reference example.

FIG. 10 is a schematic cross-sectional view for explaining a phenomenon in which unevenness occurs on the upper surface of the electron transit layer of the above reference example.

detailed description

Hereinafter, a nitride semiconductor stacked body (in particular, a nitride semiconductor stacked substrate) and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings. In addition, in the following, for concrete description, a switching element as a nitride semiconductor multilayer device using the nitride semiconductor multilayer substrate according to one embodiment of the present invention will be described as an example. In addition, each cross-sectional view referred to in the following description is shown with emphasis on main parts for convenience of description, and therefore the dimensional ratio of each component on the drawings does not necessarily match the actual dimensional ratio. In addition, in each drawing referred to in the following description, the same code|symbol is attached|subjected to the same component from a viewpoint of making description easy to understand.

In addition, below, for each layer constituting the nitride semiconductor multilayer substrate according to the embodiment of the present invention, the elements (materials) constituting the layer are exemplified, and the gist is to show the main elements constituting the layer, not the Elements other than this element (for example, impurities, etc.) are not contained at all.

[the first embodiment]

First, the nitride semiconductor multilayer substrate and its manufacturing method according to the first embodiment of the present invention will be described with reference to the drawings.

1 is a schematic cross-sectional view showing the structure of a switching element SA using a nitride semiconductor multilayer substrate 10A according to a first embodiment of the present invention.

As shown in FIG. 1 , a nitride semiconductor stacked substrate 10A according to the first embodiment of the present invention includes: a substrate 11 ; a buffer layer 12 formed on the upper surface of the substrate 11 ; The electron transit layer 13; and the electron supply layer 14 formed on the upper surface of the electron transit layer 13. Formation of each layer on the substrate 11 is carried out in a reaction furnace not shown. In addition, the lower surface of the electron supply layer 14 is in contact with the upper surface of the electron transit layer 13 , and no other layers exist between the electron transit layer 13 and the electron supply layer 14 . In addition, the buffer layer 12 is an example of the first nitride semiconductor layer. In addition, the electron transit layer 13 is an example of the second nitride semiconductor layer. In addition, the electron supply layer 14 is an example of the third nitride semiconductor layer.

The substrate 11 is made of, for example, Si, SiC, Al ₂ O ₃ , GaN, AlN, ZnO (zinc oxide), GaAs (gallium arsenide), or the like. Further, the buffer layer 12 is composed of, for example, _{InXAlYGa1 -} XYN (wherein, 0≤X+ _Y≤1 , and 0≤X≤1, and 0≤Y≤1). In addition, substrate 11 and buffer layer 12 may be composed of the same nitride semiconductor. In addition, substrate 11 and buffer layer 12 are not limited to the above-mentioned materials as long as warping and cracking of nitride semiconductor multilayer substrate 10A can be suppressed, and any material may be selected. In addition, on the upper portion of the buffer layer 12, in order to increase the withstand voltage, a withstand voltage GaN layer having a carbon concentration of 5×10 ¹⁶ /cm ³ or more may be formed.

The electron transit layer 13 is made of, for example, undoped GaN having a thickness of not less than 1 μm and not more than 5 μm. Furthermore, the electron transit layer 13 is composed of a base GaN layer 13A and a channel GaN layer 13C formed on the upper surface of the base GaN layer 13A. The formation conditions of the base GaN layer 13A and the channel GaN layer 13C are different from each other. In addition, the carbon concentration of base GaN layer 13A is less than 5×10 ¹⁶ /cm ³ . On the other hand, the carbon concentration of channel GaN layer 13C is not less than 5×10 ¹⁶ /cm ³ and not less than 1×10 ¹⁸ /cm ³ . In addition, base GaN layer 13A is an example of a fourth nitride semiconductor layer. In addition, the channel GaN layer 13C is an example of the fifth nitride semiconductor layer.

In the case where the carbon concentration of the base GaN layer 13A is 5×10 ¹⁶ /cm ³ or more, at the interface between the base GaN layer 13A and the buffer layer 12, dislocations, bending of nanotubes, etc. become small, and the dislocations, nanotubes, etc. Tubes and the like extend into the two-dimensional electron gas region, causing adverse effects on device characteristics. In addition, when the above-mentioned withstand voltage GaN layer is formed on the upper portion of the buffer layer 12, when the carbon concentration of the base GaN layer 13A is 5×10 ¹⁶ /cm ³ or more, the gap between the base GaN layer 13A and the above-mentioned withstand voltage GaN layer Bending of interfaces, dislocations, nanotubes, etc. also becomes smaller.

When the carbon concentration of the above-mentioned channel GaN layer 13C is less than 5×10 ¹⁶ /cm ³ , although the detailed reason is unknown, the flatness of the interface between the channel GaN layer 13C and the spacer layer 14A decreases, and the two-dimensional electron gas region The mobility of the electrons is reduced. In addition, when the carbon concentration of the channel GaN layer 13C is 1×10 ¹⁸ /cm ³ or more, on the contrary, due to excess carbon, the flatness of the interface between the channel GaN layer 13C and the spacer layer 14A deteriorates, and two-dimensional electrons The mobility of electrons in the gas region decreases. In addition, when the spacer layer 14A is not provided between the channel GaN layer 13C and the barrier layer 14B, the flatness of the interface between the channel GaN layer 13C and the barrier layer 14B also deteriorates.

The electron supply layer 14 has: a spacer layer 14A made of AlN, for example 5nm or less; and a barrier layer 14B made of AlZGa1 _-ZN (where 0< _Z <1) for example, 5nm or more and 100nm or less. In addition, the bandgap of the spacer layer 14A is larger than that of any one of the base GaN layer 13A and the channel GaN layer 13C. In addition, the bandgap of the barrier layer 14B is also larger than that of either the base GaN layer 13A or the channel GaN layer 13C. That is, the electron supply layer 14 has a larger band gap than the electron transit layer 13 . Here, it is more preferable that the Al _Z Ga _1-Z N composition ratio Z satisfies 0.1≦Z≦0.5.

Furthermore, the switching element SA described above has a nitride semiconductor multilayer substrate 10A, a source electrode 21 , a drain electrode 22 , and a gate electrode 23 .

The aforementioned source electrode 21 , drain electrode 22 and gate electrode 23 are formed on the upper surface of the electron supply layer 14 . In addition, the gate electrode 23 is arranged between the source electrode 21 and the drain electrode 22 .

In addition, the above-mentioned source electrode 21, drain electrode 22, and gate electrode 23 are each made of metal elements such as Ti, Al, Cu, Au, Pt, W, Ta, Ru, Ir, Pd, Hf, etc., including metal elements among these metal elements. An alloy of at least two kinds, or a nitride containing at least one of these metal elements, or the like. Each of the source electrode 21, the drain electrode 22, and the gate electrode 23 may be composed of a single layer, or may be composed of a plurality of layers with different compositions.

The above-mentioned switching element SA is a normally-on type. Therefore, even if the potential of the gate electrode 23 is the same as that of the source electrode 21, even if the gate electrode 23 is open, the two-dimensional electron gas layer 15 is generated near the interface between the channel GaN layer 13C and the spacer layer 14A, and the switch The element SA is also turned on. When the switching element SA is turned on, if the potential of the drain electrode 22 is higher than the potential of the source electrode 21 , a current flows between the source electrode 21 and the drain electrode 22 . On the other hand, when the potential of the gate electrode 23 is lower than the threshold voltage on the basis of the potential of the source electrode 21 , below the gate electrode 23 , no longer occurs in the vicinity of the interface between the channel GaN layer 13C and the spacer layer 14A. Two-dimensional electron gas layer 15. That is, a region similar to the depletion region 1009 in FIG. 7 is formed under the gate electrode 23, and the switching element SA is turned off. When the switching element SA is turned off, no current flows between the source electrode 21 and the drain electrode 22 .

Thus, in the aforementioned nitride semiconductor multilayer substrate 10A, it is necessary to form the electron supply layer 14 on the upper surface of the electron transit layer 13 made of GaN. Assuming that after the formation of the electron transit layer 13, the substrate temperature is increased, the pressure in the furnace is lowered (the pressure in the reaction furnace containing the substrate 11), and then the formation of the electron supply layer 14 is started. During the pressure in the furnace, GaN forming the electron transit layer 13 is thermally decomposed. In this case, irregularities are generated on the upper surface (interface) of the electron transit layer 13 .

Therefore, in the nitride semiconductor multilayer substrate 10A according to the first embodiment of the present invention, the electron transit layer 13 and the electron supply layer 14 capable of suppressing thermal decomposition of GaN constituting the electron transit layer 13 are formed. The following description will be made with reference to the drawings.

FIG. 2 is a time chart showing changes in substrate temperature, furnace pressure, and supply amount of source gases in an electron transit layer forming step and an electron supply layer forming step. In the electron transit layer forming step and the electron supply layer forming step, the electron transit layer 13 and the electron supply layer 14 are formed by MOCVD. In addition, after the buffer layer forming step of forming the buffer layer 12 on the upper surface of the substrate 11 in the reaction furnace, the electron transit layer forming step and the electron supply layer forming step are sequentially performed in the reaction furnace. In addition, the horizontal axis of FIG. 2 represents time, and the closer to the right side in FIG. 2 of the horizontal axis, the later the time. In addition, the vertical axis of FIG. 2 represents the substrate temperature, the pressure in the furnace, or the supply amount of the source gas. When the vertical axis of FIG. 2 represents the substrate temperature, the higher the vertical axis in FIG. 2 , the higher the substrate temperature. In addition, when the vertical axis of FIG. 2 represents the furnace internal pressure, the higher the vertical axis in FIG. 2 is, the higher the furnace internal pressure is. In addition, when the vertical axis of FIG. 2 represents the supply amount of the raw material gas, the supply amount of the raw material gas increases toward the upper side in FIG. 2 of the vertical axis. In addition, the above buffer layer forming step is an example of the first nitride semiconductor layer forming step. In addition, the above-mentioned electron transit layer forming step is an example of the second nitride semiconductor layer forming step. In addition, the above-mentioned electron supply layer forming step is an example of the third nitride semiconductor layer forming step.

As shown in FIG. 2 , first, an underlying GaN layer 13A made of GaN is formed on the buffer layer 12 (the underlying GaN layer forming step). Specifically, base GaN layer 13A made of GaN is formed by supplying TMG (trimethylgallium) as a raw material of Ga and NH ₃ as a raw material of N into the reaction furnace. At this time, _H2 was used as the carrier gas, the substrate temperature was T1, and the furnace pressure was P1. The substrate temperature T1 is, for example, 600°C to 1300°C, more preferably 700°C to 1200°C. In addition, the furnace internal pressure P1 is 0.15 atmospheric pressure or more, for example. In addition, the above-mentioned underlying GaN layer forming step is an example of the fourth nitride semiconductor layer forming step.

When the formation of the base GaN layer 13A is completed, the supply of TMG is stopped, and the conditions of the channel GaN layer formation step are changed. At this time, the substrate temperature changes from T1 to T2, and the furnace pressure changes from P1 to P2. Here, the above T2 is higher than the above T1, for example, 900°C to 1400°C, more preferably 900°C to 1200°C. In addition, the said P2 is lower than the said P1, for example, it is 0.15 atmosphere or less. In addition, when the supply amounts of TMG and NH ₃ as raw material gases are respectively TMG1 and NH ₃ 1 in the base GaN layer forming step and TMG2 and NH ₃ 2 in the channel GaN layer forming step, it is preferable _TMG2 <TMG1, _NH32 <NH31. This is because the electron supply layer 14 is much thinner than the electron transit layer 13 , so the growth rate is suppressed and the film quality is stabilized. In addition, the above-mentioned channel GaN layer forming step is an example of the fifth nitride semiconductor layer forming step.

Then, after the substrate temperature is stabilized at T2, the furnace pressure is stabilized at P2, the supply rate of TMG is stabilized at TMG2, and the supply rate of _NH3 is stabilized at _NH32 , the channel GaN layer 13C is formed (channel GaN layer formation process). Here, the carbon concentration of the channel GaN layer 13C is in a tendency to become larger than that of the base GaN layer 13A due to the influence of lowering the pressure from P1 to P2.

When the formation of the above-mentioned channel GaN layer 13C is completed, the supply amount of NH ₃ is maintained at NH ₃ 2 , the substrate temperature is maintained at T2, and the pressure in the furnace is maintained at P2. On the other hand, the supply of TMG is stopped, and the TMA (trimethylaluminum) which is a material of Al is supplied, thereby forming the spacer layer 14A (spacer layer forming step). When the formation of the spacer layer 14A starts, the substrate temperature T2 and the furnace pressure P2 have become conditions suitable for the formation of the spacer layer 14A and the barrier layer 14B, and there is no need to adjust the substrate temperature and furnace pressure for a particularly time-consuming process. The formation is interrupted by the adjustment.

When the formation of the spacer layer 14A is completed, the supply of TMG is restarted to form the barrier layer 14B (barrier layer forming step). When the supply amount of TMG at this time is set to TMG2 which is the same as the supply amount of TMG in the channel GaN layer formation process, the flow rate from the channel GaN can be achieved only by opening and closing the valve without changing the setting of the mass flow controller. Control of the TMG supply amount from the layer formation step to the barrier layer formation step is therefore preferable.

As described above, in the nitride semiconductor multilayer substrate 10A according to the first embodiment of the present invention, by changing the substrate temperature and furnace pressure to the substrate temperature of the electron supply layer 14 during the formation of the electron transit layer 13 and furnace pressure, the electron supply layer forming step can be performed continuously with the electron transit layer forming step without interruption between the electron transit layer forming step and the electron supply layer forming step. Accordingly, thermal decomposition of GaN on the upper surface of the electron transit layer 13 is suppressed, and unevenness of the upper surface (interface) of the electron transit layer 13 is less likely to occur. As a result, the surface roughness (for example, the arithmetic mean roughness Ra) of the nitride semiconductor laminated substrate 10A obtained by the atomic force microscope, that is, the surface roughness (for example, the arithmetic mean roughness Ra) of the upper surface of the barrier layer 14B obtained by the atomic force microscope Degree Ra) is 0.5nm or less in the scanning range of 1μm square.

In addition, by suppressing occurrence of unevenness on the upper surface (interface) of the electron transit layer 13 , the thickness of the extremely thin spacer layer 14A of, for example, 5 nm or less can be made uniform. Accordingly, the in-plane states of the electron transit layer 13 and the spacer layer 14A become uniform, thereby suppressing deterioration of the characteristics of the switching element SA such as a decrease in the mobility of electrons in the two-dimensional electron gas 15 .

In the first embodiment described above, the buffer layer 12 was formed on the upper surface of the substrate 11 , but the buffer layer may also be formed on the upper surface of the substrate 11 . That is, a buffer layer may be formed on the substrate 11 through another layer.

In the above-mentioned first embodiment, the electron supply layer 14 may have a potential barrier composed of In _J Al _L Ga _1-JL N (where 0<J+L≤1 and 0≤J<1, 0<L≤1). layer instead of the barrier layer 14B composed of AlZGa1 _-ZN (where 0< _Z <1).

[the second embodiment]

Next, a nitride semiconductor multilayer substrate and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings.

3 is a schematic cross-sectional view showing the structure of a switching element SB using a nitride semiconductor multilayer substrate 10B according to a second embodiment of the present invention. 4 is a timing chart showing changes in the substrate temperature, furnace pressure, and supply amount of source gases in the electron transit layer forming step and the electron supply layer forming step of the nitride semiconductor multilayer substrate 10B. In addition, FIGS. 3 and 4 are diagrams showing the structure and manufacturing method of the nitride semiconductor laminated substrate 10B according to the second embodiment of the present invention by the same method as the method shown in FIGS. 1 and 2 of the first embodiment described above. . In addition, in the following description of the nitride semiconductor multilayer substrate 10B, overlapping descriptions of structural parts that are the same as those of the above-mentioned first embodiment may be omitted in some cases.

As shown in FIG. 3 , a nitride semiconductor stacked substrate 10B according to the second embodiment of the present invention includes: a substrate 11 ; a buffer layer 12 formed on the upper surface of the substrate 11 ; The electron transit layer 213; and the electron supply layer 14 formed on the upper surface of the electron transit layer 213.

In addition, the switching element SB described above includes a nitride semiconductor stacked substrate 10B, a source electrode 21 , a drain electrode 22 , and a gate electrode 23 .

The aforementioned source electrode 21 , drain electrode 22 and gate electrode 23 are formed on the upper surface of the electron supply layer 14 . In addition, the gate electrode 23 is arranged between the source electrode 21 and the drain electrode 22 .

In addition, the above-mentioned nitride semiconductor laminated substrate 10B is different from the nitride semiconductor laminated substrate of the above-mentioned first embodiment in that the electron transit layer 213 is constituted by the base GaN layer 13A, the slope GaN layer 13B, and the channel GaN layer 13C. Bottom 10A is different. The formation conditions of the base GaN layer 13A, the slope GaN layer 13B, and the channel GaN layer 13C are different from each other. In addition, the bandgap of the spacer layer 14A is larger than that of any one of the base GaN layer 13A, the sloped GaN layer 13B, and the channel GaN layer 13C. In addition, the bandgap of the barrier layer 14B is also larger than that of any of the base GaN layer 13A, the sloped GaN layer 13B, and the channel GaN layer 13C. That is, the electron supply layer 14 has a larger bandgap than the electron transit layer 213 . In addition, the gradient GaN layer 13B is an example of a sixth nitride semiconductor layer.

The sloped GaN layer 13B can be formed by continuously supplying TMG and NH ₃ to the reaction furnace in the step of changing the formation conditions from the base GaN layer formation step to the channel GaN formation step in the first embodiment. Floor.

Hereinafter, a method for forming the electron transit layer 213 and the electron supply layer 14 of the above-mentioned nitride semiconductor multilayer substrate 10B will be specifically described with reference to FIG. 4 .

As shown in FIG. 4 , first, the underlying GaN layer 13A is formed on the buffer layer 12 by the same formation method as that of the underlying GaN layer 13A in the first embodiment (the underlying GaN layer forming step).

When the formation of the above-described base GaN layer 13A is completed, the substrate temperature and the like are shifted to the substrate temperature and the like for forming the channel GaN layer 13C. At this time, the substrate temperature changes from T1 to T2, the furnace pressure changes from P1 to P2, the supply of TMG changes from TMG1 to TMG2, and the supply of NH ₃ changes slowly from NH ₃ 1 to NH ₃ 2 over a certain period of time. During this transition, the supply of TMG and NH ₃ into the reaction furnace is continued, whereby the sloped GaN layer 13B is formed (the sloped GaN layer forming step). Here, in the vicinity of the interface between base GaN layer 13A and sloped GaN layer 13B, the carbon concentration of sloped GaN layer 13B is substantially equal to the carbon concentration of base GaN layer 13A. In addition, in the vicinity of the interface between the channel GaN layer 13C and the sloped GaN layer 13B, the carbon concentration of the sloped GaN layer 13B is substantially equal to the carbon concentration of the channel GaN layer 13C. In addition, the carbon concentration of the sloped GaN layer 13B gradually increases as proceeding from the lower side of the sloped GaN layer 13B to the upper side of the sloped GaN layer 13B.

When the above-mentioned formation of the sloped GaN layer 13B is completed, the supply amount of TMG is maintained at TMG2, the supply amount of _NH3 is maintained at _NH32 , the substrate temperature is maintained at T2, and the furnace pressure is maintained at P2. , forming the channel GAN layer 13C (channel GaN layer forming step). Here, the carbon concentration of the channel GaN layer 13C tends to become larger than that of the base GaN layer 13A due to the influence of lowering the furnace pressure from P1 to P2.

When the formation of the channel GaN layer 13C is completed, the supply of TMG is stopped and the supply of TMA is started to form the spacer layer 14A in the same manner as the method for forming the spacer layer 14A in the first embodiment (spacer layer forming step). At the end of the formation of the channel GaN layer 13C, the substrate temperature is T2 and the furnace pressure is P2. The substrate temperature T2 and the furnace pressure P2 are suitable for the formation of the spacer layer 14A and the barrier layer 14B. Therefore, the spacer layer 14A is formed continuously without interruption after the formation of the channel GaN layer 13C.

When the formation of the spacer layer 14A is completed, the supply of TMG is restarted to form the barrier layer 14B in the same manner as the method for forming the barrier layer 14B in the first embodiment (barrier layer forming step). When the supply amount of TMG at this time is set to TMG2 which is the same as the supply amount of TMG in the channel GaN layer formation process, the flow rate from the channel GaN can be achieved only by opening and closing the valve without changing the setting of the mass flow controller. Control of the TMG supply amount from the layer formation step to the barrier layer formation step is therefore preferable.

As described above, in the nitride semiconductor multilayer substrate 10B according to the second embodiment of the present invention, as in the above-mentioned first embodiment, by changing the substrate temperature and the pressure in the furnace during the formation of the electron transit layer 213 to The substrate temperature and furnace pressure of the electron supply layer 14 allow the electron supply layer forming step to be performed continuously with the electron transit layer forming step without interruption between the electron transit layer forming step and the electron supply layer forming step. Accordingly, thermal decomposition of GaN on the upper surface of the electron transit layer 13 is suppressed, and unevenness of the upper surface (interface) of the electron transit layer 13 is less likely to occur. As a result, the surface roughness (for example, the arithmetic mean roughness Ra) of the nitride semiconductor laminated substrate 10A obtained by the atomic force microscope, that is, the surface roughness (for example, the arithmetic mean roughness Ra) of the upper surface of the barrier layer 14B obtained by the atomic force microscope Degree Ra) is 0.5nm or less in the scanning range of 1μm square.

In addition, by suppressing occurrence of unevenness on the upper surface (interface) of the electron transit layer 213 , the thickness of the extremely thin spacer layer 14A of, for example, 5 nm or less can be made uniform. Thereby, the states of the electron transit layer 213 and the spacer layer 14A in the in-plane direction become uniform, and thus it is possible to suppress the occurrence of deterioration in the characteristics of the switching element SB, such as a decrease in the mobility of electrons.

Furthermore, by forming the inclined GaN layer 13B between the base GaN layer 13A and the channel GaN layer 13C, it is possible to suppress irregularities inside the electron transit layer 213 . Therefore, with regard to crystallinity and defects, adverse effects of the electron transit layer 213 on the electron supply layer 14 can be reduced.

In addition, in the above-mentioned gradient GaN layer formation process, the substrate temperature, furnace pressure, and source gas supply rate are gradually changed, so the overshoot and undershoot of the substrate temperature, furnace pressure, and source gas supply rate occurrence is suppressed.

[the third embodiment]

Next, a nitride semiconductor multilayer substrate and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings.

5 is a schematic cross-sectional view showing the structure of a switching element SC using a nitride semiconductor multilayer substrate 10C according to a third embodiment of the present invention. 6 is a timing chart showing changes in the substrate temperature, furnace pressure, and supply amount of source gases in the electron transit layer forming step and the electron supply layer forming step of the nitride semiconductor multilayer substrate 10C. In addition, FIGS. 5 and 6 are diagrams showing the structure and manufacturing method of a nitride semiconductor laminated substrate 10C according to a third embodiment of the present invention in the same manner as those shown in FIGS. 1 and 2 of the first embodiment described above. . In addition, in the following description of the nitride semiconductor multilayer substrate 10C, overlapping descriptions of structural parts that are the same as those of the above-mentioned first embodiment may be omitted in some cases.

As shown in FIG. 5 , a nitride semiconductor stacked substrate 10C according to the third embodiment of the present invention has: a substrate 11 ; a buffer layer 12 formed on the upper surface of the substrate 11 ; The electron transit layer 13; and the barrier layer 14B formed on the upper surface of the electron transit layer 13. In addition, the lower surface of the barrier layer 14B is in contact with the upper surface of the electron transit layer 13 , and no other layer exists between the electron transit layer 13 and the barrier layer 14B. In addition, the barrier layer 14B is an example of a third nitride semiconductor layer.

Furthermore, the above-mentioned switching element SC has a nitride semiconductor multilayer substrate 10C, a source electrode 21 , a drain electrode 22 , and a gate electrode 23 .

The aforementioned source electrode 21 , drain electrode 22 , and gate electrode 23 are formed on the upper surface of the barrier layer 14B. In addition, the gate electrode 23 is arranged between the source electrode 21 and the drain electrode 22 .

In addition, the above-mentioned nitride semiconductor laminated substrate 10C is different from the point that the base GaN layer 13A, the sloped GaN layer 13B, and the channel GaN layer 13C constitute the electron transit layer 213 and that only the barrier layer 14B constitutes the electron supply layer. The nitride semiconductor multilayer substrate 10A of the above-mentioned first embodiment is different.

Hereinafter, a method for forming the electron transit layer 213 and the electron supply layer 14 of the above-mentioned nitride semiconductor multilayer substrate 10B will be specifically described with reference to FIG. 5 .

As shown in FIG. 6 , first, an underlying GaN layer 13A is formed on the buffer layer 12 by the same formation method as the formation method of the underlying GaN layer 13A in the above-mentioned second embodiment (the underlying GaN layer forming step).

When the formation of the above-described base GaN layer 13A is completed, the substrate temperature and the like are shifted to the substrate temperature and the like for forming the channel GaN layer 13C. At this time, the substrate temperature changes from T1 to T2, the furnace pressure changes from P1 to P2, the supply rate of TMG changes from _TMG1 to TMG2, and the supply rate of _NH3 changes slowly from NH31 to _NH32 over a certain period of time. During this transition, the supply of TMG and NH ₃ into the reaction furnace is continued, whereby the sloped GaN layer 13B is formed (the sloped GaN layer forming step). Here, in the vicinity of the interface between base GaN layer 13A and sloped GaN layer 13B, the carbon concentration of sloped GaN layer 13B is substantially equal to the carbon concentration of base GaN layer 13A. In addition, in the vicinity of the interface between the channel GaN layer 13C and the sloped GaN layer 13B, the carbon concentration of the sloped GaN layer 13B is substantially equal to the carbon concentration of the channel GaN layer 13C. In addition, the carbon concentration of the sloped GaN layer 13B gradually increases as proceeding from the lower side of the sloped GaN layer 13B to the upper side of the sloped GaN layer 13B.

When the above-mentioned formation of the sloped GaN layer 13B is completed, the supply amount of TMG is maintained at TMG2, the supply amount of _NH3 is maintained at _NH32 , the substrate temperature is maintained at T2, and the furnace pressure is maintained at P2. , forming the channel GAN layer 13C (channel GaN layer forming step). Here, the carbon concentration of the channel GaN layer 13C tends to become larger than that of the base GaN layer 13A due to the influence of lowering the furnace pressure from P1 to P2.

When the formation of the above-mentioned channel GaN layer 13C is completed, the supply amount of TMG is maintained at TMG2, the supply amount of _NH3 is maintained at _NH32 , the substrate temperature is maintained at T2, and the furnace pressure is maintained at P2. Simultaneously, the supply of TMA which is a material of Al is started, whereby the barrier layer 14B which is an electron supply layer is formed (barrier layer forming process). When the supply amount of TMG at this time is set to TMG2 which is the same as the supply amount of TMG in the channel GaN layer formation process, the flow rate from the channel GaN can be achieved only by opening and closing the valve without changing the setting of the mass flow controller. Control of the TMG supply amount from the layer formation step to the barrier layer formation step is therefore preferable.

As described above, in the nitride semiconductor multilayer substrate 10C according to the second embodiment of the present invention, as in the above-mentioned first embodiment, by changing the substrate temperature and the pressure in the furnace during the formation of the electron transit layer 213 to The substrate temperature and furnace pressure of the electron supply layer 14 allow the electron supply layer forming step to be performed continuously with the electron transit layer forming step without interruption between the electron transit layer forming step and the electron supply layer forming step. Accordingly, thermal decomposition of GaN on the upper surface of the electron transit layer 13 is suppressed, and unevenness of the upper surface (interface) of the electron transit layer 13 is less likely to occur. As a result, the surface roughness (for example, the arithmetic mean roughness Ra) of the nitride semiconductor laminated substrate 10A obtained by the atomic force microscope, that is, the surface roughness (for example, the arithmetic mean roughness Ra) of the upper surface of the barrier layer 14B obtained by the atomic force microscope Degree Ra) is 0.5nm or less in the scanning range of 1μm square.

In addition, by suppressing occurrence of unevenness on the upper surface (interface) of the electron transit layer 213 , the thickness of the extremely thin spacer layer 14A of, for example, 5 nm or less can be made uniform. Thereby, the states of the electron transit layer 213 and the spacer layer 14A in the in-plane direction become uniform, and thus it is possible to suppress the occurrence of deterioration in the characteristics of the switching element SB, such as a decrease in the mobility of electrons.

Further, by forming the sloped GaN layer 13B between the above-mentioned base GaN layer 13A and the channel GaN layer 13C, the unevenness inside the electron transit layer 213 is suppressed. Therefore, with regard to crystallinity and defects, adverse effects of the electron transit layer 213 on the electron supply layer 14 can be reduced.

In addition, in the above-mentioned gradient GaN layer formation process, the substrate temperature, furnace pressure, and source gas supply amount are gradually changed, so the overshoot and undershoot of the substrate temperature, furnace pressure, and source gas supply amount occurrence is suppressed.

Furthermore, by suppressing the unevenness of the upper surface of the electron transit layer 213 described above, the mobility of electrons in the two-dimensional electron gas layer 1008 is improved. Therefore, even if the nitride semiconductor multilayer substrate 10C does not have the spacer layer 14A of the first embodiment described above, the on-resistance of the switching element SC is sufficiently reduced.

If the spacer layer 14A is formed between the electron transit layer 213 and the barrier layer 14B, the lattice mismatch between the electron transit layer 213 and the spacer layer 14A becomes large, and as a result, the piezoelectric effect becomes large, This can adversely affect long-term reliability. Therefore, it is significant that the spacer layer 14A that poses a reliability risk is unnecessary.

Although specific embodiments of the present invention have been described, the present invention is not limited to the first to third embodiments described above, and various modifications can be made within the scope of the present invention. For example, an aspect obtained by appropriately combining the contents described in the above-mentioned first to third embodiments can be considered as one embodiment of the present invention.

That is, the present invention and the embodiments are summarized as follows.

The method for manufacturing a nitride semiconductor laminate of the present invention is characterized by comprising:

a first nitride semiconductor layer forming step of forming a first nitride semiconductor layer 12 above the substrate 11 in a reaction furnace;

a second nitride semiconductor layer forming step of forming the second nitride semiconductor layer 13, 213 above the first nitride semiconductor layer 12; and

A third nitride semiconductor layer forming step of forming a third nitride semiconductor layer 14 , 14B having a larger bandgap than that of the second nitride semiconductor layer 13 , 213 on the upper surface of the second nitride semiconductor layer 13 , 213 ,

There is no interruption between the second nitride semiconductor layer forming step and the third nitride semiconductor layer forming step, and the third nitride semiconductor layer forming step and the second nitride semiconductor layer forming step are performed continuously.

According to the above technical solution, there is no interruption between the step of forming the second nitride semiconductor layer and the step of forming the third nitride semiconductor layer, and the step of forming the third nitride semiconductor layer and the step of forming the second nitride semiconductor layer are continuously performed. Therefore, it is possible to suppress occurrence of unevenness on the upper surface of the second nitride semiconductor.

In the method of manufacturing a nitride semiconductor laminate according to one embodiment,

The above-mentioned second nitride semiconductor layer forming step has:

a fourth nitride semiconductor layer forming step of forming the fourth nitride semiconductor layer 13A; and

a fifth nitride semiconductor layer forming step of forming a fifth nitride semiconductor layer 13C above the fourth nitride semiconductor layer 13A,

The substrate temperature in the step of forming the fifth nitride semiconductor layer is higher than the temperature of the substrate in the step of forming the fourth nitride semiconductor layer,

The furnace pressure in the fifth nitride semiconductor layer forming step is lower than the furnace pressure in the fourth nitride semiconductor layer forming step.

According to the above embodiment, in the second half of the second nitride semiconductor layer forming step, the substrate temperature is relatively high and the furnace pressure is relatively low. Therefore, even in the case where the above-mentioned third nitride semiconductor layers 14, 14B are formed at a high substrate temperature and a low furnace pressure, the third nitride semiconductor layer can be formed continuously and satisfactorily. Compound semiconductor layer formation process.

In the method of manufacturing a nitride semiconductor laminate according to one embodiment,

The second nitride semiconductor layer forming step includes a sixth nitride semiconductor layer forming step of forming a sixth nitride semiconductor layer 13B between the fourth nitride semiconductor layer 13A and the fifth nitride semiconductor layer 13C,

The substrate temperature in the sixth nitride semiconductor layer forming step is gradually changed from the same substrate temperature as in the fourth nitride semiconductor layer forming step to the same substrate temperature as in the fifth nitride semiconductor layer forming step. temperature,

The pressure in the furnace in the sixth nitride semiconductor layer forming step is gradually changed from the same pressure in the furnace in the fourth nitride semiconductor layer forming step to the same furnace pressure in the fifth nitride semiconductor layer forming step as described above. pressure.

According to the above-described embodiment, the substrate temperature and furnace pressure in the sixth nitride semiconductor layer forming step are gradually changed, so defects in the second nitride semiconductor layer 13, 213 can be reduced, and the second nitride semiconductor layer can be improved. Crystallinity of layer 13,213.

In addition, since the substrate temperature and furnace pressure in the sixth nitride semiconductor layer forming step are gradually changed, at the start of the fifth nitride semiconductor layer forming step, overshoot and drop in substrate temperature and furnace temperature can be suppressed. Chong happens.

In the method of manufacturing a nitride semiconductor laminate according to one embodiment,

The second nitride semiconductor layer 13, 213 is made of GaN,

The third nitride semiconductor layer 14B is composed of AlxGa1 _{- xN} (0<x<1).

According to the above embodiment, since the lattice mismatch between the second nitride semiconductor layer 13 and 213 and the third nitride semiconductor layer 14B is reduced, long-term reliability can be improved.

The nitride semiconductor laminate of the present invention is characterized by comprising:

Substrate 11;

a first nitride semiconductor layer 12 formed on the substrate 11;

the second nitride semiconductor layer 13, 213 formed above the first nitride semiconductor layer 12; and

The third nitride semiconductor layer 14, 14B having a larger band gap than the second nitride semiconductor layer 13, 213 is formed on the upper surface of the second nitride semiconductor layer 13, 213,

The second nitride semiconductor layer 13, 213 and the third nitride semiconductor layer 14, 14B are formed between the formation of the second nitride semiconductor layer 13, 213 and the formation of the third nitride semiconductor layer 14, 14B. The formation of the third nitride semiconductor layer 14 , 14B and the formation of the second nitride semiconductor layer 13 , 213 are performed continuously without interruption.

According to the above-mentioned technical solution, the formation of the second nitride semiconductor layer 13, 213 and the above-mentioned third nitride semiconductor layer 14, 14B are based on the formation of the above-mentioned second nitride semiconductor layer 13, 213 and the formation of the third nitride semiconductor layer 14, 14B. The formation is not interrupted, and the formation of the third nitride semiconductor layer 14, 14B and the formation of the second nitride semiconductor layer 13, 213 are continuously formed, so that the formation of the second nitride semiconductor layer can be suppressed. The surface is uneven.

In the nitride semiconductor stacked body of one embodiment,

The above-mentioned second nitride semiconductor layer 13, 213 has:

fourth nitride semiconductor layer 13A having a carbon concentration of less than 5×10 ¹⁶ /cm ³ ; and

A fifth nitride semiconductor layer 13C having a carbon concentration of 5×10 ¹⁶ /cm ³ to less than 1×10 ¹⁸ /cm ³ is formed on the fourth nitride semiconductor layer.

According to the above embodiment,

The carbon concentration of the fourth nitride semiconductor layer 13A is less than 5×10 ¹⁶ /cm ³ , thereby preventing dislocations and nanotubes occurring at the interface between the first nitride semiconductor layer 12 and the fourth nitride semiconductor layer 13A. etc. have adverse effects on device characteristics.

In addition, the carbon concentration of the fifth nitride semiconductor layer 13C is not less than 5×10 ¹⁶ /cm ³ and less than 1×10 ¹⁸ /cm ³ , thereby preventing the fifth nitride semiconductor layer 13C from colliding with the third nitride semiconductor layer. The flatness of the interface of the layers 14, 14B is reduced.

A nitride semiconductor laminate according to one embodiment includes a sixth nitride semiconductor layer 13B formed between the fourth nitride semiconductor layer 13A and the fifth nitride semiconductor layer 13C,

The carbon concentration of the sixth nitride semiconductor layer 13B is substantially equal to the carbon concentration of the fourth nitride semiconductor layer 13A in the vicinity of the interface between the fourth nitride semiconductor layer 13A and the sixth nitride semiconductor layer 13B. The vicinity of the interface between the fifth nitride semiconductor layer 13C and the sixth nitride semiconductor layer 13B has approximately the same carbon concentration as that of the fifth nitride semiconductor layer 13C, and gradually increases from the lower side of the sixth nitride semiconductor layer 13B. The amount gradually increases toward the upper side of the sixth nitride semiconductor layer 13B.

According to the above embodiment, the carbon concentration is gradually increased from the carbon concentration substantially equal to that of the fourth nitride semiconductor layer 13A to the carbon concentration substantially equal to that of the fifth nitride semiconductor layer 13C. Therefore, it is possible to gradually change from the above-mentioned formation conditions of the fourth nitride semiconductor layer 13A to the formation conditions of the fifth nitride semiconductor layer 13C. As a result, defects in the second nitride semiconductor layer 13, 213 can be reduced, and the crystallinity of the second nitride semiconductor layer 13, 213 can be improved.

In addition, since the above-mentioned formation conditions of the fourth nitride semiconductor layer 13A can be gradually changed to the formation conditions of the fifth nitride semiconductor layer 13C, the substrate temperature can be suppressed when the formation of the fifth nitride semiconductor layer 13C is started. And the occurrence of overshoot and undershoot of the furnace temperature.

In the nitride semiconductor stacked body of one embodiment,

The second nitride semiconductor layer 13, 213 is made of GaN,

The third nitride semiconductor layer 14B is composed of AlxGa1 _{- xN} (0<x<1).

According to the above embodiment, since the lattice mismatch between the second nitride semiconductor layer 13 and 213 and the third nitride semiconductor layer 14B is reduced, long-term reliability can be improved.

In the nitride semiconductor stacked body of one embodiment,

On the upper surfaces of the third nitride semiconductor layers 14 and 14B, the surface roughness obtained by an atomic force microscope is 0.5 nm or less in a scanning range of 1 μm square.

According to the above embodiment, when the source electrode 21, the drain electrode 22, and the gate electrode 23 are formed on the upper surface of the third nitride semiconductor layer 14, 14B, for example, the source electrode 21, the drain electrode 22 can be Adhesion with the gate electrode 23 to the upper surface of the third nitride semiconductor layer 14 , 14B is improved.

Symbol Description

10A, 10B, 10C Nitride semiconductor laminated substrate

11 Substrate

12 buffer layer

13, 213 Electron transit layer

13A base GaN layer

13B Tilted GaN layer

13C channel GaN layer

14 electron supply layer

14A spacer layer

14B barrier layer

15 Two-dimensional electron gas

21 Source electrode

22 Drain electrode

23 Grid electrode

SA, SB, SC switching elements

Claims (9)

1. A method for manufacturing a nitride semiconductor laminate, comprising: a first nitride semiconductor layer forming step of forming a first nitride semiconductor layer (12) above a substrate (11) in a reaction furnace; a second nitride semiconductor layer forming step of forming a second nitride semiconductor layer (13, 213) above the first nitride semiconductor layer (12); and forming a third nitride semiconductor layer (14, 14B) having a larger band gap than that of the second nitride semiconductor layer (13, 213) on an upper surface of the second nitride semiconductor layer (13, 213); a third nitride semiconductor layer forming step, There is no interruption between the step of forming the second nitride semiconductor layer and the step of forming the third nitride semiconductor layer, and the step of forming the third nitride semiconductor layer is continuous with the step of forming the second nitride semiconductor layer. be implemented. 2. The method of manufacturing a nitride semiconductor laminate according to claim 1, wherein: The step of forming the second nitride semiconductor layer includes: a fourth nitride semiconductor layer forming step of forming a fourth nitride semiconductor layer (13A); and a fifth nitride semiconductor layer forming step of forming a fifth nitride semiconductor layer (13C) above the fourth nitride semiconductor layer (13A), The substrate temperature in the fifth nitride semiconductor layer forming step is higher than the substrate temperature in the fourth nitride semiconductor layer forming step, The furnace pressure in the fifth nitride semiconductor layer forming step is lower than the furnace pressure in the fourth nitride semiconductor layer forming step. 3. The method of manufacturing a nitride semiconductor laminate according to claim 2, wherein: The second nitride semiconductor layer forming step includes a sixth step of forming a sixth nitride semiconductor layer (13B) between the fourth nitride semiconductor layer (13A) and the fifth nitride semiconductor layer (13C). Nitride semiconductor layer forming process, The substrate temperature in the sixth nitride semiconductor layer forming step is gradually changed from the same temperature as the substrate temperature in the fourth nitride semiconductor layer forming step to the substrate temperature in the fifth nitride semiconductor layer forming step. the same temperature as the bottom temperature, The pressure in the furnace in the sixth nitride semiconductor layer forming step is gradually changed from the same pressure in the furnace in the fourth nitride semiconductor layer forming step to the pressure in the furnace in the fifth nitride semiconductor layer forming step. same internal pressure. 4. The method of manufacturing a nitride semiconductor laminate according to any one of claims 1 to 3, characterized in that: The second nitride semiconductor layer (13, 213) is made of GaN, The third nitride semiconductor layer (14B) is made of AlxGa1 _{-xN ,} where 0<x<1. 5. A nitride semiconductor laminate, characterized in that it comprises: Substrate (11); a first nitride semiconductor layer (12) formed above the substrate (11); a second nitride semiconductor layer (13, 213) formed above the first nitride semiconductor layer (12); and A third nitride semiconductor layer (14, 14B) having a larger band gap than that of the second nitride semiconductor layer (13, 213) is formed on the upper surface of the second nitride semiconductor layer (13, 213). , The second nitride semiconductor layer (13, 213) and the third nitride semiconductor layer (14, 14B) are formed by forming the second nitride semiconductor layer (13, 213) in conjunction with the third nitride semiconductor layer (14, 14B). The formation of the compound semiconductor layer (14, 14B) is not interrupted, and the formation of the third nitride semiconductor layer (14, 14B) and the formation of the second nitride semiconductor layer (13, 213) are continuously carried out. The way of implementation is formed. 6. The nitride semiconductor stacked body according to claim 5, characterized in that: The second nitride semiconductor layer (13, 213) has: a fourth nitride semiconductor layer (13A) having a carbon concentration of less than 5×10 ¹⁶ /cm ³ ; and A fifth nitride semiconductor layer (13C) having a carbon concentration of not less than 5×10 ¹⁶ /cm ³ and less than 1×10 ¹⁸ /cm ³ is formed above the fourth nitride semiconductor layer (13A). 7. The nitride semiconductor stacked body according to claim 6, characterized in that: including a sixth nitride semiconductor layer (13B) formed between the fourth nitride semiconductor layer (13A) and the fifth nitride semiconductor layer (13C), The carbon concentration of the sixth nitride semiconductor layer (13B) is close to the interface between the fourth nitride semiconductor layer (13A) and the sixth nitride semiconductor layer (13B) and the fourth nitride semiconductor layer (13B). The carbon concentration of the layer (13A) is approximately the same, and in the vicinity of the interface between the fifth nitride semiconductor layer (13C) and the sixth nitride semiconductor layer (13B) and the fifth nitride semiconductor layer (13C) The carbon concentration is approximately equal and gradually increases from the lower side of the sixth nitride semiconductor layer (13B) to the upper side of the sixth nitride semiconductor layer (13B). 8. The nitride semiconductor stacked body according to any one of claims 5 to 7, characterized in that: The second nitride semiconductor layer (13, 213) is made of GaN, The third nitride semiconductor layer (14B) is made of AlxGa1 _{-xN ,} where 0<x<1. 9. The nitride semiconductor laminate according to any one of claims 5 to 8, characterized in that: On the upper surface of the third nitride semiconductor layer (14, 14B), the surface roughness obtained by an atomic force microscope is 0.5 nm or less in a scanning range of 1 μm square.