CN106684096B - A kind of array substrate - Google Patents

Abstract

A COG/FOG board, comprising a first flat layer arranged around the glass plate and a plurality of array substrates arranged in the center of the glass plate, the COG/FOG board includes: a top layer arranged sequentially on the glass plate from top to bottom A transparent electrode, a passivation layer, a second planar layer, a second metal layer, a grid insulating layer and a first metal layer. When the integrated circuit board or flexible circuit board is laminated after coating the anisotropic conductive adhesive on the array substrate area, due to the existence of the organic flat layer in the middle of the array substrate, the bonding effect between the top transparent electrode and the integrated circuit board or flexible circuit board Better, the contact conduction performance is more excellent. The uneven panel gap and poor display caused thereby can be avoided, and at the same time, the effect of binding and packaging the array substrate and the integrated circuit board or the flexible circuit board can be improved.

Description

An array substrate

technical field

The invention relates to the field of liquid crystal display screens, in particular to an array substrate.

Background technique

Due to the mature technology and low cost of LCD display technology, the advantages of high pixels can be realized, and it has a great market competitive advantage. The current LCD driving method adopts the signal input method of flexible circuit board (FPC) and integrated circuit (IC), and it is necessary to design corresponding COG board and FOG board on the glass substrate side to complete the integration of integrated circuit (IC) and flexible circuit board (IC). FPC) attachment and conduction, due to the presence of a thicker organic flat layer (generally 2um) in the process of the thin film transistor (TFT) side, in order to ensure the conduction performance, the traditional COG and FOG designs will use the entire The organic planar layer (PLN) in the area is all hollowed out, and the thin film transistors are respectively the first metal layer, the gate insulating layer (GI), the second metal layer (contacting the first metal layer through the hole for conduction), and the organic planar layer ( Fully hollowed out in all COG/FOG ranges), the insulating layer and the top transparent electrode conductive layer (contacting the metal layer through the hole conducts electricity, and directly laminating with the integrated circuit/flexible circuit board, using the anisotropic conductive adhesive film to contact and conduct electricity ).

The traditional COG (chip on glass) and FOG (FPC on glass) board design will hollow out the organic flat layer in the entire area, which will lead to the photoreactive type on the color filter (color filter, CF) side of the area. The top of the gap control material (PS) cannot be in direct contact with the film layer on the side of the thin film transistor (TFT), and cannot play a supporting role.

As shown in FIG. 1 and FIG. 2 , it is a plan view of the current array substrate design method, including multiple COG/FOG plates arranged in the center of the glass plate and an organic flat layer 3 arranged around the glass plate 1 .

The COG/FOG board 10 includes a first metal layer 7 , a gate insulating layer 2 , a second metal layer 6 , a passivation layer 4 , and a top transparent electrode 5 sequentially arranged on the glass board from top to bottom. The organic planar 3 is disposed on the gate insulating layer 2, and a passivation layer 4 is covered on the organic planar layer. Due to the large height difference between the array substrate 10 and the surrounding organic flat layer 3, the top of the photoreactive gap control material (PS) on the side of the color filter (color filter, CF) in the array substrate area cannot directly contact the thin film. The film layer on the side of the transistor (TFT) is in contact and cannot play a supporting role. This case is aimed at the problem that the gap control material (PS) cannot play an effective supporting role caused by the hollow design of the organic flat layer at the COG/FOG, and proposes a new array substrate design method to avoid uneven panel gaps and Bad display.

Contents of the invention

The purpose of this invention is to propose a new array substrate to solve the problem that the photoreactive gap control material (PS) cannot play an effective supporting role due to the hollow design of the organic flat layer at the COG and FOG, so as to avoid the resulting Uneven panel gap and poor display, while improving the bonding and packaging effect of the array substrate and integrated circuit/flexible circuit board.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions.

An array substrate, comprising a first planar layer arranged around the glass plate and a plurality of COG/FOG plates arranged in the center of the glass plate;

Each COG/FOG board includes: a top layer transparent electrode, a passivation layer, a second flat layer, a second metal layer, a grid insulating layer and a first metal layer are sequentially arranged on the glass board from top to bottom.

In the above array substrate, the second flat layer is arranged in the center of the first metal layer.

In the array substrate, the passivation layer completely covers the second flat layer and the first flat layer.

In the above-mentioned array substrate, the gate insulating layer disposed on the first metal layer is etched in an area around the inside of the first metal layer to form a groove whose bottom surface is the first metal layer.

The array substrate, wherein the second metal layer covers the gate insulating layer and the bottom surface is a groove of the first metal layer.

In the array substrate, the passivation layer does not cover the first planar layer and the second planar layer, but covers the second metal layer and the gate insulating layer respectively.

In the above-mentioned array substrate, the transparent electrodes on the top layer respectively cover the passivation layer and the second metal layer.

In the array substrate, the film thickness in the COG/FOG plate area is consistent with the height of the flat layer area around the panel.

In the array substrate, the size of the second flat layer is the size of the second metal layer.

This method has the following advantages: when the integrated circuit board or flexible circuit board is laminated after coating the anisotropic conductive adhesive (ACF) on the array substrate area, the top layer is transparent due to the existence of an organic flat layer in the middle of the COG/FOG board area The bonding effect between the electrode and the integrated circuit board or the flexible circuit board is better, and the contact conduction performance is better. The uneven panel gap and poor display caused thereby can be avoided, and at the same time, the effect of binding and packaging the array substrate and the integrated circuit board or the flexible circuit board can be improved.

Hollow out the flat layer on the periphery of the array substrate, use the conductive layer around the periphery to realize the contact and conduction between the COG/FOG board and the integrated circuit board or flexible circuit board, and keep the organic flat layer in the middle of the array substrate, so that the film in this area The thickness and height are consistent with other areas of the panel, thereby reducing the height difference between the array substrate and other areas, thereby reducing uneven panel gaps and improving display quality.

In addition, when the integrated circuit board or flexible circuit board is laminated after coating the heterosquare conductive adhesive on the COG/FOG plate area, due to the existence of the organic flat layer in the middle of the array substrate, the top transparent electrode on the top and the integrated circuit/flexible circuit The bonding effect of the board is better, and the contact conduction performance is more excellent.

Description of drawings

Hereinafter, the present invention will be described in more detail based on the embodiments with reference to the accompanying drawings. in:

FIG. 1 is a schematic plan view of a currently used array substrate.

FIG. 2 is a schematic cross-sectional view of a currently used array substrate.

FIG. 3 is a schematic plan view of the array substrate of the present invention.

FIG. 4 is a schematic cross-sectional view of the array substrate of the present invention.

In the figures, the same parts are given the same reference numerals. The drawings are not to scale.

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing.

The present invention relates to an array substrate. As shown in FIG. 3 , an array substrate includes a first flat layer 31 arranged around a glass plate 1 and a plurality of parallel COG/FOG plates 8 arranged in the center of the glass plate 1 .

As shown in FIG. 4 , the COG/FOG plate 8 includes: a top layer transparent electrode 5, a passivation layer 4, a second flat layer 32, and a second metal layer 6 arranged on the glass plate 1 in order from top to bottom. , a gate insulating layer 2 and a first metal layer 7 . Wherein, the second flat layer 32 is disposed at the center of the array substrate 8 . The passivation layer 4 completely covers the second flat layer 32 and the first flat layer 31 .

The gate insulating layer 2 disposed on the first metal layer 7 is etched in the area around the inside of the first metal layer 7 to form a groove whose bottom surface is the first metal layer 7 .

The second metal layer 6 covers the gate insulating layer 2 and the bottom surface is the groove of the first metal layer 7 . That is, the first metal layer and the second metal layer are in contact through the groove.

The parts of the passivation layer 4 not covering the first passivation layer 31 and the second passivation layer 32 cover the second metal layer 6 and the gate insulating layer 2 respectively.

The top transparent electrode 5 covers the passivation layer 4 and the second metal layer 6 respectively.

The height of the film thickness in the region of the COG/FOG plate is consistent with the height of the flat layer region around the panel.

The size of the second flat layer 32 is smaller than the size of the second metal layer 6 . Such setting can not only enable the second flat layer 32 to effectively support the integrated circuit board or flexible circuit board arranged on the top, but also ensure the conduction performance.

The array substrate also includes an integrated circuit board or a flexible circuit board arranged on the top layer, and the integrated circuit board or flexible circuit board is laminated after coating an anisotropic conductive glue on the array substrate area.

Hollow out the flat layer on the periphery of the array substrate, use the conductive layer around the periphery to realize the contact and conduction between the COG/FOG board and the integrated circuit board or flexible circuit board, and keep the organic flat layer in the middle of the array substrate, so that the film in this area The thickness and height are consistent with other areas of the panel, thereby reducing the height difference between the array substrate and other areas, thereby reducing uneven panel gaps and improving display quality.

In addition, when the integrated circuit board or flexible circuit board is pressed after being coated with anisotropic conductive adhesive in the array substrate area, due to the existence of the organic flat layer in the middle of the array substrate, the top transparent electrode on the top and the integrated circuit board or flexible circuit board The bonding effect is better, and the contact conduction performance is more excellent

While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for parts thereof without departing from the scope of the invention. In particular, as long as there is no structural conflict, the technical features mentioned in the various embodiments can be combined in any manner. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims (9)

1. An array substrate, characterized in that: comprising a first flat layer arranged around the glass plate and a plurality of COG/FOG plates arranged in the center of the glass plate; Each of the COG/FOG boards includes: a top-layer transparent electrode, a passivation layer, a second flat layer, a second metal layer, a grid insulating layer and a first metal layer are sequentially arranged on the glass board from top to bottom. 2. The array substrate according to claim 1, wherein the second flat layer is disposed in the center of the first metal layer. 3. The array substrate according to claim 1, wherein the passivation layer completely covers the first flat layer and the second flat layer. 4. The array substrate according to claim 1, wherein the gate insulating layer disposed on the first metal layer is etched in the area around the inside of the first metal layer to form a bottom surface of the first metal layer. Grooves in the metal layer. 5 . The array substrate according to claim 4 , wherein the second metal layer covers the gate insulating layer and the bottom surface is a groove of the first metal layer. 6 . The array substrate according to claim 3 , wherein the passivation layer does not cover parts of the first flat layer and the second flat layer, but covers the second metal layer and the gate insulating layer respectively. 7 . The array substrate according to claim 1 , wherein the top transparent electrode covers the passivation layer and the second metal layer respectively. 8 . The array substrate according to claim 1 , wherein the thickness and height of the film in the area of the COG/FOG plate are consistent with the height of the area around the glass plate where the first flat layer is located. 9. The array substrate according to claim 1, wherein an area of the second flat layer is smaller than an area of the second metal layer.