CN106684057B - 芯片封装结构及其制造方法 - Google Patents
芯片封装结构及其制造方法 Download PDFInfo
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Abstract
本发明实施例提供一种芯片封装结构,包括基板、封装于所述基板的上表面的多个芯片和多个分离器件、以及散热装置,所述散热装置包括层压设置的绝缘层和导热层,所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,用于将所述多个芯片及多个分立器件产生的热量传导至所述导热层和所述基板上,以通过所述导热层及所述基板将所述多个芯片及多个分立器件产生的热量散除。另,本发明实施例还提供一种芯片封装结构的制造方法。所述芯片封装结构通过设置所述散热装置,可以实现均匀、高效的系统级芯片封装散热。
Description
技术领域
本发明涉及芯片封装技术领域,尤其涉及一种芯片封装结构及其制造方法。
背景技术
随着芯片工艺节点的不断下降,芯片的集成度不断上升。小尺寸,高速率,高性能已成为电子器件发展的趋势。芯片中单位面积的晶体管数量越来越多,功率密度也随之不断提高,芯片的热管理变得越来越挑战。在系统级芯片封装(System-in-Package,SiP)结构中,多个异质芯片及分立器件被封装集成在一个小尺寸的系统中。由于不同芯片在不同工作状态下有不同的功耗,导致系统级封装结构容易出现热累积和散热不均等问题。目前,提高芯片散热能力的常用技术是在芯片的无源面通过热界面材料(Thermal InterfaceMaterials,TIM)添加散热装置,如金属散热片,热电制冷片(Thermo Electric Cooler,TEC)等,最终将芯片产生的热量传递到空气。然而,这种散热方式对于系统级芯片封装时,无法实现多个异质芯片及分立器件的快速均匀散热,不利于提升系统级芯片封装的散热效率。
发明内容
本发明实施例提供一种芯片封装结构及其制造方法,以及一种应用所述系统级芯片封装结构的终端,以实现系统级芯片封装内多个芯片及分立器件的快速均匀散热,提升系统级芯片封装结构及终端的散热效率。
本发明实施例第一方面提供一种芯片封装结构,包括基板、封装于所述基板的上表面的多个芯片和多个分离器件、以及散热装置,所述散热装置包括层压设置的绝缘层和导热层,所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,用于将所述多个芯片及多个分立器件产生的热量传导至所述导热层和所述基板上,以通过所述导热层及所述基板将所述多个芯片及多个分立器件产生的热量散除。
所述芯片封装结构通过设置所述包括层压设置的绝缘层和导热层的散热装置,并将所述绝缘层全包覆所述芯片封装的多个芯片、多个分立器件及基板的上表面,从而可以有效增加散热面积,实现对所述多个芯片及个分立器件的均匀快速散热。
在一种实施方式中,所述层压设置的绝缘层和导热层在垂直于所述基板的上表面的投影方向上重叠。
在一种实施方式中,所述绝缘层还用于将所述多个芯片及多个分立器件产生的热量传导至空气中,以直接通过所述绝缘层将所述多个芯片及多个分立器件产生的热量散除。
由于所述绝缘层在靠近所述基板的边缘位置直接与空气接触,从而还可以通过所述绝缘层直接将所述多个芯片及多个分立器件产生的热量散除,以进一步提升散热速度。
在一种实施方式中,所述绝缘层由可成形性的绝缘材料制成。
通过采用可成形性的材料制成所述绝缘层,从而在将所述散热装置固化到系统级芯片封装之上时,可以通过热压等方式使得所述绝缘层与所述多个芯片、多个分立器件的外表面及所述基板的上表面紧密贴合,从而有效增加散热面积,实现对所述多个芯片及多个分立器件的快速散热。
在一种实施方式中,所述导热层由导热材料和可成形性的绝缘材料制成。
在一种实施方式中,所述导热材料均匀掺杂于所述可成形性的绝缘材料中。
通过在所述可成形性的绝缘材料中均匀掺杂所述导热材料,从而形成所述导热层,一方面可以借助所述绝缘材料的可成形性来使得所述导热层也具有良好的可成形性,另一方面通过所述均匀掺杂的导热材料来保证所述导热层的每一个区域具有均匀的导热率,从而实现对所述多个芯片及多个分立器件的均匀散热。
在一种实施方式中,所述导热材料包括石墨烯、石墨片、氮化硼片中的一种或多种。
在一种实施方式中,所述可成形性的绝缘材料包括环氧树脂或聚酰亚胺中的至少一项。
通过将石墨烯、石墨片或氮化硼片按照不同的比例均匀掺杂到环氧树脂或聚酰亚胺中制成所述导热层,以方便可以保证良好的导热效率,提升散热速度,另一方面可以保证所述导热层具有良好的可成形性,从而在将所述散热装置固化到系统级芯片封装之上时,可以通过热压等方式使得所述导热层跟随所述多个芯片、多个分立器件的外表面及所述基板的上表面的外形的变化而变化,有利于进一步增加散热面积,提升整个系统级芯片封装的散热效率。
在一种实施方式中,所述芯片包括引线键合芯片或倒装芯片中的任一项。
在一种实施方式中,所述芯片封装结构还包括多个焊球,所述多个焊球呈阵列设置于所述基板的下表面。
本发明实施例第二方面提供一种芯片封装结构的制造方法,包括:
提供一基板,并在基板的上表面封装多个芯片及多个分离器件;
提供一散热装置,所述散热装置包括绝缘层和导热层;
将所述散热装置层压设置于所述基板的上表面,并使所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面。
所述芯片封装结构的制造方法通过将所述散热装置层压设置于所述基板的上表面,并使所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,从而可以有效增加散热面积,实现对所述多个芯片及个分立器件的均匀快速散热。
在一种实施方式中,所述将所述散热装置层压设置于所述基板的上表面,并使所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,包括:
对所述绝缘层加热到第一温度,并以第一压力持续压合第一时间至完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面;
对所述绝缘层热到第二温度并持续第二时间,以对所述绝缘层进行固化;
对所述导热层加热到第三温度,并以第二压力持续压合第三时间至所述绝缘层的上表面;
对所述导热层加热到第四温度并持续第四时间,以对所述导热层进行固化。
在一种实施方式中,所述将所述散热装置层压设置于所述基板的上表面,并使所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,包括:
将所述导热层压合于所述绝缘层上,形成层压设置的绝缘层和导热层作为所述散热装置;
将所述绝缘层朝向所述基板的上表面,对所述散热装置加热到第一温度,并以第一压力持续压合第一时间至所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面;
对所述散热装置加热到第二温度并持续第二时间,以对所述散热装置进行固化。
在一种实施方式中,所述第一温度和所述第三温度均为150度,所述第二温度和所述第四温度均为175度,所述第一压力和所述第二压力均为7-10Kgf/cm2,所述第一时间和所述第三时间均为30秒,所述第二时间和所述第四时间均为1小时。
本发明实施例第四方面提供一种终端,包括芯片封装结构和主板,所述主板上设置有焊盘,所述芯片封装结构焊接于所述焊盘上,所述芯片封装结构,包括基板、封装于所述基板的上表面的多个芯片和多个分离器件、以及散热装置,所述散热装置包括层压设置的绝缘层和导热层,所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,用于将所述多个芯片及多个分立器件产生的热量传导至所述导热层和所述基板上,以通过所述导热层及所述基板将所述多个芯片及多个分立器件产生的热量散除。
所述芯片封装结构通过在所述基板的上表面设置所述包括绝缘层和导热层的散热装置,且通过热压工艺使得所述绝缘层与所述多个芯片、多个分立器件的外表面及所述基板的上表面紧密贴合,从而可以有效增加散热面积,提升散热均匀性,实现对所述多个芯片及多个分立器件的快速高效散热,从而提升所述终端的散热效率。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对本发明实施例描述中所需要使用的附图作简单地介绍。
图1是本发明实施例提供的系统级芯片封装结构的剖面示意图;
图2是本发明实施例提供的系统级芯片封装结构的拆解示意图;
图3是本发明实施例提供的系统级芯片封装结构的散热路径示意图;
图4是应用本发明实施例提供的系统级芯片封装结构的终端的结构示意图;
图5是本发明实施例提供的系统级芯片封装结构的制造方法的流程示意图;
图6是本发明实施例提供的系统级芯片封装结构的制造方法的另一流程示意图。
具体实施方式
下面将结合附图,对本发明的实施例进行描述。
请参阅图1,在本发明一个实施例中,提供一种系统级芯片封装结构10,包括基板104,所述基板104的上表面封装有多个芯片101、102及多个分立器件103,所述基板104的下表面设置有多个焊球105。在本实施例中,所述芯片101以倒装形式(Flip Chip)封装于所述基板104的上表面,所述芯片102以引线键合形式(Wire bonding)封装于所述基板104的上表面,所述多个分立器件103以表面贴装的形式封装于所述基板104的上表面。可以理解,当所述系统级芯片封装结构10工作时,所述多个芯片101、102及多个分立器件103为发热源。为使所述系统级芯片封装结构10的工作温度处于额定的温度范围之内,需要将所述多个芯片101、102及多个分立器件103产生的热量均匀快速地散除,从而保证所述系统级芯片封装结构10的稳定工作。可以理解,所述芯片101、102的类型包括但不限于引线键合芯片和倒装芯片,所述分立器件包括但不限于电容和电感。
所述系统级芯片封装结构10还包括散热装置100,所述散热装置100包括层压设置的绝缘层106和导热层107,所述绝缘层106完全包覆并贴合所述多个芯片101、102、多个分立器件103的外表面及所述基板104的上表面,用于将所述多个芯片101、102及多个分立器件103产生的热量传导至所述导热层107和所述基板104上,以通过所述导热层107及所述基板104将所述多个芯片101、102及多个分立器件103产生的热量散除。其中,所述层压设置是指:在用或不用粘结剂的条件下,借助加热、加压把两层或多层相同或不相同材料结合为整体。在本实施例中,所述绝缘层106和所述导热层107在热力和压力的作用下结合为整体。在本实施例中,所述层压设置的绝缘层106和导热层107在垂直于所述基板104的上表面的投影方向上重叠。
可以理解,所述绝缘层106还用于将所述多个芯片101、102及多个分立器件103产生的热量传导至空气中,以直接通过所述绝缘层106将所述多个芯片101、102及多个分立器件103产生的热量散除。其中,所述绝缘层106具有良好的可成形性及一定的导热率,从而可以通过热压的方式将所述散热装置100固化于所述基板104上,并使得所述绝缘层106与所述多个芯片101、102、多个分立器件103的外表面及所述基板104的上表面紧密贴合,从而有效增加散热面积,实现对所述多个芯片101、102、多个分立器件103的快速散热。在本实施例中,所述绝缘层106由可成形性的绝缘材料制成,例如包括并不限于环氧树脂或聚酰亚胺;所述导热层107由石墨烯、石墨片或氮化硼片按照不同的比例掺杂环氧树脂或聚酰亚胺制成。可以理解,所述导热层107并不限于由石墨烯、石墨片或氮化硼片掺杂环氧树脂或聚酰亚胺制成,也可以有其他与石墨烯、石墨片或氮化硼片具有相似性能的导热材料按照一定的比例均匀掺杂于其他与环氧树脂或聚酰亚胺具有相似性能的可成形性的绝缘材料制成。
在一种实施方式中,所述散热装置100可以包括多层所述绝缘层106和多层所述导热层107,多层所述绝缘层106和多层所述导热层107交替层压设置。当所述散热装置100包括多层所述绝缘层106和多层所述导热层107时,底层为绝缘层106,用于完全包覆所述多个芯片101、102、多个分立器件103的外表面及所述基板104的上表面,顶层为导热层107,用于将所述多个芯片101、102及多个分立器件103产生的热量传导至空气中。可以理解,不同的绝缘层106及不同的导热层107可以有不同的导热系数和不同的导电系数。
请参阅图2,在制造所述系统级芯片封装结构10时,可以首先在所述基板104的上表面封装好对应的芯片101、102及分立器件103,然后采用热压的方式将所述散热装置100固化于所述基板104的上表面。具体地,可以提前将所述绝缘层106和导热层107层压在一起形成所述散热装置100,进而将所述绝缘层106朝向所述基板104的上表面,采用热压的方式将所述散热装置100固化于所述基板104的上表面,如图2所示。也可以先采用热压的方式将所述绝缘层106固化于所述基板104的上表面,然后采用热压的方式将所述导热层107固化于所述绝缘层106的上表面。可以理解,将所述散热装置100固化于所述基板104的上表面的工艺条件可以包括但不限于温度条件和压力条件。
请参阅图3,通过将所述散热装置100的绝缘层106完全包覆于所述多个芯片101、102、多个分立器件103的外表面及所述基板104的上表面,从而可以在所述多个芯片101、102、多个分立器件103周围形成全方位的散热路径,实现多个芯片101、102、多个分立器件103的均匀高效散热。具体地,所述系统级芯片封装结构10的散热路径如图3中箭头方向所示,由于所述绝缘层106与所述基板104的上表面及所述导热层107紧密接触,所述多个芯片101、102、多个分立器件103产生的热量一方面可以通过所述绝缘层106传导至所述基板104上,进而通过所述基板104将所述热量散除到空气中,另一方面可以通过所述绝缘层106传导至所述导热层107上,进而通过所述导热层107将所述热量散除到空气中,此外,靠近所述基板104的边缘位置的热量,还可以通过所述绝缘层106直接传导至空气中以实现散热。由于所述绝缘层106与所有的芯片101、102及分离器件103均紧密接触,从而可以使得芯片101、102、分离器件103产生的热量可以更均匀地传导至所述导热层107及所述基板104上,从而可以有效防止因个别芯片或者分立器件温度过高而影响整个系统级芯片封装结构10的性能。
请参阅图4,在本发明一个实施例中,提供一种终端40,包括系统级芯片封装结构10和主板20,所述主板20上设置有焊盘21,所述系统级芯片封装结构10通过所述焊球105焊接于所述焊盘21上,从而实现与所述主板20的电性连接。其中,所述系统级芯片封装结构10为图1至图3所示实施例中所述的系统级芯片封装结构10,具体可以参照图1至图3所示实施例中的相关描述,此处不再赘述。可以理解,由于所述系统级芯片封装结构10包括所述散热装置100,从而可以实现所述系统级芯片封装结构10内各芯片101、102及分离器件103的均匀高效散热,有利于提升所述终端40的散热性能,从而保证所述终端40工作的稳定性。其中,所述终端可以是但不限于手机、平板电脑、智能手表等。
请参阅图5,在本发明一个实施例中,提供一种系统级芯片封装结构的制造方法,包括:
步骤501:提供一基板,并在基板的上表面封装多个芯片及多个分离器件;
步骤502:提供一散热装置,所述散热装置包括绝缘层和导热层;
步骤503:对所述绝缘层加热到第一温度,并以第一压力持续压合第一时间至完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面;
步骤504:对所述绝缘层热到第二温度并持续第二时间,以对所述绝缘层进行固化;
步骤505:对所述导热层加热到第三温度,并以第二压力持续压合第三时间至所述导热层贴合所述绝缘层的上表面;
步骤506:对所述导热层加热到第四温度并持续第四时间,以对所述导热层进行固化。
在本实施例中,在本实施例中,所述第一温度和所述第三温度均为150度,所述第二温度和所述第四温度均为175度,所述第一压力和所述第二压力均为7-10Kgf/cm2(千克力/平方厘米),所述第一时间和所述第三时间均为30秒,所述第二时间和所述第四时间均为1小时。可以理解,所述绝缘层压合时的温度条件、压力条件及持续时间与所述导热层压合时的温度条件、压力条件及持续时间可以相同或者不同,所述绝缘层固化时的温度条件及持续时间与所述导热层固化时的温度条件及持续时间也可以相同或者不同,具体可以根据不同的材料来选择。
请参阅图6,在本发明一个实施例中,提供一种系统级芯片封装结构的制造方法,包括:
步骤601:提供一基板,并在基板的上表面封装多个芯片及多个分离器件;
步骤602:提供一散热装置,所述散热装置包括绝缘层和导热层;
步骤603:将所述导热层压合于所述绝缘层上,形成层压设置的绝缘层和导热层;
步骤604:将所述绝缘层朝向所述基板的上表面,对所述散热装置加热到第一温度,并以第一压力持续压合第一时间至所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面;
步骤605:对所述散热装置加热到第二温度并持续第二时间,以对所述散热装置进行固化。
在本实施例中,在本实施例中,所述第一温度为150度,所述第二温度为175度,所述第一压力为7-10Kgf/cm2,所述第一时间为30秒,所述第二时间为1小时。
可以理解,图5和图6所示方法实施例中各步骤中用到的工艺参数仅为示例性参数,并不能用于限制本发明的保护范围。所述工艺参数可以根据所述绝缘层和导热层所使用的材料的不同而适当改变。
所述系统级芯片封装结构10通过在所述基板104的上表面设置所述包括绝缘层106和导热层107的散热装置100,且通过热压工艺使得所述绝缘层106与所述多个芯片101、102、多个分立器件103的外表面及所述基板104的上表面紧密贴合,从而可以有效增加散热面积,提升散热均匀性,实现对所述多个芯片101、102、多个分立器件103的快速高效散热。
Claims (13)
1.一种芯片封装结构,其特征在于,包括基板、封装于所述基板的上表面的多个芯片和多个分离器件、以及散热装置,所述散热装置包括层压设置的多层绝缘层和多层导热层,多层所述绝缘层和多层所述导热层交替层压设置,且底层为所述绝缘层,顶层为所述导热层,位于底层的所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,用于将所述多个芯片及多个分立器件产生的热量传导至所述导热层和所述基板上,以通过位于顶层的所述导热层及所述基板将所述多个芯片及多个分立器件产生的热量散除。
2.如权利要求1所述的芯片封装结构,其特征在于,所述层压设置的绝缘层和导热层在垂直于所述基板的上表面的投影方向上重叠。
3.如权利要求1所述的芯片封装结构,其特征在于,所述绝缘层还用于将所述多个芯片及多个分立器件产生的热量传导至空气中,以直接通过所述绝缘层将所述多个芯片及多个分立器件产生的热量散除。
4.如权利要求1至3中任一项所述的芯片封装结构,其特征在于,所述绝缘层由可成形性的绝缘材料制成。
5.如权利要求1述的芯片封装结构,其特征在于,所述导热层由导热材料和可成形性的绝缘材料制成。
6.如权利要求5述的芯片封装结构,其特征在于,所述导热材料均匀掺杂于所述可成形性的绝缘材料中。
7.如权利要求5或6所述的芯片封装结构,其特征在于,所述导热材料包括石墨烯、石墨片、氮化硼片中的一种或多种。
8.如权利要求5所述的芯片封装结构,其特征在于,所述可成形性的绝缘材料包括环氧树脂或聚酰亚胺中的至少一项。
9.如权利要求1所述的芯片封装结构,其特征在于,所述芯片包括引线键合芯片或倒装芯片中的任一项。
10.如权利要求1所述的芯片封装结构,其特征在于,所述芯片封装结构还包括多个焊球,所述多个焊球呈阵列设置于所述基板的下表面。
11.一种芯片封装结构的制造方法,其特征在于,包括:
提供一基板,并在基板的上表面封装多个芯片及多个分离器件;
提供一散热装置,所述散热装置包括多层绝缘层和多层导热层,其中,多层所述绝缘层和多层所述导热层交替层压设置,且所述散热装置的底层为所述绝缘层,其顶层为所述导热层;
将所述散热装置层压设置于所述基板的上表面,并使位于底层的所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面。
12.如权利要求11所述的方法,其特征在于,所述将所述散热装置层压设置于所述基板的上表面,并使位于底层的所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,包括:
对所述绝缘层加热到第一温度,并以第一压力持续压合第一时间至完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面;
对所述绝缘层加热到第二温度并持续第二时间,以对所述绝缘层进行固化;
对所述导热层加热到第三温度,并以第二压力持续压合第三时间至所述导热层贴合所述绝缘层的上表面;
对所述导热层加热到第四温度并持续第四时间,以对所述导热层进行固化。
13.如权利要求11所述的方法,其特征在于,所述将所述散热装置层压设置于所述基板的上表面,并使位于底层的所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面,包括:
将所述导热层压合于所述绝缘层上,形成层压设置的绝缘层和导热层作为所述散热装置;
将所述绝缘层朝向所述基板的上表面,对所述散热装置加热到第一温度,并以第一压力持续压合第一时间至所述绝缘层完全包覆并贴合所述多个芯片、多个分立器件的外表面及所述基板的上表面;
对所述散热装置加热到第二温度并持续第二时间,以对所述散热装置进行固化。
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CN110060961B (zh) | 2018-01-19 | 2021-07-09 | 华为技术有限公司 | 一种晶圆封装器件 |
US10720416B2 (en) * | 2018-08-15 | 2020-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package including thermal relaxation block and manufacturing method thereof |
US10973114B2 (en) * | 2018-10-29 | 2021-04-06 | L3 Technologies, Inc. | Indium-based interface structures, apparatus, and methods for forming the same |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101174598A (zh) * | 2006-10-23 | 2008-05-07 | 恩益禧电子股份有限公司 | 电子器件及其制造方法 |
CN104620373A (zh) * | 2012-12-18 | 2015-05-13 | 富士电机株式会社 | 半导体装置 |
CN105453253A (zh) * | 2013-08-07 | 2016-03-30 | 日东电工株式会社 | 中空型电子器件密封用树脂片及中空型电子器件封装件的制造方法 |
CN106206486A (zh) * | 2015-05-25 | 2016-12-07 | 松下知识产权经营株式会社 | 电子器件封装 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6395582B1 (en) * | 1997-07-14 | 2002-05-28 | Signetics | Methods for forming ground vias in semiconductor packages |
US6963141B2 (en) * | 1999-12-31 | 2005-11-08 | Jung-Yu Lee | Semiconductor package for efficient heat spreading |
JP4268778B2 (ja) * | 2001-12-27 | 2009-05-27 | ポリマテック株式会社 | 発熱電子部品の冷却方法及びそれに用いる熱伝導性シート |
JP2004104115A (ja) | 2002-08-21 | 2004-04-02 | Matsushita Electric Ind Co Ltd | パワーモジュール及びその製造方法 |
TWI234210B (en) * | 2002-12-03 | 2005-06-11 | Sanyo Electric Co | Semiconductor module and manufacturing method thereof as well as wiring member of thin sheet |
US20050039884A1 (en) * | 2003-08-20 | 2005-02-24 | Ivan Pawlenko | Conformal heat sink |
WO2005027223A1 (ja) * | 2003-09-09 | 2005-03-24 | Sanyo Electric Co., Ltd | 回路素子と絶縁膜を含む半導体モジュールとその製造方法およびその応用 |
US8202765B2 (en) | 2009-01-22 | 2012-06-19 | International Business Machines Corporation | Achieving mechanical and thermal stability in a multi-chip package |
CN102208373A (zh) | 2010-03-30 | 2011-10-05 | 力成科技股份有限公司 | 芯片封装结构及其制造方法 |
CN102371739A (zh) * | 2010-08-26 | 2012-03-14 | 富葵精密组件(深圳)有限公司 | 胶片及其制作方法 |
CN102683302A (zh) | 2011-03-08 | 2012-09-19 | 中国科学院微电子研究所 | 一种用于单芯片封装和系统级封装的散热结构 |
TW201320263A (zh) * | 2011-11-11 | 2013-05-16 | Chipmos Technologies Inc | 加強散熱的封裝結構 |
CN102692000A (zh) * | 2012-06-04 | 2012-09-26 | 山西山地新源科技有限公司 | 用于led大功率照明模组的石墨基板及制作工艺 |
US9159643B2 (en) * | 2012-09-14 | 2015-10-13 | Freescale Semiconductor, Inc. | Matrix lid heatspreader for flip chip package |
WO2014045671A1 (ja) * | 2012-09-21 | 2014-03-27 | 株式会社村田製作所 | 電子機器 |
US8575767B1 (en) * | 2012-10-06 | 2013-11-05 | Ixys Corporation | Reflow of thermoplastic sheet for passivation of power integrated circuits |
JP6259608B2 (ja) | 2013-08-09 | 2018-01-10 | 日東電工株式会社 | 電子デバイス封止用樹脂シート及び電子デバイスパッケージの製造方法 |
US10319660B2 (en) | 2013-10-31 | 2019-06-11 | Nxp Usa, Inc. | Semiconductor device packages using a thermally enhanced conductive molding compound |
CN106684057B (zh) * | 2016-12-30 | 2019-10-22 | 华为技术有限公司 | 芯片封装结构及其制造方法 |
-
2016
- 2016-12-30 CN CN201611258231.8A patent/CN106684057B/zh active Active
-
2017
- 2017-11-28 WO PCT/CN2017/113385 patent/WO2018121162A1/zh active Application Filing
- 2017-12-27 US US15/855,752 patent/US10903135B2/en not_active Expired - Fee Related
- 2017-12-28 TW TW106146116A patent/TWI663695B/zh active
- 2017-12-29 KR KR1020170183330A patent/KR102082252B1/ko active Active
- 2017-12-29 EP EP17211035.5A patent/EP3343610B1/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101174598A (zh) * | 2006-10-23 | 2008-05-07 | 恩益禧电子股份有限公司 | 电子器件及其制造方法 |
CN104620373A (zh) * | 2012-12-18 | 2015-05-13 | 富士电机株式会社 | 半导体装置 |
CN105453253A (zh) * | 2013-08-07 | 2016-03-30 | 日东电工株式会社 | 中空型电子器件密封用树脂片及中空型电子器件封装件的制造方法 |
CN106206486A (zh) * | 2015-05-25 | 2016-12-07 | 松下知识产权经营株式会社 | 电子器件封装 |
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