CN106682268B - Programmable logic device configuration method and equipment - Google Patents

Abstract

The embodiment of the invention discloses a configuration method and equipment of a programmable logic device, which are used for realizing design files by generating a PLD (programmable logic device) model file containing a device model and an operator model and a PLD (programmable logic device); mapping a target function module and a connection relation in a design file of a PLD (programmable logic device) to the top layer of a device model in the PLD model file, and configuring a corresponding grid point element on the top layer; traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file; and writing the configuration file into the PLD to be configured. The method can realize the precise configuration process of the PLD, and is beneficial to the development and the test of designers on the PLD. The invention can configure the basic elements forming the PLD, thereby realizing the maximization of the resource utilization of the PLD chip, and simultaneously, flexibly setting the internal structure of the lattice point elements and the connection relation among the lattice point elements, and effectively solving the problem of accurate control of the critical path.

Description

Programmable logic device configuration method and device

technical field

The present invention relates to the technical field of digital electronics, and in particular, to a method and device for configuring a programmable logic device.

Background technique

Programmable Logic Device (Programmable Logic Device, PLD for short) is an electronic device whose logic function can be changed at any time according to actual needs. PLDs are generally divided into Programmable ReadOnly Memory (PROM), Erase Programmable Read Only Memory (EPROM), Programmable Logic Array (PLA), and Programmable Logic Array (PLA). Array logic (Programmable Array Logic, PAL for short), Generic Array Logic (GAL for short), Field Programmable Gate Array (FPGA for short), Complex Programmable Logic Device (Complex Programmable Logic Device, for short) CPLD), etc.

In the field of digital electronic technology, the circuit of a fixed logic device is permanent, and once it is manufactured, it cannot be changed, and only one or a group of corresponding logic functions can be completed. However, due to its high flexibility, PLD can change its logic function at any time through programming according to actual needs in the design process, thus providing users and designers with more choices; at the same time, in the design process, designers only It is necessary to use low-cost software tools to develop, simulate, and debug its design. Different logic functions can be realized without changing the physical structure of the PLD itself, which greatly reduces the cost of designers and manufacturers in the design and development process. Therefore, PLD has been widely used.

In the prior art, the configuration and debugging process of PLD is varied, usually described in hardware description languages such as Verilog HDL (Verilog Hardware Description Language), VHDL (Very-High-Speed Integrated Circuit Hardware Description Language, very high-speed integrated circuit hardware description language). Design logic, and then use EDA (Electronics Design Automation, electronic design automation) tools to generate configuration files through automatic layout and routing and other steps, and then download the configuration files to the PLD for debugging. However, due to the limitation of the layout and routing algorithm, the above method cannot achieve the maximum utilization of PLD resources, and also cannot achieve precise control of the critical path, which may lead to the problem that the above method cannot be applied in some special occasions.

SUMMARY OF THE INVENTION

The present invention provides a programmable logic device configuration method and equipment, so as to solve the problem that the existing PLD configuration method cannot achieve precise control of the critical path and achieve greater utilization of PLD resources.

To this end, an embodiment of the present invention provides a programmable logic device configuration method, including:

Generate a programmable logic device model file, the programmable logic device model file contains a device model and an operator model; the device model includes the basic element of the programmable logic device at the bottom layer, the grid element in the middle layer, and the grid element at the top layer. A point system, the grid element is composed of at least one basic element, and the grid system is composed of at least one grid element; the operator model includes functional modules for realizing each function, and a function module is composed of a grid element in the grid element. The connection and combination between the basic components are realized;

Select the corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determine the connection relationship between the target function modules to generate the programmable logic device implementation design file;

mapping the target function modules and connection relationships in the programmable logic device implementation design file to the top layer of the device model in the programmable logic device model file, and configuring the corresponding lattice elements on the top layer;

Traversing and extracting the configuration parameters of each grid element on the top layer to generate a configuration file;

Writing the configuration file into the programmable logic device to be configured.

Further, the device model includes identification information for uniquely identifying the device model, functional parameter configuration information of the implemented function, and corresponding interface information;

The lattice element includes configuration description information for describing positions, graphic description information for graphic representation, and structure description information for describing internal structures.

Further, the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and description information of all implementations for implementing the functional module.

Further, the generation of the programmable logic device implementation design file includes:

Determine and define each input and output interface according to the connection relationship;

For each of the target function modules, generate an internal implementation description statement describing each target function module to obtain an instance of the target function module;

A description statement of each routing path is generated according to the connection relationship, and key routing paths are identified and constrained to obtain network cable instances.

Further, mapping the target function modules and connection relationships in the programmable logic device implementation design file to the top layer, and configuring the corresponding lattice elements on the top layer includes:

Compile the device model sequentially from the bottom layer to the top layer to obtain the top-level grid model of the device model and store it in the model compilation library, and compile and store each functional module in the operator model in the model compilation library;

Compile the programmable logic device implementation design file to obtain the target function module instance and the network cable instance;

Find the respective corresponding function modules from the model compilation library according to the target function module instance, and configure the corresponding function module according to the parameters of each target function module instance to obtain a parameter configuration function module;

According to the network cable instance and the implementation of each parameter configuration function module, each parameter configuration function module is mapped to the grid corresponding to the top-level grid model, and the corresponding parameters of the parameter configuration function module are paired accordingly. Grid elements on the grid are configured.

The embodiment of the present invention also provides a programmable logic device configuration device, including:

The model generation module is used to generate a programmable logic device model file, wherein the programmable logic device model file contains a device model and an operator model; A point element and a top-level lattice point system, the lattice point element is composed of at least one basic element, and the lattice point system is composed of at least one lattice point element; the operator model includes functional modules for realizing each function, one functional module It is realized by the connection and combination between the basic elements in the lattice element;

A design generation module is used to select a corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determine the connection relationship between the target function modules to generate a programmable logic format in Valence language format. Logic device implementation design file;

The processing module is used to map the target function modules and connection relationships in the programmable logic device implementation design file to the top layer of the device model in the programmable logic device model file, and map the corresponding grid points on the top layer and is further used for traversing and extracting the configuration parameters of each grid element on the top layer to generate a configuration file, and writing the configuration file into the to-be-configured programmable logic device.

Further, the device model includes identification information for uniquely identifying the device model, functional parameter configuration information of the implemented function, and corresponding interface information;

The lattice element includes configuration description information for describing positions, graphic description information for graphic representation, and structure description information for describing internal structures.

Further, the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and description information of all implementations for implementing the functional module.

Further, the design generation module is used to determine and define each input and output interface according to the connection relationship, and for each of the target function modules, generate an internal implementation description statement describing each target function module to obtain the target function module instance, and generating description sentences of each routing path according to the connection relationship, and identifying and constraining key routing paths to obtain network cable instances.

Further, the processing module includes:

The compiling sub-module is used to sequentially compile the device model from the bottom layer to the top layer to obtain the top-level grid model of the device model and store it in the model compilation library, and compile and store each functional module in the operator model in the In the model compilation library; also used for compiling the programmable logic device implementation design file to obtain the target function module instance and the network cable instance;

A mapping submodule is used to find the respective corresponding function modules from the model compilation library according to the target function module instance, and configure the corresponding function module according to the parameters of each target function module instance to obtain a parameter configuration function module; Describe the implementation mode of the network cable instance and each parameter configuration function module, map each parameter configuration function module to the grid corresponding to the top-level grid model, and map the corresponding grid according to the parameters of each parameter configuration function module. on the grid element to configure.

beneficial effect

According to the programmable logic device configuration method and device provided by the embodiments of the present invention, by generating a programmable logic device (PLD) model file including a device model and an operator model; A point element and a top-level lattice point system, the lattice point element is composed of at least one basic element, and the lattice point system is composed of at least one lattice point element; the operator model includes functional modules for realizing each function, one functional module It is realized by the connection and combination of the basic elements in the lattice element; according to the function to be realized by the PLD to be configured, the corresponding target function module is selected from the operator model, and the connection relationship between the target function modules is determined to Generate a PLD implementation design file in the Valence language format; map the target function modules and connection relationships in the PLD implementation design file to the top layer of the device model in the PLD model file, and map the corresponding grid elements on the top layer. performing configuration; traversing and extracting configuration parameters of each grid element on the top layer to generate a configuration file; and writing the configuration file into the PLD to be configured. It can effectively solve the problems of inability to achieve precise control of critical paths and inability to achieve greater utilization of PLD resources, and can realize precise configuration of PLDs. The utilization of resources is maximized, and at the same time, the internal structure of the grid element and the connection relationship between the grid elements can be flexibly set, so it is beneficial for designers to develop and test PLDs and promote the development of PLD technology.

Description of drawings

1 is a schematic flowchart of a PLD configuration method provided in Embodiment 1 of the present invention;

2 is a schematic structural diagram of a lattice point system in a device model provided by Embodiment 1 of the present invention;

3 is a schematic diagram of the composition of the PLD implementation design file provided in Embodiment 1 of the present invention;

4 is a schematic flowchart of a mapping configuration method for a PLD device model provided by Embodiment 1 of the present invention;

5 is a schematic structural diagram of a programmable logic device configuration device according to Embodiment 2 of the present invention;

FIG. 6 is a schematic structural diagram of another programmable logic device configuration device according to Embodiment 2 of the present invention.

Detailed ways

The embodiments of the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

Example 1:

Embodiment 1 of the present invention provides a method for implementing a configuration process of a programmable logic device based on Valence language, so as to achieve the purpose of configuring and debugging a PLD, and the configuration process is efficient and convenient, which is beneficial for designers to develop and test PLD logic functions , which is conducive to promoting the development of PLD technology.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of a PLD configuration method provided in Embodiment 1 of the present invention, including:

S11: Generate a PLD model file, where the PLD model file includes a device model and an operator model; the device model includes the PLD basic elements at the bottom layer, the lattice point elements in the middle layer, and the lattice point system at the top layer, the lattice points The element is composed of at least one basic element, and the grid system is composed of at least one grid element; the operator model includes functional modules that realize each function, and a functional module is realized by the connection and combination of the basic elements in the grid element .

By generating a PLD model file, that is, modeling the PLD to be configured, the PLD model file generated by modeling includes a device model. Among them, the device model includes a PLD basic element at the bottom layer (which can be called Prim Device), a grid element in the middle layer (which can be called Grid Device), and a grid system at the top layer (which can be called Architecture Device). The basic element of the bottom layer is the abstract minimum work unit, and the grid element of the middle layer is composed of one or at least two basic elements. Some are different, and all may be the same. Specifically, the composition and/or number of basic elements in the grid element can be flexibly set according to the logic function of the PLD to be configured. The grid system on the top layer is formed by the arrangement of grid elements according to certain rules. The grid system is composed of at least one grid element, usually composed of a plurality of grid elements, such as dozens, hundreds, or even thousands of grid elements on a large scale. For a better understanding of the present invention, please refer to FIG. 2 , which is a schematic structural diagram of a lattice point system in a device model provided by Embodiment 1 of the present invention. It includes the grid system of the top layer, the grid elements of the middle layer, and the basic elements of the bottom layer. The grid point system is composed of a plurality of regularly arranged grid point elements, each grid point element is composed of at least one basic element, and the basic elements in each grid point element may be the same or different.

The generated device model should also include identification information that uniquely identifies the device model, functional parameter configuration information of the implemented function, and corresponding interface information. It should be understood that the identification information that uniquely identifies the device model may be the name of the model device; the function parameter configuration information may be specifically set according to the logic function implemented by the PLD to be configured.

In the process of generating the device model, the functional structure of each component for generating the PLD device model to be configured should be described, so as to form a complete device model. Each model entity can be called a component (Device), and specifically can be a basic element, a lattice element, and a lattice system, all of which can be called a component. The component should include the name of the corresponding component, interface information and configuration parameters, where the name of the component can be used as the unique identification information of the component, the interface is mainly used for signal connection, and the configuration parameters determine the specific function implemented by the component.

In this embodiment, the description language of the above structure format (eg, PLD model file, PLD implementation design file) is called Valence language.

The description of each component based on Valence language can be carried out from many aspects, including structure description (Structure View), configuration description (Configuration View) and graphic description (Schematic View). The structure description is used to define the internal structure of the component. For example, a grid element is formed by combining and connecting multiple basic elements. The structure description defines the configuration parameter value of each basic element and the connection relationship between the basic elements. It should be understood that since a basic element is an abstract minimum basic unit, there is no structural description of the basic element. The configuration description is used to define the configuration point (Config Bit, one-to-one correspondence with the physical switch in the PLD device) and the configuration value (Config Value) of the component. Since the grid components are arranged regularly in the top-level grid system, Therefore, all Config Bits can be planned in the grid element, so that the position of a certain Config Bit in the whole PLD device can be easily located. Graphical description is used to define the graphics of the component, mainly used for drawing.

For example, the grid element is described from the above three aspects, so as to obtain configuration description information including position description, graphic description information for graphic representation, and structure description information for describing internal structure. The configuration description information includes the specific coordinate value of the grid element, for example, it can be expressed as: (a, 1, 4), where "a" indicates that the grid element belongs to grid point system a, and "1, 4" indicates that the grid The specific position of the point element in the grid point system a is in the first row and the fourth column. The graphic description information includes a graphic for representing the grid element, and the image can be specifically set based on the logic function to be implemented by the grid element. The structure description information is used to describe the internal structure of the lattice element, specifically which basic elements the lattice element consists of and the connection relationship between the basic elements.

When modeling the PLD device to be configured by the Valence language, the PLD model file also includes an operator model, and the operator model includes functional modules (that is, operators) that implement each function. The connection and combination between the basic elements in the element are realized, and different basic elements can form different functional modules through different connection methods to realize different logical functions. Specifically, the functional modules include, but are not limited to, adders, multipliers, comparators, flip-flops, etc., all of which may be referred to as a functional module.

The functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and description information of all implementations for implementing the functional module. It should be noted that the specific function of a functional module is not unique in terms of implementation, and there may be multiple implementations, and one of the implementations may be reasonably selected in the subsequent configuration process based on actual usage scenarios.

S12: Select a corresponding target function module from the operator model according to the function of the PLD to be configured, and determine the connection relationship between the target function modules to generate a PLD implementation design file in Valence language format.

Specifically, each input and output interface can be determined according to the connection relationship of each target functional module; for each target functional module, an internal implementation description statement describing each target functional module is generated; and each routing path is generated according to the connection relationship of each target functional module description statement, and identify constraints on critical routing paths. Finally, a PLD implementation design file in Valence language format is generated.

For a better understanding of the present invention, please refer to FIG. 3 , which is a schematic diagram of the composition of a PLD implementation design file provided in Embodiment 1 of the present invention. The PLD implementation design file mainly includes three statement blocks: an interface definition statement block, an internal implementation statement block, and a routing path definition statement block.

Among them, the interface definition statement block contains description statements for defining the design name, defining the relevant parameters of the design, and input and output interface statements; the input and output ports here can be simply understood as the input and output of the module in the Verilog language. The function is the interaction between the PLD device and external signals, such as the clock signal input to the PLD device. The internal implementation statement block contains the designed internal structure description statement, specifically, instantiate and connect a specific function module to realize the corresponding function. When writing the internal structure, not only the existing function modules can be used, but also special function modules can be designed according to actual needs, and even lattice elements or basic elements can be directly configured and connected, for example, function modules and/or components can be directly specified in The position in the entire PLD to be configured, specifically, the position of the used functional modules and/or components may be constrained by the coordinates of each grid point in the grid point system.

The routing path definition statement block contains description statements of each routing path, which are used to identify and constrain the key routing paths of the PLD, and realize precise control of the key routing paths. The key routing path in this embodiment can be any network cable (a network cable can be understood as a wire in the Verilog language, and its function is to connect the ports of two functional modules to realize data transmission), a functional module connected at both ends of the network cable The ports are all determined in the internal structure description statement. The routing path definition statement only constrains the path of the key network cables. The network cables that are not constrained can be routed using a routing algorithm in subsequent processing. For example, when writing, first use the wiring constraint keyword to identify a network cable to start constraining, and then use the connection symbol to connect each node of the network cable from the start point to the end point in sequence, and finally end with a semicolon.

S13: Map the target function modules and connection relationships in the PLD implementation design file to the top layer of the device model in the PLD model file, and configure corresponding lattice elements on the top layer.

After the PLD model file in the Valence language format and the PLD implementation design file are written and generated, the target function modules, the connection relationship between them, and the top-level model in the device model can be read, and the PLD implementation design file can be read. The target function module and connection relationship of the PLD model file are mapped to the top layer of the device model in the PLD model file, so as to realize the configuration of the PLD device model.

In order to better understand the present invention, the following describes the PLD device model mapping and configuration process in detail. Please refer to FIG. 4 . FIG. 4 is a schematic flowchart of a mapping configuration method for a PLD device model provided in Embodiment 1 of the present invention, including:

S131: Compile the PLD model file, and store the compilation result in the model compilation library.

Because the PLD model file contains the device model and the operator model, the top-level mesh model of the device model can be obtained after compiling the device model, and it can be stored in the model compilation library; for the operator model, each of the The function modules are compiled and stored in the model compilation library.

S132: Compile the PLD implementation design file to obtain the target function module instance and the network cable instance.

When compiling the PLD implementation design file, the target function module instance is obtained based on the internal implementation description statement describing each target function module, the network cable instance is generated according to the connection relationship between each function module, and the key path is determined according to the routing path description statement. Constrain. The target function module instance and network cable instance obtained after compiling the PLD implementation design file can be stored in the work library (Work Lib). The network cable instance has the unique identifier of each target function module instance to which it is connected, and the network cable instance that is over-constrained by using the routing path definition statement block will also store its specific routing path.

S133: Find the respective corresponding function modules from the model compilation library according to the target function module instance, and configure the corresponding function module according to the parameters of each target function module instance to obtain a parameter configuration function module.

S134: According to the network cable instance and the implementation manner of each parameter configuration function module, map each parameter configuration function module to a grid corresponding to the top-level grid model, and configure parameters of the function module according to each parameter Configure the mesh elements on the corresponding mesh.

Take out the network cable instance in the working library, take out the top-level grid model of the PLD device from the model compilation library, map each parameter configuration function module to the specific grid point corresponding to the top-level grid model, and according to the current parameters The configuration parameters of the configuration function module configure the current grid element. According to the network cable instance taken out, use the routing algorithm to assign a suitable routing path to each network cable. For a specific routing path that has been defined, routing is performed according to the routing path.

The specific implementation mode of each parameter configuration function module can be manually written into the PLD implementation design file, or can be automatically selected by the compiling software.

S14: Traversely extract the configuration parameters of each grid element on the top layer to generate a configuration file.

Finally, by traversing each grid element in the top-level grid system of the PLD, reading its configuration information and writing it to the file, after the configuration of all grid elements is completed, the configuration file of the PLD can be generated.

S15: Write the configuration file into the to-be-configured PLD.

After the configuration file of the PLD is generated, it can be written into the PLD to be configured by writing software. After writing, it can also be run and tested to verify that the desired logic function and stability are achieved. If the expected effect is not achieved, it can be achieved by modifying the corresponding program files, which is convenient and quick, and does not require high design costs.

An embodiment of the present invention provides a method for configuring a programmable logic device, by generating a PLD model file in the Valence language format that includes a device model and an operator model; the device model includes a PLD basic element located at the bottom layer and a grid element in the middle layer. and a top-level grid point system, the grid point element is composed of at least one basic element, and the grid point system is composed of at least one grid point element; the operator model includes functional modules for realizing each function, and one function module is composed of grid points. The connection and combination between the basic elements in the point element are realized; and the corresponding target function module is selected from the operator model according to the function to be realized by the PLD to be configured, and the connection relationship between the target function modules is determined to generate A PLD implementation design file in the Valence language format; map the target function modules and connection relationships in the PLD implementation design file to the top layer of the device model in the PLD model file, and perform the corresponding grid elements on the top layer. configuration; traversing and extracting configuration parameters of each grid element on the top layer to generate a configuration file; and writing the configuration file into the to-be-configured PLD. It can realize the precise configuration process of the PLD, which is beneficial to the designer's development and testing of the PLD. Since the present invention can configure the basic elements constituting the PLD, the resource utilization of the PLD chip can be maximized. The problem of precise control of the critical path.

Embodiment 2:

An embodiment of the present invention provides a programmable logic device configuration device, which is used to implement the programmable logic device configuration method described in the first embodiment. Please refer to FIG. 5 , which is a schematic structural diagram of a programmable logic device configuration device according to Embodiment 2 of the present invention. The programmable logic device configuration device 5 includes: a model generation module 51 , a design generation module 52 , and a processing module 53 , in:

The model generation module 51 is used to generate a PLD model file, the PLD model file includes a device model and an operator model; the device model includes the PLD basic elements located at the bottom layer, the grid point elements in the middle layer and the grid point system at the top layer , the grid element is composed of at least one basic element, and the grid system is composed of at least one grid element; the operator model includes functional modules for realizing each function, and a functional module is composed of basic elements in the grid element The connection between the combination is realized.

The PLD model file generated by the model generation module 51, that is, the PLD to be configured is modeled, and the generated PLD model file includes the device model. Among them, the device model includes the basic elements of the PLD at the bottom layer, the lattice elements in the middle layer, and the lattice point system at the top layer. The basic element of the bottom layer is the abstract minimum work unit, the grid element of the middle layer is formed by the combination of one or more basic elements, and the grid point system of the top layer is formed by the arrangement of grid elements according to certain rules.

The device model generated by the model generation module 51 should also include identification information that uniquely identifies the device model, function parameter configuration information of the implemented function, and corresponding interface information. It should be understood that the identification information that uniquely identifies the device model may be the name of the model device; the function parameter configuration information may be specifically set according to the logic function implemented by the PLD to be configured.

In the process of generating the device model by the model generating module 51, it is also used to describe the functional structure of each component for generating the PLD device model to be configured, so as to form a complete device model. The individual components include PLD basic elements on the bottom layer, lattice elements in the middle layer, and lattice point systems on the top layer.

The description of each component by the model generation module 51 can be carried out from various aspects, including structural description, configuration description and graphic description. The structure description is used to define the internal structure of the component. For example, a grid element is formed by combining and connecting multiple basic elements. The structure description defines the configuration parameter value of each basic element and the connection relationship between the basic elements. It should be understood that since a basic element is an abstract minimum basic unit, there is no structural description of the basic element. The configuration description is used to define the configuration points and configuration values of the component. Since the grid components are arranged regularly in the top-level grid system, all Config Bits can be planned in the grid components, which is convenient The location of a certain Config Bit in the entire PLD device. Graphical description is used to define the graphics of the component, mainly used for drawing.

When modeling the PLD device to be configured by the model generation module 51, the PLD model file also includes an operator model, and the operator model includes functional modules for realizing each function. The connection and combination between components are realized, and different basic components can form different functional modules through different connection methods to realize different logical functions. Specifically, the functional modules include, but are not limited to, adders, multipliers, comparators, flip-flops, etc., all of which may be referred to as a functional module.

The functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and description information of all implementations for implementing the functional module. It should be noted that the specific function of a functional module is not unique in terms of implementation, and there may be multiple implementations, and a certain implementation may be reasonably selected based on the actual usage scenario in the subsequent configuration process.

In this embodiment, the programmable logic device configuration device 5 further includes a design generation module 52 for selecting a corresponding target function module from the operator model according to the function of the PLD to be configured, and determining each target function The connection relationship between modules is to generate a PLD implementation design file in Valence language format.

Specifically, the design generation module 52 can determine each input and output interface according to the functions to be implemented in the design; for each target function module, generate an internal implementation description statement describing each target function module; and generate a route according to the connection relationship of each target function module. The description statement of the line path, which identifies and constrains the key line path. Finally, a PLD implementation design file in Valence language format is generated.

The PLD implementation design file in the Valence language format generated by the design generation module 52 mainly includes three statement blocks: an interface definition statement block, an internal implementation statement block, and a routing path definition statement block.

Among them, the interface definition statement block contains description statements for defining the design name, defining the relevant parameters of the design, and input and output interface statements; the input and output ports here can be simply understood as the input and output of the module in the Verilog language. The function is the interaction between the PLD device and external signals, such as the clock signal input to the PLD device. The internal implementation statement block contains the designed internal structure description statement, specifically, instantiate and connect a specific function module to realize the corresponding function. When writing the internal structure, not only the existing function modules can be used, but also special function modules can be designed according to actual needs, and even lattice elements or basic elements can be directly configured and connected, for example, function modules and/or components can be directly specified in The position in the entire PLD to be configured, specifically, the position of the used functional modules and/or components may be constrained by the coordinates of each grid point in the grid point system.

The routing path definition statement block contains description statements of each routing path, which are used to identify and constrain the key routing paths of the PLD, and realize precise control of the key routing paths. The key routing path in this embodiment can be any network cable (a network cable can be understood as a wire in the Verilog language, and its function is to connect the ports of two functional modules to realize data transmission), a functional module connected at both ends of the network cable The ports are all determined in the internal structure description statement. The routing path definition statement only constrains the path of the key network cables. The network cables that are not constrained can be routed using a routing algorithm in subsequent processing.

In this embodiment, the PLD model file generated by the model generation module 51 and the PLD implementation design file generated by the design generation module 52, the description language for generating this file format can be called the Valence language.

The processing module 53 is used to map the target function modules and connection relationships in the PLD implementation design file to the top layer of the device model in the PLD model file, and configure the corresponding lattice elements on the top layer; traverse extraction The configuration parameters of each grid element on the top layer generate a configuration file, and the configuration file is written into the PLD to be configured.

After the model generation module 51 generates the PLD model file in the Valence language format, and the design generation module 52 generates the PLD implementation design file, the processing module 53 can read the target function modules, the connection between them, and the components. The top-level model in the model, and the target functional modules and connection relationships in the PLD implementation design file are mapped to the top-level of the device model in the PLD model file, so as to realize the configuration of the PLD device model.

The processing module 53 may further include a compiling sub-module 531 and a mapping sub-module 532 . Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of another programmable logic device configuration device according to Embodiment 2 of the present invention. The compilation sub-module 531 is used to sequentially compile the device model from the bottom layer to the top layer to obtain the top-level grid model of the device model, which is stored in the model compilation library, and compiles each functional module in the operator model. Then, it is stored in the model compilation library; it is also used to compile the PLD implementation design file to obtain the target function module instance and the network cable instance.

When the compiling submodule 531 compiles the PLD model file, since the PLD model file contains the device model and the operator model, the top-level mesh model of the device model can be obtained after compiling the device model, and can be stored in the model compilation library. For the operator model, the compiling sub-module 531 can also compile each functional module therein and store it in the model compiling library.

When the compilation sub-module 531 compiles the PLD implementation design file, it obtains an instance of the target function module based on the internal implementation description statement describing each target function module, generates a network cable instance according to the connection relationship between the various function modules, and describes it according to the routing path. Statements constrain the critical path. The target function module instance and network cable instance obtained after compiling the PLD implementation design file can be stored in the work library. The network cable instance has the unique identifier of each target function module instance to which it is connected, and the network cable instance that is over-constrained by using the routing path definition statement block will also store its specific routing path.

It should be understood that the compilation result of the PLD model file and the PLD implementation design file by the compilation submodule 531 is not limited to being stored in the model compilation library and the work library, but can also be stored in other storage spaces that can store the compilation result. .

The mapping submodule 532 is used to find the respective corresponding function modules from the model compilation library according to the target function module instance, and configure the corresponding function module according to the parameters of each target function module instance to obtain the parameter configuration function module; Describe the implementation mode of the network cable instance and each parameter configuration function module, map each parameter configuration function module to the grid corresponding to the top-level grid model, and map the corresponding grid according to the parameters of each parameter configuration function module. on the grid element to configure.

The embodiment of the present invention provides a programmable logic device configuration device 5, which generates a PLD model file in the Valence language format through the model generation module 51, where the PLD model file includes a device model and an operator model, and the device model includes a bottom layer. A basic element, a lattice element in the middle layer, and a lattice system in the top layer, the lattice element is composed of at least one basic element, and the lattice system is composed of at least one lattice element; the operator model includes the realization of each function The function module, a function module is realized by the connection and combination between the basic elements in the lattice element; the design generation module 52 is used to select the corresponding target function module from the operator model according to the function to be realized by the PLD to be configured, and Determine the connection relationship between the described target function modules to generate the PLD implementation design file in the Valence language format; the processing module 53 is used to map the target function module and connection relationship in the PLD implementation design file to the PLD model file on the top layer of the middle device model, and configure the corresponding grid elements on the top layer; traverse and extract the configuration parameters of each grid element on the top layer to generate a configuration file; and write the configuration file into the to-be-configured PLD. Through the programmable logic device configuration device, the precise configuration of the PLD can be realized, and the problems that the critical path cannot be accurately controlled and the resource utilization ratio of the PLD chip cannot be achieved effectively can be solved. At the same time, the internal structure of the grid element and the connection relationship between the grid elements can be flexibly set, which is beneficial for designers to develop and test the PLD logic function.

Obviously, those skilled in the art should understand that each module or each step of the above-mentioned embodiments of the present invention may be implemented by a general-purpose computing device, and they may be centralized on a single computing device, or distributed among multiple computing devices. On the network, they can optionally be implemented with program code executable by a computing device, so that they can be stored in a computer storage medium (ROM/RAM, magnetic disk, optical disk) for execution by the computing device, and in some In some cases, the steps shown or described may be performed in a different order than herein, either by fabricating them separately into individual integrated circuit modules, or by fabricating multiple modules or steps of them into a single integrated circuit module. . Therefore, the present invention is not limited to any particular combination of hardware and software.

The above content is a further detailed description of the embodiments of the present invention in combination with specific embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A method for configuring a programmable logic device, comprising:

generating a programmable logic device model file in a Valence language format, wherein the programmable logic device model file comprises a device model and an operator model; the device model comprises basic elements of the programmable logic device at the bottom layer, lattice point elements at the middle layer and a lattice point system at the top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model library comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice element;

selecting a corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determining the connection relation among the target function modules to generate a programmable logic device implementation design file in a Valence language format; generating description sentences of each routing path according to the connection relation, and identifying and constraining the key routing paths;

mapping a target function module and a connection relation in the programmable logic device implementation design file to the top layer of a device model in the programmable logic device model file, and configuring a corresponding lattice point element on the top layer;

traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file;

and writing the configuration file into the programmable logic device to be configured.

2. The programmable logic device configuration method of claim 1, wherein the device model includes identification information for uniquely identifying the device model, functional parameter configuration information of the implemented function, and corresponding interface information;

the lattice element includes configuration description information describing a position, graphic description information performing graphic representation, and structure description information describing an internal structure.

3. The programmable logic device configuration method according to claim 2, wherein the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and all implementation description information for implementing the functional module.

4. The programmable logic device configuration method of claim 3, wherein said generating a programmable logic device implementation design file comprises:

determining and defining each input/output interface according to the connection relation;

for each target function module, generating an internal implementation description statement describing each target function module to obtain a target function module example;

and generating description sentences of each routing path according to the connection relation, and identifying and constraining the key routing paths to obtain a network cable example.

5. The method for configuring a programmable logic device according to claim 4, wherein mapping the target function module and the connection relation in the implementation design file of the programmable logic device onto the top layer, and configuring the corresponding lattice point element on the top layer comprises:

sequentially compiling the device model from the bottom layer to the top layer to obtain a top layer grid model of the device model, storing the top layer grid model in a model compiling library, and compiling and storing each functional module in the operator model in the model compiling library;

compiling the programmable logic device implementation design file to obtain a target function module example and a network cable example;

finding out respective corresponding functional modules from the model compiling library according to the target functional module examples, and configuring the corresponding functional modules according to the parameters of the target functional module examples to obtain parameter configuration functional modules;

and mapping each parameter configuration function module to a grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring grid elements on the corresponding grid according to the parameters of each parameter configuration function module.

6. A programmable logic device configuration apparatus, comprising:

the model generation module is used for generating a programmable logic device model file in a Valence language format, and the programmable logic device model file comprises a device model and an operator model; the device model comprises basic elements of the programmable logic device at the bottom layer, lattice point elements at the middle layer and a lattice point system at the top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model library comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice element;

the design generation module is used for selecting a corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determining the connection relation among the target function modules to generate a programmable logic device implementation design file in a Valence language format; generating description sentences of each routing path according to the connection relation, and identifying and constraining the key routing paths;

the processing module is used for mapping the target function module and the connection relation in the programmable logic device implementation design file to the top layer of the device model in the programmable logic device model file and configuring the corresponding lattice point element on the top layer; and the configuration file is also used for traversing and extracting the configuration parameters of each lattice point element on the top layer to generate a configuration file, and writing the configuration file into the programmable logic device to be configured.

7. The programmable logic device configuration apparatus of claim 6, wherein the device model includes identification information for uniquely identifying the device model, functional parameter configuration information of the implemented function, and corresponding interface information;

the lattice element includes configuration description information describing a position, graphic description information performing graphic representation, and structure description information describing an internal structure.

8. The programmable logic device configuration apparatus of claim 7, wherein the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and all implementation description information for implementing the functional module.

9. The configuration device of claim 8, wherein the design generation module is configured to determine and define each input/output interface according to the connection relationship, generate, for each target function module, an internal implementation description statement describing each target function module to obtain a target function module instance, generate a description statement describing each routing path according to the connection relationship, and perform identification constraint on a key routing path to obtain a network cable instance.

10. The programmable logic device configuration apparatus of claim 9, wherein the processing module comprises:

the compiling submodule is used for compiling the device models from the bottom layer to the top layer in sequence to obtain top layer grid models of the device models and storing the top layer grid models in a model compiling library, and compiling and storing each functional module in the operator models in the model compiling library; the programmable logic device is also used for compiling the programmable logic device implementation design file to obtain a target function module example and a network cable example;

the mapping submodule is used for finding out the corresponding functional module from the model compiling library according to the target functional module example and configuring the corresponding functional module according to the parameter of each target functional module example to obtain a parameter configuration functional module; and the grid element configuration module is also used for mapping each parameter configuration function module to the grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring the grid element on the corresponding grid according to the parameters of each parameter configuration function module.

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