CN106657834B - ADC dynamic logic flip circuit, word line voltage selection circuit and storage unit circuit - Google Patents
ADC dynamic logic flip circuit, word line voltage selection circuit and storage unit circuit Download PDFInfo
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Abstract
本发明涉及一种ADC动态逻辑翻转电路、字线电压选择电路及存储单元电路。ADC动态逻辑翻转电路包括：第一PMOS晶体管，源极连接第一电源端，漏极连接第一节点，栅极连接于第一控制端；第一NMOS晶体管，源极连接第二电源端，漏极连接第二节点，栅极连接于第三节点；依次连接的多级翻转电路，多级翻转电路并联于第一节点与第二节点之间，上一级翻转电路的输出端连接至下一级翻转电路的输入端；输入电路，用于向第一级翻转电路提供输入信号；第一电容，连接于第一节点与第二节点之间。本发明中，逻辑翻转电路和存储单元与电源端和地端分开，存储单元的写操作与读操作或复位操作控制信号分开，避免电路翻转过程对电源端和地端产生影响，提高成像质量。
The present invention relates to an ADC dynamic logic flip circuit, a word line voltage selection circuit and a storage unit circuit. The ADC dynamic logic flip circuit comprises: a first PMOS transistor, a source connected to a first power supply terminal, a drain connected to a first node, and a gate connected to a first control terminal; a first NMOS transistor, a source connected to a second power supply terminal, a drain connected to a second node, and a gate connected to a third node; a plurality of flip circuits connected in sequence, the plurality of flip circuits are connected in parallel between a first node and a second node, and an output end of a previous flip circuit is connected to an input end of a next flip circuit; an input circuit for providing an input signal to the first flip circuit; and a first capacitor connected between the first node and the second node. In the present invention, the logic flip circuit and the storage unit are separated from the power supply terminal and the ground terminal, and the write operation of the storage unit is separated from the read operation or the reset operation control signal, so as to avoid the circuit flip process from affecting the power supply terminal and the ground terminal, thereby improving the imaging quality.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to an ADC dynamic logic flip circuit, a word line voltage selection circuit and a memory cell circuit.
Background
Most of the CMOS image sensors in common use today are output through column parallel logic circuits and stored in SRAM memories. In the existing logic circuit, the CMOS circuit realizes the logic overturning function by charging and discharging the node capacitor in the overturning process, and the NMOS transistor and the PMOS transistor are simultaneously conducted in the charging and discharging process, so that the fluctuation of a power end and a ground end can be caused. In addition, in the photosensitive process of the image sensor, a plurality of columns of logic circuits are turned over simultaneously, and meanwhile, turning signals are written into the SRAM, and the simultaneous operation of CMOS logic of a plurality of columns of ADCs can also cause fluctuation of power supply and ground, so that the image quality is affected.
Disclosure of Invention
The invention aims to provide an ADC dynamic logic flip circuit of an image sensor, which solves the problem that fluctuation of a power end and a ground end in the prior art affects imaging quality.
Another object of the present invention is to provide a word line voltage selection circuit, which separates the write operation and the read operation or the reset operation of the memory cell, and prevents the read operation and the reset operation control circuit from affecting the ADC dynamic logic flip circuit for generating the write operation control signal.
It is still another object of the present invention to provide a memory cell circuit that separates the memory cells from the power supply terminal and the ground terminal, and blocks the power supply and ground interference of the SRAM of multiple columns during the writing process.
In order to solve the above technical problems, the present invention provides an ADC dynamic logic flip circuit, comprising:
The source electrode of the first PMOS transistor is connected with the first power supply end, the drain electrode of the first PMOS transistor is connected with the first node, and the grid electrode of the first PMOS transistor is connected with the first control end;
The source electrode of the first NMOS transistor is connected with the second power supply end, the drain electrode of the first NMOS transistor is connected with the second node, and the grid electrode of the first NMOS transistor is connected with the third node;
The multi-stage turnover circuit is connected in sequence, connected in parallel between the first node and the second node, and the output end of the upper-stage turnover circuit is connected to the input end of the lower-stage turnover circuit;
an input circuit for providing an input signal to the first stage flip circuit;
and the first capacitor is connected between the first node and the second node.
Optionally, the flip-flop circuit of each stage includes:
The source electrode of the second PMOS transistor is connected with the first node, the drain electrode of the second PMOS transistor is connected with the third node, and the grid electrode of the second PMOS transistor is connected with the first control end;
the source electrode of the second NMOS transistor is connected with the second node, the drain electrode of the second NMOS transistor is connected with the third node, and the grid electrode of the second NMOS transistor is connected with the output end of the input circuit or the output end of the upper-stage flip circuit;
A source electrode of the third PMOS transistor is connected with the first node, a drain electrode of the third PMOS transistor is connected with the input end of the next-stage flip-flop circuit, and a grid electrode of the third PMOS transistor is connected with the third node;
And the source electrode of the third NMOS transistor is connected with the second node, the drain electrode of the third NMOS transistor is connected with the input end of the next stage flip circuit, and the grid electrode of the third NMOS transistor is connected with the second control end.
Optionally, the input circuit includes:
A source electrode of the fourth PMOS transistor is connected with the third power supply end, a drain electrode of the fourth PMOS transistor is connected with the fourth node, and a grid electrode of the fourth PMOS transistor is connected with the first control end;
a fifth PMOS transistor, the source electrode of which is connected with the fourth node, the drain electrode of which is connected with the first node, and the grid electrode of which is connected with the third node;
A drain electrode of the fourth NMOS transistor is connected with the fourth node, a source electrode of the fourth NMOS transistor is connected with the input end of the first-stage flip circuit, and a grid electrode of the fourth NMOS transistor is connected with an input signal;
a fifth NMOS transistor, the drain electrode of which is connected with the input end of the first stage flip circuit, the source electrode of which is connected with the second power supply end, and the grid electrode of which is connected with the second control end;
a fourth capacitor, one pole of which is connected to the fourth node, and the other pole of which is connected to the second node;
and one electrode of the fifth capacitor is connected with the input end of the first-stage flip circuit, and the other electrode of the fifth capacitor is connected with the second node.
Optionally, the voltage of the first power supply end is 1.2 v-1.5 v, the second power supply end is connected with the ground end, and the voltage of the third power supply end is 1.8 v-2.8 v.
Optionally, the capacitance value of the fourth capacitor is smaller than the capacitance value of the first capacitor, and the capacitance value of the fifth capacitor is smaller than the capacitance value of the fourth capacitor.
Optionally, the first stage flip circuit further comprises a sixth NMOS transistor, wherein the drain electrode of the sixth NMOS transistor is connected with the third node, the source electrode of the sixth NMOS transistor is connected with the second node, and the gate electrode of the sixth NMOS transistor is connected with the third control end.
Correspondingly, the invention also provides a word line voltage selection circuit, which comprises:
the word line voltage generating circuit adopts the ADC dynamic logic flip circuit, the output end of one stage flip circuit is connected to one input end of a first NOR gate through a first inverter, the output end of the next adjacent stage flip circuit is connected to the other input end of the first NOR gate, the output end of the first NOR gate provides word line voltage, and the word line voltage is connected to word line control voltage of a storage unit through a first gating circuit;
The read operation control signal and the reset operation control signal are respectively connected to two input ends of a second NOR gate, and the output end of the second NOR gate is connected to the word line control voltage of the memory cell through a second inverter and a second gating circuit.
Correspondingly, the invention also provides a memory cell circuit, which comprises:
A seventh PMOS transistor, the source electrode of which is connected with the fourth power end, the drain electrode of which is connected with the power end of the 6T memory cell, and the grid electrode of which is connected with the fourth control end;
And the drain electrode of the seventh NMOS transistor is connected with the ground end of the 6T memory cell, the source electrode of the seventh NMOS transistor is connected with the fifth power supply end, and the grid electrode of the seventh NMOS transistor is connected with the fifth control end.
Optionally, the word line control signal of the 6T memory cell is connected to the word line control voltage output by the word line voltage selection circuit.
Compared with the prior art, the invention has at least the following beneficial effects:
1) In the ADC dynamic logic flip circuit, the multi-stage flip circuit is disconnected with a first power end through a first PMOS transistor, is disconnected with a second power end through a first NMOS transistor, is disconnected with a third power end through a fourth PMOS transistor, and charges and discharges flip signals in the multi-stage flip circuit through a first capacitor and a fourth capacitor, so that the circuit cannot influence the first power end, the second power end and the third power end in the flip process, the influence on other circuits in a chip is avoided, and the imaging quality of the image sensor is improved.
) In the word line voltage selection circuit, the write operation of the memory cell circuit is separated from the control signal of the read operation or the reset operation, so that the read operation and the reset operation control circuit are prevented from influencing the ADC dynamic logic flip circuit for generating the write operation control signal.
3) In the memory cell circuit, the power supply end of the 6T memory cell is disconnected with the power supply end through the seventh PMOS transistor, and the ground end is disconnected through the seventh NMOS transistor, so that the circuit cannot influence the fourth power supply end and the fifth power supply end in the overturning process.
Drawings
FIG. 1 is a schematic diagram of an ADC dynamic logic flip circuit according to a first embodiment of the present invention;
FIG. 2 is a timing control diagram of an ADC dynamic logic flip circuit according to a first embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a word line voltage selection circuit according to a second embodiment of the present invention;
FIG. 4 is a schematic diagram of a memory cell circuit according to a third embodiment of the present invention;
FIG. 5 is a timing control diagram for implementing SRAM write and read operations in a third embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than those herein described, and those skilled in the art will readily appreciate that the present invention may be similarly embodied without departing from the spirit or essential characteristics thereof, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, which are only examples for convenience of illustration, and should not be construed as limiting the scope of the invention.
In order to make the above objects, features and advantages of the present invention more comprehensible, the following describes the ADC dynamic logic flip circuit of the present invention in detail with reference to the accompanying drawings.
The ADC dynamic logic flip circuit of the present invention is described below with reference to the accompanying drawings.
First embodiment
Referring to fig. 1, the present invention provides an ADC dynamic logic flip circuit, comprising:
the source electrode of the first PMOS transistor P1 is connected with the first power supply end VDD, the drain electrode of the first PMOS transistor P1 is connected with the first node S1, and the grid electrode of the first PMOS transistor P1 is connected with the first control end int_ sramb;
The source electrode of the first NMOS transistor N1 is connected with the second power supply end VSS, the drain electrode of the first NMOS transistor N1 is connected with the second node S2, and the grid electrode of the first NMOS transistor N3 is connected with the third node S3;
the multistage flip circuits are connected in sequence, the multistage flip circuits are connected in parallel between the first node and the second node, the output end of the upper stage flip circuit is connected to the input end of the lower stage flip circuit, the first stage flip circuit 11 and the second stage flip circuit 12 are shown in fig. 1, and the output end OUT1 of the first stage flip circuit 11 is connected to the input end of the second stage flip circuit 12;
An input circuit 13, the input circuit 13 providing an input signal to the first stage flip-flop circuit 11 according to its input signal cmp_out;
the first capacitor C1 is connected between the first node S1 and the second node S2.
Specifically, referring to fig. 1, the flip-flop circuit includes:
A second PMOS transistor P2, having a source connected to the first node S1, a drain connected to the third node S3, and a gate connected to the first control terminal int_ sramb;
the source electrode of the second NMOS transistor N2 is connected with the second node S2, the drain electrode of the second NMOS transistor N2 is connected with the third node S3, and the grid electrode of the second NMOS transistor N2 is connected with the output end of the upper-stage flip circuit or connected to the input circuit;
A source electrode of the third PMOS transistor P3 is connected with the first node S1, a drain electrode of the third PMOS transistor P3 is connected with the input end of the next-stage flip-flop circuit, and a grid electrode of the third PMOS transistor P is connected with the third node S3;
a source electrode of the third NMOS transistor N3 is connected with the second node S2, a drain electrode of the third NMOS transistor N3 is connected with the input end of the next-stage flip circuit, and a grid electrode of the third NMOS transistor N is connected with the second control end int_sram;
The first control terminal int_ sramb and the second control terminal int_sram are two signals with opposite phases.
In addition, the flip-flop circuit of each stage further comprises a second capacitor (not shown in the figure), the second capacitor is connected between the third node S3 and the second node S2, the capacitance value of the first capacitor C1 is larger than that of the second capacitor, and the second capacitor is used for maintaining the potential of the third node S3 and adjusting the RC delay on the third node S3. The flip-flop circuit of each stage further comprises a third capacitor (not shown in the figure), the third capacitor is connected between the output end of the flip-flop circuit of the stage and the first node S1, the capacitance value of the first capacitor C1 is larger than that of the third capacitor, and the third capacitor is used for maintaining the potential of the output end and adjusting the RC delay on the output end. It should be noted that, since the capacitance values of the second capacitor and the third capacitor are relatively small and can be obtained through parasitic capacitance in the circuit layout, it is not necessary to add these two capacitors in the schematic diagram.
With continued reference to fig. 1, the input circuit 13 includes:
A source electrode of the fourth PMOS transistor P4 is connected to the third power supply terminal AVDD, a drain electrode thereof is connected to the fourth node S4, and a gate electrode thereof is connected to the first control terminal int_ sramb;
A fifth PMOS transistor P5, having a source connected to the fourth node S4, a drain connected to the first node S1, and a gate connected to the third node S3;
A fourth capacitor C4, wherein one pole of the fourth capacitor C4 is connected to the fourth node S4, the other pole is connected to the second node S2, and a capacitance value of the fourth capacitor is smaller than that of the first capacitor;
a fourth NMOS transistor N4, having a drain connected to the fourth node S4, a source connected to a fifth node (an input terminal of the first stage flip-flop 11), a gate connected to an input signal cmp_out, the input signal cmp_out being an output signal of a comparator in the ADC of the previous stage;
A fifth NMOS transistor N5 having a drain connected to a fifth node (an input terminal of the first stage flip circuit 11), a source connected to the second power supply terminal VSS, and a gate connected to the second control terminal int_sram;
And a fifth capacitor C5, wherein one pole of the fifth capacitor C5 is connected to the fifth node S5 (the input end of the first stage flip-flop 11), and the other pole is connected to the second node S2.
In this embodiment, the output signal cmp_out of the previous stage comparator circuit has a high level of 2.8V, the voltage of the first power supply terminal VDD is 1.2V to 1.5V, for example, 1.2V, the second power supply terminal VSS is connected to the ground terminal, and the voltage of the third power supply terminal AVDD is 1.8V to 2.8V, for example, 1.8V. In order to inhibit the leakage problem, all MOS tubes adopt a thick oxygen structure.
Referring to fig. 1 and 2, the operation of the ADC dynamic logic flip-flop of the present invention is as follows:
First, at time t1, the first control terminal int_ sramb is a low level signal, the second control terminal int_sram is a high level signal, so that the first PMOS transistor P1, the second PMOS transistor P2, and the fourth PMOS transistor P4 are turned on, the voltage of the fourth node S4 is pulled to the voltage value of the third power supply terminal AVDD, the voltage vo1 of the first node S1 and the third node S3 is pulled to the voltage value of the first power supply terminal VDD, the first NMOS transistor N1 and the fifth NMOS transistor N5 are turned on, the voltage of the second node S2 and the fifth node S5 is pulled to the voltage of the second power supply terminal VSS, the third transistor N3 is turned on, and the voltage vo2 of the output terminal OUT1 is VSS. Meanwhile, the PMOS transistor P2' of the second stage flip-flop is turned on, the voltage vo3 of the node S3' is VDD, the NMOS transistor N3' is turned on, and the potential vo4 of the output terminal OUT2 is VSS. At this time, the source terminal of the fifth PMOS transistor is 1.8V, the drain and gate terminals are 1.2V, and the fifth PMOS transistor is in an on-edge state. .
Thereafter, at time t2, the first control terminal int_sram is at a low level, the second control terminal int_ sramb is at a high level, so that the first PMOS transistor P1, the fourth PMOS transistor P4, and the fifth NMOS transistor N5 are all turned off, the first capacitor C1 maintains the voltage between the first node S1 and the second node S2, the fourth capacitor C4 maintains the voltage between the fourth node S4 and the second node S2, and the multi-stage flip circuits 11, 12 are disconnected from the first power supply terminal VDD and the third power supply terminal AVDD. During this time, the voltage on the fourth node S4 is gradually reduced from 1.8V, and the voltage on the first node S1 is correspondingly increased from 1.2V due to the weak on state of the fifth PMOS transistor P5. At the same time, the second PMOS transistor P2 and the third NMOS transistor N3 also enter the off state.
Next, at time t3, the potential of the input signal cmp_out gradually increases to 2.8V, so that the fourth NMOS transistor N4 is turned on, the voltage of the fifth node is gradually pulled up by the fourth node, so that the second NMOS transistor N2 is turned on, the third node S3 is pulled up to VSS by the second node S2, the first NMOS transistor N1 is turned off, and the second node S2 is disconnected from the second power supply terminal VSS and maintained at the VSS voltage.
After the voltage vo1 of the third node S3 becomes low, the fifth PMOS transistor P5 is fully turned on so that the voltages of the first node S1 and the fourth node S4 are equal, and the voltage is stabilized at about 1.4V. At the same time, the third PMOS transistor P3 is turned on, the voltage vo2 of the output terminal OUT1 gradually rises to a high level, and the output terminal OUT1 of the first-stage flip-flop circuit 11 is output to the input terminal (gate of the NMOS transistor N2') of the second-stage flip-flop circuit 12. The second NMOS transistor N2' in the second stage flip-flop 12 is turned on, the voltage vo3 on the node S3' is pulled low, the PMOS transistor P3' is turned on, and the potential of the output terminal OUT2 is pulled high, so that the potential of vo4 is pulled high.
In addition, the first stage flip-flop 11 in this embodiment further includes a sixth NMOS transistor N6 having a drain connected to the third node S3, a source connected to the second node S2, and a gate connected to the third control terminal set. After the end of the writing phase, a high level pulse signal is provided at the third control terminal set, so that the circuit column which has not received the cmp_out high level signal in the writing phase can complete the flipping, which is equivalent to the filling of a bright spot in the image sensor. After the write and set operations are all completed, cmp_out goes low and the circuit returns to the state at time t 1.
Second embodiment
Referring to fig. 2 and 3, the present invention further provides a word line voltage selection circuit, which includes two branches of a word line voltage WL for controlling a write operation and a control signal sel or a control signal rst for controlling a read operation, controls gating of the two branches, outputs a corresponding word line control voltage WLO, and outputs the corresponding word line control voltage WLO to a memory cell circuit, thereby controlling a read/write state of a memory cell. In this embodiment, the word line voltage WL of the memory cell performing the write operation is separated from the sel signal of the read operation and the rst signal of the reset operation, the first gate circuit 33 and the second gate circuit 34 are selected to be turned on by the write operation control signals write_n and write_d, the word line control voltage WLO is connected to the write operation voltage WL in the write operation stage, and the word line control voltage WLO is connected to the read operation control signal sel or the reset operation control signal rst in the non-write operation stage, so that the process of the write operation and the read operation or the reset operation of the memory cell are separated, and the influence of the circuits of the read operation and the reset operation on the ADC dynamic logic flip circuit of the write operation is avoided.
The word line voltage generating circuit 20 provides a write operation voltage WL, the write operation voltage WL is connected to a word line control voltage WLO of the memory cell through a first strobe circuit, the output end of the first stage flip circuit of the ADC dynamic logic flip circuit is connected to an input end of the first nor gate through a first inverter, the output end of the next adjacent stage flip circuit is connected to another input end of the first nor gate, and the output end of the first nor gate generates the write operation voltage WL. Specifically, referring to fig. 2 and 3, the output terminal vo2 of the first stage flip circuit 11 in the word line voltage generating circuit 20 is connected to one input terminal of the first nor gate 22 through the first inverter 21, the output terminal vo4 of the second stage flip circuit 12 is connected to the other input terminal of the first nor gate 22, and the output terminal of the first nor gate 22 is connected to the write operation voltage WL. After cmp_out goes high, a high pulse signal is formed at the output of nor gate 22 as write operation signal WL by a flip-flop delay between vo2 and vo 4.
It should be noted that, each of the word line control voltages WLO is connected to several tens of memory cells of the SRAM, so that its load capacitance is relatively large, and when the write operation signal WL becomes a high level pulse, it is connected to WLO through the first strobe circuit to charge the word line control terminals of the connected several tens of memory cells, so that the voltage of the first node S1 of the ADC dynamic logic flip circuit is greatly lowered. In order to prevent the logic flip circuit from not working normally due to the too low voltage on the S1 caused by the pulling, the fifth PMOS transistor in the ADC dynamic logic flip circuit is completely conducted to transfer the higher voltage on the fourth node S4 to the first node S1, the voltage on the first node S1 is increased in advance, and the ADC dynamic logic flip circuit is ensured to maintain a correct working state under the condition of low voltage pulling. This process is shown with reference to fig. 2.
With continued reference to fig. 3, the read operation control signal sel and the reset operation control signal rst are respectively connected to two input terminals of the second nor gate 31, and an output terminal of the second nor gate 31 is connected to the word line control voltage WLO of the memory cell through the second inverter 32 and the second gate circuit 34.
Third embodiment
Referring to fig. 4 and 5, the present embodiment provides a memory cell circuit including a seventh PMOS transistor P7 having a source connected to the fourth power terminal VDD ', a drain connected to the power terminal (the sixth node S6) of the 6T memory cell 40, a gate connected to the fourth control terminal bitcell _ intb, and a seventh NMOS transistor N7 having a drain connected to the ground terminal (the seventh node S7) of the 6T memory cell 40, a source connected to the fifth power terminal VSS', and a gate connected to the fifth control terminal bitcell _int. The fourth control terminal bitcell _ intb and the fifth control terminal bitcell _int are a pair of opposite control signals.
Wherein the 6T memory unit 40 includes:
an eighth PMOS transistor P8, having a source connected to the sixth node S6, a drain connected to the eighth node S8, and a gate connected to the ninth node S9;
An eighth NMOS transistor having a source connected to the seventh node S7, a drain connected to the eighth node S8, and a gate connected to the ninth node S9;
A ninth PMOS transistor P9, having a source connected to the sixth node S6, a drain connected to the ninth node S9, and a gate connected to the eighth node S8;
A ninth NMOS transistor N9 having a source connected to the seventh node S7, a drain connected to the ninth node S9, and a gate connected to the eighth node S8;
a tenth NMOS transistor N10, wherein a drain of the tenth NMOS transistor N10 is connected to the first bit line BL, a source is connected to the eighth node S8, and a gate is connected to the word line control voltage WLO output from the word line voltage selection circuit;
An eleventh NMOS transistor N11, the drain of the eleventh NMOS transistor N11 being connected to the second bit line BLb, the source being connected to the ninth node S9, and the gate being connected to the word line control voltage WLO outputted from the word line voltage selection circuit.
In the write operation stage, the voltage difference between the fourth power terminal VDD 'and the fifth power terminal VSS' does not have to be the power supply voltage. In this embodiment, the fourth power terminal VDD 'takes 450mV and the fifth power terminal VSS' takes 150mV. Referring to fig. 4 and 5, the sixth node S6 and the seventh node S7 are precharged to 450mV and 150mV, respectively, during the reset phase of the SRAM, and then the seventh PMOS transistor P7 disconnects the power terminal of the memory cell 40 from the fourth power terminal, and the seventh NMOS transistor N7 disconnects the ground terminal of the memory cell 40 from the fifth power terminal. During the writing operation, the values of the high voltage and the low voltage of BL and BLb are controlled, so that the eighth node S8 and the ninth node S9 also keep changing between 150mV and 450mV, and after the writing operation is completed, the eighth node S8 and the ninth node S9 are respectively 450mV and 150mV. After a period of time, the circuit enters a read operation stage, changes the voltages of the fourth control terminal bitcell _ intb and the fifth control terminal bitcell _int so that the seventh PMOS transistor P7 and the seventh NMOS transistor N7 are turned on, the fourth power terminal VDD 'is pulled to the power supply voltage, and the fifth power terminal VSS' is put to the ground voltage, and although the voltage difference between the eighth node S8 and the ninth node S9 decreases after a period of time due to the switching effect and the influence of the leakage, it is sufficient to pull the fourth power terminal VDD 'to the power supply voltage and pull the eighth node S8 and the ninth node S9 to the power supply voltage and the ground voltage from 450mV and 150mV after the fifth power terminal VSS' is put to the ground voltage, respectively, as long as the voltage difference is ensured to be above 200 mV.
In summary, in the present invention, since the whole writing operation process is controlled by dynamic logic, the power supply terminal and the ground terminal are disconnected, and thus other circuits are not affected. In addition, the writing operation of the memory cell is also performed under a small voltage difference, so that the influence of the overturn in the memory cell on other modules is greatly reduced, and the pulling-up action on the nodes in the memory cell when the data is finally read is performed when all writing operations are completed, so that the mutual influence among the memory cells is also reduced. In this series of ways, the image quality of the image sensor is improved.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
Claims (12)
1. A memory cell circuit, comprising:
A 6T memory unit, a seventh PMOS transistor and a seventh NMOS transistor respectively arranged at the power end and the ground end of the 6T memory unit,
A seventh PMOS transistor, the source electrode of which is connected with the fourth power end, the drain electrode of which is connected with the power end of the 6T memory cell, and the grid electrode of which is connected with the fourth control end;
A seventh NMOS transistor, the drain electrode of which is connected with the ground end of the 6T memory cell, the source electrode of which is connected with the fifth power end, and the grid electrode of which is connected with the fifth control end;
Wherein the fourth control terminal and the fifth control terminal are controlled by a pair of opposite control signals.
2. The memory cell circuit of claim 1, wherein the word line control signal of the 6T memory cell is connected to the word line control voltage output by the word line voltage selection circuit, the 6T memory cell comprises an eighth PMOS transistor having a source connected to the sixth node, a drain connected to the eighth node, and a gate connected to the ninth node;
An eighth NMOS transistor, wherein the source electrode of the eighth NMOS transistor is connected with the seventh node, the drain electrode of the eighth NMOS transistor is connected with the eighth node, and the grid electrode of the eighth NMOS transistor is connected with the ninth node;
A ninth PMOS transistor, wherein a source of the ninth PMOS transistor is connected to the sixth node S6, a drain of the ninth PMOS transistor is connected to the ninth node, and a gate of the ninth PMOS transistor is connected to the eighth node;
A ninth NMOS transistor, wherein the source electrode of the ninth NMOS transistor is connected with the seventh node, the drain electrode of the ninth NMOS transistor is connected with the ninth node, and the grid electrode of the ninth NMOS transistor is connected with the eighth node;
a tenth NMOS transistor having a drain connected to the first bit line, a source connected to the eighth node, and a gate connected to the word line control voltage output from the word line voltage selection circuit;
And an eleventh NMOS transistor having a drain connected to the second bit line, a source connected to the ninth node, and a gate connected to the word line control voltage output from the word line voltage selection circuit.
3. The memory cell circuit of claim 2, wherein the sixth node and seventh node are respectively precharged during a reset phase, and then the memory cell circuit is disconnected from the fourth power supply terminal and the fifth power supply terminal.
4. A memory cell circuit according to claim 2 or 3, wherein the eighth node and the ninth node are kept changed between the potentials of the precharge of the sixth node and the seventh node by controlling the values of the high and low voltages of the first bit line and the second bit line during the write operation.
5. The memory cell circuit of claim 2,3 or 4, wherein after completion of a write operation, the circuit enters a read phase to turn on the memory cell circuit with the fourth power supply terminal and the fifth power supply terminal.
6. The memory cell circuit of claim 1, wherein the word line voltage selection circuit comprises,
Word line voltage generating circuit, wherein the output end of the first-stage flip circuit in the word line voltage generating circuit passes through
The first inverter is connected to one input end of a first NOR gate, the output end of an adjacent next-stage flip circuit is connected to the other input end of the first NOR gate, and the output end of the first NOR gate provides word line voltage;
A first gate circuit through which a word line voltage is connected to a word line control voltage of the memory cell circuit;
The second NOR gate, the read operation control signal and reset operation control signal are connected to two input ends of the second NOR gate respectively;
The output end of the second NOR gate is connected to the word line control voltage of the memory cell circuit through the second inverter and the second gating circuit.
7. The memory cell circuit of claim 6, wherein the word line voltage generation circuit comprises an ADC dynamic logic flip circuit comprising:
The source electrode of the first PMOS transistor is connected with the first power supply end, the drain electrode of the first PMOS transistor is connected with the first node, and the grid electrode of the first PMOS transistor is connected with the first control end;
The source electrode of the first NMOS transistor is connected with a second power supply end, the drain electrode of the first NMOS transistor is connected with a second node, and the grid electrode of the first NMOS transistor is connected with a third node, wherein the second power supply end is different from the first power supply end;
The multi-stage turnover circuit is connected in sequence, connected in parallel between the first node and the second node, and the output end of the upper-stage turnover circuit is connected to the input end of the lower-stage turnover circuit;
an input circuit for providing an input signal to the first stage flip circuit;
and the first capacitor is connected between the first node and the second node.
8. The memory cell circuit of claim 7, wherein the flip-flop circuit of each stage comprises:
The source electrode of the second PMOS transistor is connected with the first node, the drain electrode of the second PMOS transistor is connected with the third node, and the grid electrode of the second PMOS transistor is connected with the first control end;
the source electrode of the second NMOS transistor is connected with the second node, the drain electrode of the second NMOS transistor is connected with the third node, and the grid electrode of the second NMOS transistor is connected with the output end of the input circuit or the output end of the upper-stage flip circuit;
A source electrode of the third PMOS transistor is connected with the first node, a drain electrode of the third PMOS transistor is connected with the input end of the next-stage flip-flop circuit, and a grid electrode of the third PMOS transistor is connected with the third node;
And the source electrode of the third NMOS transistor is connected with the second node, the drain electrode of the third NMOS transistor is connected with the input end of the next stage flip circuit, and the grid electrode of the third NMOS transistor is connected with the second control end.
9. The memory cell circuit of claim 7 or 8, wherein the input circuit comprises:
A source electrode of the fourth PMOS transistor is connected with the third power supply end, a drain electrode of the fourth PMOS transistor is connected with the fourth node, and a grid electrode of the fourth PMOS transistor is connected with the first control end;
a fifth PMOS transistor, the source electrode of which is connected with the fourth node, the drain electrode of which is connected with the first node, and the grid electrode of which is connected with the third node;
A drain electrode of the fourth NMOS transistor is connected with the fourth node, a source electrode of the fourth NMOS transistor is connected with the input end of the first-stage flip circuit, and a grid electrode of the fourth NMOS transistor is connected with an input signal;
A fifth NMOS transistor, wherein the drain electrode of the fifth NMOS transistor is connected with the input end of the first-stage flip circuit, the source electrode of the fifth NMOS transistor is connected with the second power supply end, and the grid electrode of the fifth NMOS transistor is connected with the second control end;
a fourth capacitor, one pole of which is connected to the fourth node, and the other pole of which is connected to the second node;
and one electrode of the fifth capacitor is connected with the input end of the first-stage flip circuit, and the other electrode of the fifth capacitor is connected with the second node.
10. The memory cell circuit of claim 9, wherein the voltage of the first power supply terminal is 1.2v to 1.5v, the second power supply terminal is connected to the ground terminal, and the voltage of the third power supply terminal is 1.8v to 2.8v.
11. The memory cell circuit of claim 9, wherein the fourth capacitor has a capacitance less than the first capacitor, and wherein the fifth capacitor has a capacitance less than the fourth capacitor.
12. The memory cell circuit of claim 8 wherein the first stage flip-flop further comprises a sixth NMOS transistor having a drain connected to the third node, a source connected to the second node, and a gate connected to a third control terminal.
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| CN201611257003.9A CN106657834B (en) | 2016-12-30 | 2016-12-30 | ADC dynamic logic flip circuit, word line voltage selection circuit and storage unit circuit |
| CN202411614246.8A CN119729248A (en) | 2016-12-30 | 2016-12-30 | ADC dynamic logic flip circuit, word line voltage selection circuit and memory cell circuit |
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| CN104616691B (en) * | 2015-01-31 | 2018-01-26 | 上海华虹宏力半导体制造有限公司 | Word line voltage generation circuit and memory |
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| CN101110420A (en) * | 2006-07-19 | 2008-01-23 | 国际商业机器公司 | Method and apparatus for reducing integrated circuit leakage current |
| CN101436426A (en) * | 2007-11-14 | 2009-05-20 | 恩益禧电子股份有限公司 | Semiconductor storage device and method of controlling the same |
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