CN106656121B - A sub-nanosecond digital delayed pulse generating device and working method - Google Patents
A sub-nanosecond digital delayed pulse generating device and working method Download PDFInfo
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- CN106656121B CN106656121B CN201611074667.1A CN201611074667A CN106656121B CN 106656121 B CN106656121 B CN 106656121B CN 201611074667 A CN201611074667 A CN 201611074667A CN 106656121 B CN106656121 B CN 106656121B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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Abstract
The invention relates to a subnanosecond digital delay pulse generating device which comprises a trigger signal generating module, a temperature compensation crystal oscillator, a touch screen and a communication module, wherein the trigger signal generating module, the temperature compensation crystal oscillator, the touch screen and the communication module are respectively connected with an FPGA module, the FPGA module is connected with a delay output port through a ramp circuit module and an output driving module, the ramp circuit module is connected with the FPGA module through a capacitor discharge compensation module, and the output driving module is connected with the FPGA module. The self-triggering mode has an automatic one-key calibration function, automatically calibrates each channel to the optimal configuration, and solves the problem of large manual calibration error. The external trigger mode has a capacitor self-discharge compensation function, and reduces the influence of capacitor self-discharge on precision in a digital delay stage. The trigger signal generating module conditions trigger signals with different frequencies, and key technical indexes are improved. The output shake of the external trigger mode is controlled within 0.8ns, and the self-trigger output shake is controlled within 0.1 ns. The circuit has the advantages of simple structure, small volume, light weight, low power consumption, low cost and simple and convenient operation.
Description
Technical Field
The invention relates to a digital delay pulse generating device, in particular to a subnanosecond digital delay pulse generating device and a working method thereof.
Background
The subnanosecond digital delay pulse generating device is widely applied to the fields of laser targeting, framing cameras, laser-induced breakdown spectroscopy analysis instruments, flight time secondary ion mass spectrometry instruments, raman spectroscopy instruments and the like. The device provides accurate working time sequence (output shake is smaller than 1 ns) for key parts of the whole machine, and the index of the delay device influences the performance of the whole instrument.
CN 103308492B discloses a synchronous machine for laser-induced breakdown spectroscopy, which uses the capacitor charging principle, FPGA and niosII soft core technology to emphasize the basic functions of the delay device, and has the advantages of simple circuit structure and small volume. But still have the following disadvantages: 1. the parameters of each channel of the synchronous machine are required to be manually calibrated by an oscilloscope, the calibration error is large, and the steps are tedious and time-consuming; 2. in the digital delay stage, the charging switch is closed, but the capacitor voltage cannot be kept unchanged due to the self-discharging phenomenon of the capacitor, so that the delay precision is affected; 3. the synchronous machine trigger signal generation module sorts the time of the signal, and is influenced by the signal voltage, which leads to errors in the inherent delay of the synchronous machine.
Disclosure of Invention
The invention aims to provide a subnanosecond digital delay pulse generating device aiming at the defects of the prior art;
another object of the invention is to provide a method of operating a digital delayed pulse generating device of the sub-nanosecond scale.
The invention aims at realizing the following technical scheme:
The sub-nanosecond digital delay pulse generation device comprises a trigger signal generation module (2), a temperature compensation crystal oscillator (3), a touch screen (7) and a communication module (8), wherein the trigger signal generation module (2), the temperature compensation crystal oscillator (3), the touch screen (7) and the communication module (8) are respectively connected with an FPGA module (4), and the FPGA module (4) is connected with a delay output port (9) through a ramp circuit module (5) and an output driving module (6), and is characterized in that the ramp circuit module (5) is connected with the FPGA module (4) through a capacitor discharge compensation module (10), and the output driving module (6) is connected with the FPGA module (4);
the trigger signal generation module (2) consists of an amplifying and shaping circuit (11), a voltage follower circuit (12), a high-speed comparator (13), a D/A (14) and a high-speed A/D (15); the amplifying and shaping circuit (11) is connected with the high-speed comparator (13) through the high-speed comparator (13), the FPGA module (4) and the D/A (14), and the voltage follower circuit (12) is connected with the FPGA module (4) through the high-speed A/D (15);
The FPGA module (4) consists of a jitter compensation circuit (17), an A channel digital delay (18), a B channel digital delay (19), a C channel digital delay (20), a D channel digital delay (21), a NIOS II soft core (22) and an automatic calibration unit (23), wherein the jitter compensation circuit (17) is connected with the slope circuit module (5) through the A channel digital delay (18), the B channel digital delay (19), the C channel digital delay (20) and the D channel digital delay (21), the jitter compensation circuit (17) is connected with the slope circuit module (5), and the NIOS II soft core (22) is connected with the NIOS II soft core (22) through the slope circuit module (5), the output driving module (6) and the automatic calibration unit (23);
The ramp circuit module (5) consists of a T0 channel ramp circuit (24), an A channel ramp circuit (25), a B channel ramp circuit (26), a C channel ramp circuit (27) and a D channel ramp circuit (28), wherein the T0 channel ramp circuit (24), the A channel ramp circuit (25), the B channel ramp circuit (26), the C channel ramp circuit (27) and the D channel ramp circuit (28) are respectively connected with the output driving module (6);
The output driving module (6) is composed of a T0 channel output driving module (34), an A channel output driving module (35), a B channel output driving module (36), a C channel output driving module (37) and a D channel output driving module (38), wherein the T0 channel output driving module (34), the A channel output driving module (35), the B channel output driving module (36), the C channel output driving module (37) and the D channel output driving module (38) are respectively and correspondingly connected with T0 and A, B, C, D output ports in the delay output port (9).
The working method of the subnanosecond digital delay pulse generating device comprises the following steps of externally triggering and self-triggering:
a. Starting a digital delay pulse generating device, setting delay time through a touch screen, selecting an external trigger working mode, when an external trigger signal is detected,
B. Firstly, shaping the signal by a trigger signal generating module 2;
c. Secondly, the output is sent to an FPGA module, the module generates delay time by utilizing a ramp circuit module 5 and a temperature compensation crystal oscillator 3,
D. Then, the capacitor discharge compensation module 10 compensates the charging capacitor, and the output driving module 6 provides driving capability and polarity selection function of the output signal;
e. finally transmitting to an output port;
f. selecting a self-triggering operating mode:
g. firstly, checking the precision of a digital delay pulse generating device, such as the change of device parameters and working environment, and starting automatic calibration;
h. The FPGA module 4 and the temperature compensation crystal oscillator module 3 finish digital delay;
i. After the digital delay is completed, a starting signal is sent to the inclined slope circuit module 5 to start analog delay;
j. After the analog delay is completed, a start signal is sent to the driving output module 6, and the driving capability and polarity selection function of the output signal are provided by the output driving module 6.
The beneficial effects are that: in the invention, each channel of the digital delay pulse generating device has own independent configuration parameters in consideration of the fact that the parameter indexes of the components cannot be completely consistent. The self-triggering mode has an automatic one-key calibration function, and automatically calibrates each channel to the optimal configuration, thereby solving the problem of large manual calibration error. The external trigger mode has the function of capacitor self-discharge compensation, reduces the influence of capacitor self-discharge on the precision in the digital delay stage, and has high precision of long-time delay. The trigger signal generation module regulates the trigger signals with different frequencies in the same time, eliminates the redundant function and improves the key technical index. The output shaking of the external trigger mode is controlled within 0.8ns, and the shaking of the self-trigger output is controlled within 0.1ns, so that the requirements of most instruments and fields are met. The circuit has the advantages of simple structure, small volume, light weight, low power consumption, low cost and simple and convenient operation.
Drawings
FIG. 1 is a block diagram of a sub-nanosecond digital delay pulse generator
Fig. 2 is a block diagram of the trigger signal generation module 2 in fig. 1
FIG. 3 is a block diagram of the FPGA module 4 of FIG. 1
Fig. 4 is a block diagram of the ramp circuit module 5 in fig. 1
FIG. 5 is a schematic diagram of the ramp circuit of FIG. 1
FIG. 6 is a block diagram of the output driving module in FIG. 1
FIG. 7 is a schematic diagram of the capacitor discharge compensation in FIG. 1
FIG. 8 is a graph showing the capacitance-voltage variation of the ramp circuit of FIG. 1
FIG. 9 is a schematic diagram of an automatic calibration unit
1 External trigger input port, 2 trigger signal generation module, 3 temperature compensation crystal oscillator, 4FPGA module, 5 ramp circuit module, 6 output driving module, 7 delay output port, 8 communication module, 9 touch screen, 10 capacitor discharge compensation module 10, 11 amplifying shaping circuit, 12 voltage follower circuit, 13 high speed comparator, 14D/a,15 high speed a/D,17 jitter compensation circuit, 18A channel digital delay, 19B channel digital delay, 20C channel digital delay, 21D channel digital delay, 22NIOS ii soft core, 23 auto calibration unit, 24T0 channel ramp circuit, 25A channel ramp circuit, 26B channel ramp circuit, 27C channel ramp circuit, 28D channel ramp circuit, 29 constant current source circuit, 30 charge/discharge switch, 31 charge capacitor, 32D/a,34T0 channel output driving module, 35A channel output driving module, 36B channel output driving module, 37C channel output driving module, 38D channel output driving module, 39A/D,40 voltage follower
Detailed Description
The following is a further detailed description with reference to the drawings and examples:
The sub-nanosecond digital delay pulse generating device comprises a trigger signal generating module 2, a temperature compensation crystal oscillator 3, a touch screen 7 and a communication module 8 which are respectively connected with an FPGA module 4, wherein the FPGA module 4 is formed by connecting a slope circuit module 5 and an output driving module 6 with a delay output port 9, the slope circuit module 5 is connected with the FPGA module 4 by a capacitor discharge compensation module 10, and the output driving module 6 is formed by connecting the FPGA module 4.
The trigger signal generation module 2 is formed by connecting an amplifying and shaping circuit 11 with a high-speed comparator 13 through a high-speed comparator 13, an FPGA module 4 and a D/A14, and connecting a voltage follower circuit 12 with the FPGA module 4 through a high-speed A/D15.
The jitter compensation circuit 17 is connected with the ramp circuit module 5 through an A channel digital delay 18, a B channel digital delay 19, a C channel digital delay 20 and a D channel digital delay 21 respectively, the jitter compensation circuit 17 is connected with the ramp circuit module 5, and the NIOS II soft core 22 is connected with the NIOS II soft core 22 through the ramp circuit module 5, the output driving module 6 and the automatic calibration unit 23.
The ramp circuit block 5 includes a T0-channel ramp circuit 24, an a-channel ramp circuit 25, a B-channel ramp circuit 26, a C-channel ramp circuit 27, and a D-channel ramp circuit 28, which are connected to the output driving block 6, respectively.
The output driving module 6 includes a T0 channel output driving module 34, an a channel output driving module 35, a B channel output driving module 36, a C channel output driving module 37, and a D channel output driving module 38, which are correspondingly connected with the T0 and A, B, C, D output ports in the delay output port 9.
The communication modes include two modes of Ethernet (LAN) and serial port (RS 232).
The subnanosecond digital delay pulse generating device can also remove a touch screen, and a communication module in the device is connected with a computer to acquire or set delay time on the computer.
The working method of the subnanosecond digital delay pulse generating device comprises the following steps of externally triggering and self-triggering:
a. Starting a digital delay pulse generating device, setting delay time through a touch screen, selecting an external trigger working mode, when an external trigger signal is detected,
B. Firstly, shaping the signal by a trigger signal generating module 2;
c. Secondly, the output is sent to an FPGA module, the module generates delay time by utilizing a ramp circuit module 5 and a temperature compensation crystal oscillator 3,
D. Then, the capacitor discharge compensation module 10 compensates the charging capacitor, and the output driving module 6 provides driving capability and polarity selection function of the output signal;
e. finally transmitting to an output port;
f. selecting a self-triggering operating mode:
g. firstly, checking the precision of a digital delay pulse generating device, such as the change of device parameters and working environment, and starting automatic calibration;
h. The FPGA module 4 and the temperature compensation crystal oscillator module 3 finish digital delay;
i. After the digital delay is completed, a starting signal is sent to the inclined slope circuit module 5 to start analog delay;
j. After the analog delay is completed, a start signal is sent to the driving output module 6, and the driving capability and polarity selection function of the output signal are provided by the output driving module 6.
As shown in FIG. 1, the sub-nanosecond digital delay pulse generating device consists of ten parts, namely an external trigger input port, a trigger signal generating module, a temperature compensation crystal oscillator, an FPGA module, a ramp circuit module, an output driving module, a delay output port, a communication module, a touch screen, a capacitor discharge compensation module and the like.
The time delay function mainly comprises three parts: fixed delay, digital delay, and analog delay. The fixed delay refers to the inherent delay when the circuit is generated; the digital delay is delay time generated by a digital chip FPGA and a temperature compensation crystal oscillator; the analog delay refers to the delay time generated by the ramp circuit. Due to factors such as differences of analog devices, the fixed delay of each synchronous machine device cannot be guaranteed to be identical, and the difference of digital delay and analog delay is combined at the moment to ensure that the delay time of a T0 port and external trigger signals is fixed and is 38ns. The delay time of the output port A, the output port B, the output port C and the output port D relative to the output port T0 is set in a programmable manner, the adjustment range is 0-10s, and the steps are 0.1ns.
Fig. 2 is a diagram of the trigger signal generation module 2: the module consists of an amplifying and shaping circuit 11, a high-speed comparator 13, a voltage follower circuit 12, a high-speed A/D15 and a high-speed D/A14 which are formed by a field effect transistor and an impedance matching circuit, converts an external trigger signal into a signal conforming to LVCOMS level (3.3V) and inputs the signal into the FPGA module 4. The time of the external trigger signal passing through the amplifying and shaping circuit 11 and the high-speed comparator 13 is influenced by the trigger signal voltage, the high-speed A/D15 collects the trigger signal voltage and transmits the trigger signal voltage to the FPGA module 4, the FPGA module 4 automatically adjusts the reference voltage of the high-speed comparator D/A14 according to the magnitude of the trigger voltage, the delay of the trigger signal generating module 2 is a fixed value, the influence of the trigger signal voltage is avoided, and the delay precision is improved.
Fig. 3 is a block diagram of FPGA module 4: in the external trigger working mode, the shaped external trigger signal 16 and the shaped temperature compensation crystal oscillator signal (100 MHz) enter a jitter compensation circuit 17 in the FPGA module 4 to generate a control signal for the digital delay and ramp circuit module 5. The digital delay circuit is positioned in the FPGA chip and comprises digital delay of four channels, and the principle of each channel is the same, and the digital delay circuit is a counter taking temperature compensation crystal oscillation as a clock signal. After the control signal arrives, the counter measures the delay time by taking 10ns as a unit, and stops counting when the required time value is reached, and outputs a counting stop indication signal. In the self-triggering mode, an external triggering signal is not needed, and the counter generated by the 100MHz temperature compensation crystal oscillator directly completes digital time delay. After the digital delay is completed, a starting signal is sent to the slope circuit module to start analog delay.
Fig. 4 is a block diagram of a ramp circuit: a ramp circuit comprising five channels, each channel having the same principle, the ramp circuit principle being based on fig. 5: the constant current source circuit 29 charges the capacitor, the capacitor voltage changes linearly with time, and when the voltage value set by D/a (i.e., the control signal generated by the FPGA module 4) is reached, the comparator inverts to form an output signal. The capacitor charging voltage is linearly changed within the range of 0.1V to 3.1V, deltaV=3.0V, the charging time is 50ns, and when the noise voltage amplitude of the input end of the comparator is smaller than 6mV, the delay time precision can reach 50 ns/(3.0V/6 mV) =0.1 ns.
Jitter compensation circuit 17 in FPGA module: the time difference between the external trigger signal and the rising edge of the temperature compensation crystal oscillator clock signal is random, and the variation range is 0-10ns, which is called trigger input time jitter. If the preset total delay time is less than 50ns, the delay requirement can be met only by using a ramp circuit, digital delay is not needed, and the triggering input time jitter does not influence the final output. If the preset delay time is greater than 50ns, jitter compensation is required: when the external trigger signal comes, the ramp circuit and the digital delay circuit are immediately started, the digital delay is counted to an appropriate value (such as 20 ns), the ramp circuit is closed until the digital delay is finished, the ramp circuit is opened again, and the rest of delay is continuously finished. The final output is ensured not to be affected by the time jitter of the trigger input.
The output driving module 6 provides driving capability and polarity selection function of the output signal, based on fig. 6. The module completes the selection of the output port (A, B, C or D) and the selection of the trigger polarity. The device may be triggered by a rising or falling edge of an external signal.
Fig. 7 is a diagram of a capacitive discharge compensation module, including a capacitive compensation circuit with four channels (A, B, C, D), and fig. 8 is a diagram of a capacitive voltage change in the ramp circuit module 5. The module is used for measuring the discharge coefficient of the charging capacitor 31 and measuring the time between an external trigger signal and the rising edge of the temperature compensation crystal oscillator clock. The charge and discharge switch 30 is turned off, but the capacitor voltage drops exponentially due to the switch leakage current and PCB impedance (see fig. 8, section CD). The self-discharge coefficient of the capacitor can be obtained by measuring the voltage of the charge capacitor 31 at two times of digital delay. The formula is as follows:
Wherein τ is the self-discharge coefficient of the charging capacitor, T is the time interval between two sampling of A/D38, y 1 is the first sampling voltage of A/D38, and y 2 is the second sampling voltage of A/D38. According to the magnitude of tau value, niosII soft core 22 automatically judges whether the current delay range needs compensation, if so, the voltage of capacitor reduced in digital delay stage is folded to analog delay slope circuit D/A32, and the error caused by capacitor self-discharge is eliminated.
FIG. 9 is a schematic diagram of an automatic calibration function in a self-triggering mode, wherein a clock generated by a temperature compensation crystal oscillator is used as a time reference, and the delay of T0 is an integer multiple of a clock period. Taking the a channel as an example, the T0 channel emits pulses at fixed time intervals (assuming 100 ns), while setting the a channel delay to be also 100ns, and the a channel delay consists of a digital delay X (assuming 90 ns) and an analog delay Y (assuming 10 ns). The level of the A channel is detected at the rising edge of T0, and depending on the level state, the nios II soft core 22 adjusts the D/A32 of the ramp circuit so that the rising edges of T0 and A channels are approximated indefinitely. The charging coefficient k= DeltaV/DeltaT (DeltaV is the voltage difference, deltaT=10ns) of the analog delay part can be accurately obtained, the influence of different component parameters on the charging coefficient is eliminated, and the nios II soft core 22 automatically adjusts the parameters of the A channel to be optimal. B. The C, D channel is the same as the a channel principle. The function skillfully utilizes the time sequence detection of the FPGA and the logic control function of the niosII soft core 22, and can realize accurate and automatic calibration of parameter configuration without other devices.
Due to the differences in analog devices, the linearity of the charging voltage of the capacitor 31 of the ramp circuit, and the transient process of starting and shutting off the charging of the capacitor, can deviate the delay time from a linear relationship with the D/a set point. The digital delay pulse generating device is calibrated: the correction value with the delay time of 0-50ns and the stepping of 0.5ns is measured and stored in the FLASH of the FPGA module as a correction data table, and when in actual work, the correction value is read out to correct the deviation, so that the function of one-key calibration is not required to be started every time the device is started, and one machine is one parameter.
The functions of the communication module 8, the touch screen 7 and the like are finished by niosII soft cores 22 in the FPGA chip, wherein the communication mode of the communication module is divided into two types of Ethernet (LAN) and serial ports (RS 232), and the touch screen is connected with niosII soft cores through the serial ports (RS 232). Meanwhile, the singlechip is also responsible for realizing the overall logic control of the synchronous machine device.
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| CN111277248B (en) * | 2020-04-03 | 2023-09-19 | 中国科学院近代物理研究所 | A multi-working mode synchronization pulse generating device and its working method |
| CN111564098A (en) * | 2020-05-22 | 2020-08-21 | 上海瓯龙模型标识有限公司 | Photoelectric building model sand table exhibition method and system thereof |
| CN112436824B (en) * | 2020-11-12 | 2021-08-10 | 华中科技大学 | High-stability time sequence signal generation method and device |
| CN113009455B (en) * | 2021-04-14 | 2022-06-03 | 吉林大学 | A method and system for improving the accuracy of pulsed laser ranging |
| CN114256052A (en) * | 2022-02-22 | 2022-03-29 | 浙江迪谱诊断技术有限公司 | Pulse delay device, method and time-of-flight mass spectrometer comprising pulse delay device |
| CN115037286B (en) * | 2022-06-22 | 2026-02-03 | 国仪量子技术(合肥)股份有限公司 | Delay pulse generation device and method based on FPGA chip and electronic equipment |
| CN120017020A (en) * | 2025-02-06 | 2025-05-16 | 北京中航通用科技有限公司 | Hardware Design of a New Picosecond Digital Delay Pulse Generator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103308492A (en) * | 2013-06-13 | 2013-09-18 | 吉林大学 | Synchronous machine applied to laser-induced breakdown spectroscopy |
| CN105827222A (en) * | 2016-05-18 | 2016-08-03 | 中国工程物理研究院应用电子学研究所 | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4841497A (en) * | 1987-12-07 | 1989-06-20 | Tektronix, Inc. | Digital time base with corrected analog interpolation |
| EP1632825B1 (en) * | 2004-09-03 | 2008-10-29 | Derek Ward | Improvements in or relating to programmable logic controller and related electronic devices |
| CN102035512B (en) * | 2010-11-19 | 2014-06-25 | 中国工程物理研究院流体物理研究所 | Clock phase-splitting technology-based precise digital time delay synchronous machine and time delay method |
| US9312844B2 (en) * | 2012-11-15 | 2016-04-12 | Microchip Technology Incorporated | Slope compensation module |
| CN103117732B (en) * | 2013-02-22 | 2015-12-09 | 哈尔滨工程大学 | Multi-channel video pulse signal generation device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103308492A (en) * | 2013-06-13 | 2013-09-18 | 吉林大学 | Synchronous machine applied to laser-induced breakdown spectroscopy |
| CN105827222A (en) * | 2016-05-18 | 2016-08-03 | 中国工程物理研究院应用电子学研究所 | Nanosecond grade digital synchronizer based on FPGA high-speed serial bus |
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