CN106653609B - A kind of novel fin formula field effect transistor and preparation method thereof - Google Patents
A kind of novel fin formula field effect transistor and preparation method thereof Download PDFInfo
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Abstract
本发明公开了一种新型鳍式场效应晶体管及其制作方法,本发明的新型鳍式场效应晶体管,包括:基底;位于所述基底上的鳍部,所述鳍部两端形成源区和漏区;横跨所述源区和漏区中间的鳍部上表面以及两侧的栅极结构,所述鳍部上表面呈凸齿结构,所述凸齿结构凸起部分为齿部,所述鳍部上表面两齿部之间存在迁移率增强区,所述源区以及漏区在齿部顶端无掺杂,所述栅极结构嵌入所述鳍部的凸齿结构内,本发明可提高晶体管驱动电流,改善晶体管性能。
The invention discloses a novel fin field effect transistor and a manufacturing method thereof. The novel fin field effect transistor of the present invention comprises: a base; a fin located on the base, a source region and a The drain region; across the upper surface of the fin in the middle of the source region and the drain region and the gate structure on both sides, the upper surface of the fin has a convex tooth structure, and the convex part of the convex tooth structure is a tooth, so There is a mobility enhanced region between the two teeth on the upper surface of the fin, the source region and the drain region are not doped at the top of the teeth, and the gate structure is embedded in the protruding tooth structure of the fin. The present invention can Increase transistor drive current and improve transistor performance.
Description
技术领域technical field
本发明涉及半导体技术领域,特别涉及一种鳍式场效应晶体管及其制作方法。The invention relates to the technical field of semiconductors, in particular to a fin field effect transistor and a manufacturing method thereof.
技术背景technical background
晶体管是集成电路中关键的元件。为了满足晶体管更快速的需求,需要较高的驱动电流。另外,由于晶体管的驱动电流正比于晶体管的栅极宽度,为了提高驱动电流,需要较大的栅极宽度。Transistors are critical components in integrated circuits. To meet the demands of faster transistors, higher drive currents are required. In addition, since the driving current of the transistor is proportional to the gate width of the transistor, in order to increase the driving current, a larger gate width is required.
鳍式场效应晶体管具有一从基底突出的狭窄半导体材料有源区域作为鳍部,此鳍部包括两端的源区与漏区,栅极结构包括栅介质层以及位于栅介质层上的栅电极,栅极结构横跨源区与漏区之间的鳍部,与其上表面以及两侧接触形成导电沟道,相当于增加了栅极宽度,有效增加了驱动电流,改善了器件性能。随着现有相关技术的进步,器件的特征尺寸进一步下降,需进一步改善工艺,进一步增加驱动电流。The fin field effect transistor has a narrow semiconductor material active region protruding from the base as a fin, the fin includes a source region and a drain region at both ends, the gate structure includes a gate dielectric layer and a gate electrode on the gate dielectric layer, The gate structure spans the fin between the source region and the drain region, and forms a conductive channel in contact with its upper surface and both sides, which is equivalent to increasing the gate width, effectively increasing the driving current, and improving device performance. With the advancement of existing related technologies, the feature size of the device is further reduced, and the process needs to be further improved to further increase the driving current.
发明内容Contents of the invention
本发明的目的是提供一种新型鳍式场效应晶体管的制作方法,提高晶体管驱动电流,改善晶体管性能。The object of the present invention is to provide a novel manufacturing method of a fin field effect transistor, increase the driving current of the transistor, and improve the performance of the transistor.
本发明的另一目的是提供上述方法制作的鳍式场效应晶体管。Another object of the present invention is to provide a fin field effect transistor fabricated by the above method.
为实现上述目的,本发明采用如下技术方案:To achieve the above object, the present invention adopts the following technical solutions:
一种新型鳍式场效应晶体管的制作方法,包括以下步骤:A method for manufacturing a novel fin field effect transistor, comprising the following steps:
(1)提供基底,并在所述基底上形成一半导体凸出结构;(1) providing a base, and forming a semiconductor protrusion structure on the base;
(2)制作并通过第一掩膜版刻蚀所述半导体凸出结构,形成上表面呈凸齿结构的鳍部,所述凸齿结构凸起部分为齿部;(2) making and etching the semiconductor protruding structure through the first mask to form a fin with a convex tooth structure on the upper surface, and the convex part of the convex tooth structure is a tooth;
(3)在未被第一掩膜版覆盖的鳍部表面沉积与鳍部晶格常数不同迁移率增强区;(3) Depositing a mobility enhancement region different from the lattice constant of the fin on the surface of the fin not covered by the first mask;
(4)制作第二掩膜版,第二掩膜版覆盖鳍部中间,同时以第一掩膜版以及第二掩膜版为掩膜,向所述鳍部两端掺杂杂质,形成源区以及漏区,并去除第二掩膜版以及第一掩膜版;(4) Make a second mask, the second mask covers the middle of the fin, and at the same time use the first mask and the second mask as masks to dope impurities to both ends of the fin to form a source region and drain region, and removing the second mask and the first mask;
(5)制作覆盖源区以及漏区的第三掩膜版,所述第三掩膜版两端开口边缘投影在未被掺杂的中间的鳍部上,通过第三掩膜版形成嵌入所述鳍部的凸齿结构内的栅极结构,并去除第三掩膜版。(5) Make a third mask covering the source region and the drain region. The opening edges at both ends of the third mask are projected on the undoped middle fin, and the third mask is used to form the embedded The gate structure in the protruding tooth structure of the fin portion is removed, and the third mask plate is removed.
优选地,所述基底为硅(Si)或者绝缘体上硅(SOI)。Preferably, the substrate is silicon (Si) or silicon-on-insulator (SOI).
优选地,所述迁移率增强区为硅锗(GeSi)或碳化硅(SiC)。Preferably, the mobility enhanced region is silicon germanium (GeSi) or silicon carbide (SiC).
优选地,第(3)步采用外延生长法沉积迁移率增强区。Preferably, the step (3) adopts the epitaxial growth method to deposit the mobility enhanced region.
优选地,第(4)步掺杂杂质采用离子注入掺杂。Preferably, the doping of impurities in step (4) is done by ion implantation.
优选地,第(4)步离子注入掺杂时,注入方向不与第一掩膜版垂直。Preferably, during step (4) ion implantation and doping, the implantation direction is not perpendicular to the first mask.
优选地,第(4)步离子注入掺杂时,先偏向源区或漏区方向成一定角度注入,再偏向相反的方向成一定角度注入。Preferably, during step (4) ion implantation doping, the implantation is performed at a certain angle towards the direction of the source region or the drain region, and then implanted at a certain angle towards the opposite direction.
优选地,第(5)步所述第三掩膜版两端开口边缘在未被掺杂的中间的鳍部上的齿部上。Preferably, in step (5), the edges of the openings at both ends of the third mask plate are on the teeth of the undoped middle fin.
优选地,第(5)步所述第三掩膜版两端开口边缘在未被掺杂的中间的鳍部上的齿部中央上。Preferably, in step (5), the edges of the openings at both ends of the third mask plate are on the center of the teeth on the undoped middle fin.
一种新型鳍式场效应晶体管,包括:基底;位于所述基底上的鳍部,所述鳍部两端形成源区和漏区;横跨所述源区和漏区中间的鳍部上表面以及两侧的栅极结构,所述鳍部上表面呈凸齿结构,所述凸齿结构凸起部分为齿部,所述鳍部上表面两齿部之间存在迁移率增强区,所述源区以及漏区在齿部顶端无掺杂,所述栅极结构嵌入所述鳍部的凸齿结构内。A novel Fin Field Effect Transistor, comprising: a base; a fin located on the base, a source region and a drain region are formed at both ends of the fin; an upper surface of the fin spanning the middle of the source region and the drain region As well as the gate structures on both sides, the upper surface of the fin has a convex tooth structure, the convex part of the convex tooth structure is a tooth, and there is a mobility enhanced region between the two teeth on the upper surface of the fin, the The source region and the drain region are not doped at the top of the tooth portion, and the gate structure is embedded in the protruding tooth structure of the fin portion.
相对于现有技术,本发明具有以下有益效果:Compared with the prior art, the present invention has the following beneficial effects:
本发明鳍式场效应晶体管制作方法第一掩膜版首先做掩膜形成上表面呈凸齿结构的鳍部,其次作为迁移率增强区形成过程的掩膜,再次作为杂质掺杂的部分掩膜,实现了第一掩膜版的多次有效利用,使得工艺流程简单易实现,节约工艺成本。The first mask plate of the fin field effect transistor manufacturing method of the present invention is firstly used as a mask to form a fin with a convex tooth structure on the upper surface, secondly used as a mask for the formation process of the mobility enhancement region, and then used as a partial mask for impurity doping , realize multiple effective utilization of the first mask plate, make the process flow simple and easy to realize, and save the process cost.
本发明制作的晶体管,所述鳍部上表面呈凸齿结构,所述鳍部上表面两齿部之间形成晶格常数不同于鳍部的迁移率增强区,引入压应力或拉应力,增加对鳍部载流子的迁移率,提高晶体管导通时的导通电流;所述栅极结构嵌入所述鳍部的凸齿结构内,增加了栅极宽度,进一步提高晶体管的驱动电流;此外,源区以及漏区在齿部顶端无掺杂,增加源区以及漏区表面电阻,减小栅极与源区以及漏区的漏电流,进一步优化晶体管性能。In the transistor produced by the present invention, the upper surface of the fin has a convex tooth structure, and a mobility enhancement region with a lattice constant different from that of the fin is formed between the two teeth on the upper surface of the fin, and compressive stress or tensile stress is introduced to increase For the mobility of fin carriers, the conduction current when the transistor is turned on is improved; the gate structure is embedded in the protruding tooth structure of the fin, which increases the gate width and further improves the drive current of the transistor; in addition , the source region and the drain region are not doped at the top of the teeth, which increases the surface resistance of the source region and the drain region, reduces the leakage current between the gate and the source region and the drain region, and further optimizes the performance of the transistor.
附图说明Description of drawings
图1-图5为本发明实施例制作过程结构示意图;Fig. 1-Fig. 5 is the structural schematic diagram of the manufacturing process of the embodiment of the present invention;
图6为本发明实施例整体结构示意图;6 is a schematic diagram of the overall structure of an embodiment of the present invention;
图7为本发明实施例栅极结构局部示意图。FIG. 7 is a partial schematic diagram of a gate structure according to an embodiment of the present invention.
具体实施方式Detailed ways
下面结合附图以及实施例对本发明进行介绍,实施例仅用于对本发明进行解释,并不对本发明有任何限定作用。The present invention will be introduced below in conjunction with the accompanying drawings and embodiments, and the embodiments are only used to explain the present invention and do not limit the present invention in any way.
图1-图5为本发明实施例制作过程各步骤结构示意图,如图所示,新型鳍式场效应晶体管的制作方法,包括以下步骤:Figures 1-5 are schematic structural diagrams of each step in the manufacturing process of the embodiment of the present invention. As shown in the figure, the manufacturing method of the novel fin field effect transistor includes the following steps:
(1)如图1,提供基底100,并在所述基底上形成一半导体凸出结构201;(1) As shown in FIG. 1 , a substrate 100 is provided, and a semiconductor protrusion structure 201 is formed on the substrate;
基底100材料可为绝缘体上硅(SOI),此时所述SOI的顶层硅层用于形成所述凸出结构201;基底100材料也可为硅(Si)、锗(Ge)、硅锗(GeSi)或者碳化硅(SiC)等半导体衬底,此时所述凸出结构201通过对上述半导体衬底刻蚀后形成,在凸出结构201两侧的半导体衬底上形成表面低于凸出结构201的绝缘介质层;基底100材料也可为氧化硅等绝缘衬底,此时所述凸出结构201通过外延工艺形成,鳍部200材料可为硅(Si)、锗(Ge)、硅锗(GeSi)或者碳化硅(SiC),本发明实施例优选基底为硅(Si)或者绝缘体上硅(SOI),附图以绝缘体上硅(SOI)为例。The material of the base 100 can be silicon-on-insulator (SOI), at this time the top silicon layer of the SOI is used to form the protruding structure 201; the material of the base 100 can also be silicon (Si), germanium (Ge), silicon germanium ( GeSi) or silicon carbide (SiC) and other semiconductor substrates. At this time, the protruding structure 201 is formed by etching the above-mentioned semiconductor substrate. The insulating dielectric layer of the structure 201; the material of the base 100 can also be an insulating substrate such as silicon oxide, at this time, the protruding structure 201 is formed by an epitaxial process, and the material of the fin 200 can be silicon (Si), germanium (Ge), silicon Germanium (GeSi) or silicon carbide (SiC), the preferred substrate of the embodiment of the present invention is silicon (Si) or silicon-on-insulator (SOI). The accompanying drawings use silicon-on-insulator (SOI) as an example.
(2)如图2,制作并通过第一掩膜版10刻蚀所述半导体凸出结构201,形成上表面呈凸齿结构的鳍部200,所述凸齿结构凸起部分为齿部210;(2) As shown in FIG. 2 , fabricate and etch the semiconductor protruding structure 201 through the first mask plate 10 to form a fin 200 with a convex tooth structure on the upper surface, and the convex part of the convex tooth structure is a tooth portion 210 ;
第一掩膜版10首先做掩膜形成上表面呈凸齿结构的鳍部200。The first mask plate 10 is first used as a mask to form the fin portion 200 with a convex tooth structure on the upper surface.
(3)如图3,在未被第一掩膜版10覆盖的鳍部200表面沉积与鳍部200晶格常数不同的迁移率增强区300;(3) As shown in FIG. 3 , deposit a mobility enhancement region 300 having a lattice constant different from that of the fin 200 on the surface of the fin 200 not covered by the first mask 10 ;
本发明实施例未被第一掩膜版10覆盖部分,刻蚀形成的两个齿部210之间的凹槽的槽壁以及槽底漏出鳍部200半导体材料,可采用外延生长沉积迁移率增强区300,实施例基底为硅(Si)或者绝缘体上硅(SOI)时,鳍部200材料为硅,锗或者碳与硅晶格常数不同,且锗或者碳的硅化物易外延生长在硅表面,所以迁移率增强区300优选为硅锗(GeSi)或碳化硅(SiC)。The portion not covered by the first mask plate 10 in the embodiment of the present invention, the groove wall and groove bottom of the groove between the two tooth portions 210 formed by etching leak out the semiconductor material of the fin portion 200, and the mobility enhancement can be deposited by epitaxial growth. In region 300, when the embodiment substrate is silicon (Si) or silicon-on-insulator (SOI), the material of fin 200 is silicon, germanium or carbon has a different lattice constant from silicon, and the silicide of germanium or carbon is easy to epitaxially grow on the silicon surface , so the mobility enhanced region 300 is preferably silicon germanium (GeSi) or silicon carbide (SiC).
(4)如图4,制作第二掩膜版20,第二掩膜版20覆盖鳍部中间,同时以第一掩膜版10以及第二掩膜版20为掩膜,向所述鳍部200两端掺杂杂质,形成源区400以及漏区500,之后去除第二掩膜版20以及第一掩膜版10;(4) As shown in Figure 4, make a second mask 20, the second mask 20 covers the middle of the fin, and at the same time use the first mask 10 and the second mask 20 as masks to cover the fins. Doping impurities at both ends of 200 to form a source region 400 and a drain region 500, and then removing the second mask 20 and the first mask 10;
本发明实施例以第一掩膜版10以及第二掩膜版20为掩膜进行掺杂,第二掩膜版20覆盖鳍部中间,所以在鳍部200中间形成不掺杂的区域,以便在达到阈值电压之前,使晶体管关断;由于第一掩膜板10的覆盖,所以向所述鳍部200两端掺杂杂质形成源区400以及漏区500时,源区400以及漏区500在齿部210顶端无掺杂,本发明实施例掺杂杂质为磷或砷等n型杂质或者磷等p型杂质,掺杂方式优选离子注入掺杂,离子注入掺杂时,注入方向不与第一掩膜版10垂直,先偏向源区或漏区方向成一定角度注入,再偏向相反的方向成一定角度注入,以便在整个源区400以及漏区500内形成连续地掺杂区,齿部210顶端无掺杂区域的大小可由齿部的高度以及离子注入时的注入角度调节。In the embodiment of the present invention, the first mask 10 and the second mask 20 are used as masks for doping, and the second mask 20 covers the middle of the fin, so an undoped region is formed in the middle of the fin 200, so that Before reaching the threshold voltage, the transistor is turned off; due to the coverage of the first mask 10, when doping impurities to both ends of the fin portion 200 to form the source region 400 and the drain region 500, the source region 400 and the drain region 500 There is no doping at the top of the tooth portion 210. The doping impurities in the embodiment of the present invention are n-type impurities such as phosphorus or arsenic or p-type impurities such as phosphorus. The doping method is preferably ion implantation doping. The first mask plate 10 is vertical, implanted at a certain angle to the direction of the source region or the drain region, and then implanted at a certain angle to the opposite direction, so as to form a continuous doped region in the entire source region 400 and drain region 500. The size of the undoped region at the top of the portion 210 can be adjusted by the height of the teeth and the implantation angle during ion implantation.
(5)如图5,制作覆盖源区400以及漏区500的第三掩膜版30,所述第三掩膜版30两端开口边缘投影在未被掺杂的中间的鳍部200上,通过第三掩膜版30形成嵌入所述鳍部200的凸齿结构内的栅极结构600,之后去除第三掩膜版30。(5) As shown in FIG. 5 , make a third mask 30 covering the source region 400 and the drain region 500 , and the opening edges at both ends of the third mask 30 are projected on the undoped middle fin 200 , The gate structure 600 embedded in the protruding tooth structure of the fin portion 200 is formed through the third mask 30 , and then the third mask 30 is removed.
优选地所述,第三掩膜版30两端开口边缘在未被掺杂的中间的鳍部200上的齿部210上,由于齿部210上无迁移率增强区300,载流子迁移率弱,减小栅极漏电流,优选地,所述第三掩膜版30两端开口边缘在未被掺杂的中间的鳍部200上的齿部210中央上,齿部210中央载流子迁移率最弱,所以更好地减小栅极漏电流。Preferably, the opening edges at both ends of the third mask 30 are on the tooth portion 210 on the undoped middle fin portion 200, since there is no mobility enhancement region 300 on the tooth portion 210, the carrier mobility Weak, to reduce the gate leakage current, preferably, the opening edges at both ends of the third mask 30 are on the center of the teeth 210 on the undoped middle fin 200, and the center of the teeth 210 carriers The mobility is the weakest, so it is better to reduce the gate leakage current.
上述方法制作的本发明实施例鳍式场效应晶体管,包括:基底100;位于所述基底100上的鳍部200,所述鳍部200两端形成源区400和漏区500;横跨所述源区400和漏区500中间的鳍部200上表面以及两侧的栅极结构600,所述鳍部200上表面呈凸齿结构,所述凸齿结构凸起部分为齿部210,所述鳍部200上表面两齿部210之间存在迁移率增强区300,所述源区400以及漏区500在齿部210顶端无掺杂,所述栅极结构600嵌入所述鳍部200的凸齿结构内。The fin field effect transistor of the embodiment of the present invention manufactured by the above method includes: a substrate 100; a fin 200 located on the substrate 100, and a source region 400 and a drain region 500 are formed at both ends of the fin 200; The upper surface of the fin 200 in the middle of the source region 400 and the drain region 500 and the gate structures 600 on both sides, the upper surface of the fin 200 has a convex tooth structure, and the convex part of the convex tooth structure is a tooth portion 210. There is a mobility enhancement region 300 between the two tooth portions 210 on the upper surface of the fin portion 200, the source region 400 and the drain region 500 are not doped at the top of the tooth portion 210, and the gate structure 600 is embedded in the convex portion of the fin portion 200. within the tooth structure.
如图6以及图7,本发明实施例鳍式场效应晶体管,所述鳍部200上表面呈凸齿结构,所述鳍部200上表面两齿部210之间形成晶格常数不同于鳍部200的迁移率增强区300,引入压应力或拉应力,增加对鳍部200载流子的迁移率,提高晶体管导通时的导通电流;所述栅极结构600嵌入所述鳍部的凸齿结构内,增加了栅极宽度,进一步提高晶体管的驱动电流;此外,源区400以及漏区500在齿部210顶端无掺杂,增加源区400以及漏区500表面电阻,本领域常识,晶体管源区400与源电极电性连接,漏区500与漏电极电性连接,所以可以减小栅极与源电极以及漏电极间的漏电流,进一步优化晶体管性能。As shown in Fig. 6 and Fig. 7, the fin field effect transistor of the embodiment of the present invention, the upper surface of the fin 200 has a convex tooth structure, and the lattice constant formed between the two teeth 210 on the upper surface of the fin 200 is different from that of the fin. The mobility enhancement region 300 of 200 introduces compressive stress or tensile stress, increases the mobility of carriers to the fin 200, and improves the conduction current when the transistor is turned on; the gate structure 600 is embedded in the raised portion of the fin. In the tooth structure, the gate width is increased to further increase the driving current of the transistor; in addition, the source region 400 and the drain region 500 are not doped at the top of the tooth portion 210, which increases the surface resistance of the source region 400 and the drain region 500, which is common knowledge in the field. The source region 400 of the transistor is electrically connected to the source electrode, and the drain region 500 is electrically connected to the drain electrode, so the leakage current between the gate, the source electrode and the drain electrode can be reduced, and the performance of the transistor can be further optimized.
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