CN106650138B - A kind of method of automatic realization static state and dynamic timing analysis comparison - Google Patents
A kind of method of automatic realization static state and dynamic timing analysis comparison Download PDFInfo
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- 238000013461 design Methods 0.000 claims abstract description 18
- 238000005259 measurement Methods 0.000 claims abstract description 10
- 238000004088 simulation Methods 0.000 claims abstract description 10
- 238000012731 temporal analysis Methods 0.000 claims abstract description 8
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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Abstract
A kind of method of automatic realization static state and dynamic timing analysis comparison, comprising the following steps: load Spice Deck file packet obtains the STA Time-Series analysis report file in each path and the circuit meshwork list file for emulation；Setting is scanned to voltage, temperature and Monte Carlo analysis respectively；It calls emulator to be emulated, generates corresponding dynamic time sequence measurement result file；STA result and simulation result are compared, the correctness of design is verified.Method of the invention, the comparison of result is completed using the tool of automation, and shows the analysis report of comparison, provides information required for designer, is saved the time for designer, is shortened the design cycle, improve the efficiency of design.
Description
Technical field
The present invention relates to Design of Digital Circuit analysis tool technical fields, more particularly to the method for Time-Series analysis comparison.
Background technique
In the prior art, STA(Static Timing Analysis) technology is a kind of exhaustive analysis method, to measure
Circuit performance, it extracts the timing path of entire circuit, is propagated by calculating delay of the signal on path, finds out and violate timing
The mistake of constraint, it is main to check whether settling time and retention time meet the requirements, and they are respectively by maximum path
The analysis of delay and minimal path delay obtains.
But STA might have 20% even greater analytical error.First source of error is Delay computing, STA work
Tool masks actual circuit behavior using simplified delay model, such as switches multiple input switches and active reception simultaneously
Device, these influences may be ignored or are roughly calculated, these basic delay errors can be up to 5% or more.Second
Influence is the influence of technique variance (Process Variance), and technique variance can cause delay displacement more on individual unit
Up to 50%, this will increase another 5% to 10% clock delay errors again.Third, in subnormal voltage operation and local voltage change
When, it is contemplated that overall error can rise to up to 20% or more.For static timing analysis, designer usually compares concern electricity
The Slack parameter index on road, Slack are used to show the case where whether violating setup time constraint on the timing path.Work as Slack
To indicate to meet setup time constraint when positive value, setup time constraint is then unsatisfactory for when Slack is negative.On the one hand, when static
Result is excessively pessimistic sometimes for sequence analysis tool, that is, the Slack value analyzed is smaller than true value, so that designer needs to be added
Excessive delay unit can be only achieved design requirement, this will lead to, and final chip area is bigger than normal, and power consumption is bigger than normal；On the other hand, because
It is simplified or ignore the influence of many Key Circuits for STA, it there may come a time when that the calculated result that will appear mistake, i.e. Slack value are positive
And true value the case where being negative, then it will lead to flow failure.Therefore need to carry out by emulation tool dynamic Time-Series analysis come
It is more accurately and reliably verified, and by the comparison of two kinds of analysis results it can be found that the error and mistake of STA.At present
For the process of this contrast verification still completely in such a way that manpower is compared, this process can spend engineer's many times
And energy, it is very long to lead to the design cycle, therefore the comparison of result is completed there is an urgent need to a rapid automatized tool, and
The analysis report for showing comparison provides information required for designer, saves the time for designer, shortens design week
Phase.
Summary of the invention
In order to solve the shortcomings of the prior art, the purpose of the present invention is to provide a kind of automatic realization static state and dynamics
The method of Time-Series analysis comparison, carries out dynamic Time-Series analysis by emulation tool, and STA result and simulation result are carried out pair
Than finding the error and mistake of STA.
To achieve the above object, the method for automatic realization static state provided by the invention and dynamic timing analysis comparison, including
Following steps:
1) Spice Deck file packet is loaded, obtains the STA Time-Series analysis report file in each path and for emulation
Circuit meshwork list file；
2) setting is scanned to voltage, temperature and Monte Carlo analysis respectively；
3) it calls emulator to be emulated, generates corresponding dynamic time sequence measurement result file；
4) STA result and simulation result are compared, verify the correctness of design.
Further, the step 1) further includes steps of required voltage drive value in specified design, temperature
Degree, and the library file needed.
Further, calling emulator described in step 3) is emulated, and is to carry out transient state point to the netlist in each path
Analysis, generates corresponding dynamic time sequence measurement result file.
Further, the step 4) is the static analysis report file for reading STA tool and the dynamic of emulator generation
Measurement report file compares, and verifies the correctness of design.
Further, the step 4) further includes steps of
Show the specific data information in selected path in a manner of table and waveform；
The analysis statistical information of voltage scanning, temperature scanning and Monte Carlo scanning is shown with chart mode；
Simulation result is filtered and is sorted.
The automatic method for realizing the comparison of static and dynamic timing analysis of the invention, when carrying out dynamic by emulation tool
Sequence analyze more accurately and reliably to be verified, and by two kinds analysis results comparison it can be found that STA error and
Mistake.The time and efforts of engineer is saved, so that the design cycle shortens.Result is completed by rapid automatized tool
Comparison, and show the analysis report of comparison, information required for designer be provided, save the time for designer, contract
The short design cycle.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, and with it is of the invention
Embodiment together, is used to explain the present invention, and is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is automatic realization static state according to the present invention and the method work flow diagram that dynamic timing analysis compares；
Fig. 2 is instrument start-up display interface schematic diagram according to the present invention；
Fig. 3 is Create Workspace interface schematic diagram according to the present invention；
Fig. 4 is Create Session interface schematic diagram according to the present invention；
Fig. 5 is Config Session interface schematic diagram according to the present invention；
Fig. 6 is that data according to the present invention show main interface schematic diagram；
Fig. 7 is the specifying information figure of single Path according to the present invention；
Fig. 8 is the statistical information figure of all Path according to the present invention；
Fig. 9 is scanning analysis statistical results chart according to the present invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 1 is the method work flow diagram of automatic realization static state according to the present invention and dynamic timing analysis comparison, below
Fig. 1 will be referred to, the automatic method for realizing the comparison of static and dynamic timing analysis of the invention will be described in detail.
It include multiple paths in packet firstly, loading the Spice Deck packet of coming in required for specifying in step 101
(path), each Path is as a unit, comprising the STA Time-Series analysis report file generated and for emulating in each Path
Circuit meshwork list file.It can specify required voltage drive value in design, temperature simultaneously, and need library (library)
File.
Fig. 2 is instrument start-up display interface schematic diagram according to the present invention, as shown in Fig. 2, including menu bar, work in interface
Have column, circuit simulation list column and result Show board.There is opening file in menu bar, configure, emulation generates the options such as report behaviour
Make.All Workspace and Path for being included in engineering are listed on the left list column, and show the status information of Path.Fig. 3 is
Create Workspace interface schematic diagram according to the present invention, as shown in figure 3, menu item is opened in selection recalls Create
The interface Workspace inputs the workspace name that will be generated, and the working directory of specified workspace.According to Fig. 4
Create Session interface schematic diagram of the invention, as shown in figure 4, the Spice Deck packet that load is come in required for specified.
In step 102, it is scanned setting.In this step, respectively to voltage scanning, temperature scanning and Monte Carlo point
Analysis is configured.Fig. 5 is Config Session interface schematic diagram according to the present invention, as shown in figure 5, select tools column
Configure Session supports voltage scanning, temperature scanning and Monte Carlo point to the setting being scanned respectively
Analysis.
In step 103, emulator emulation is called, transient state point is carried out to the netlist in every Path in Spice Deck packet
Analysis, and generate corresponding dynamic time sequence measurement result file.In this step, Run figure in Run or toolbar is clicked in menu bar
Mark is emulated.This invocation of procedure emulator carries out transient analysis to the netlist in every Path, and when generating corresponding dynamic
Sequence measurement result file.
In step 104, reads simulation result and be shown, list STA result and simulation result.
The interface Inspect menu formation Timing Inspection is clicked after emulation.Fig. 6 is according to the present invention
Data show main interface schematic diagram, as shown in fig. 6, this interface includes three modules, it is path filtering (Filter) module respectively,
Data show that table module and data analyze (Analysis) button module.What data display table module was listed first is all
The information of Path, one shares 10 column, respectively Path Name, Start Point, End Point, Slack (STA), Slack
(SIM),Slack(Delta),Freq(STA),Freq(SIM),Delay Type,Path Group.Wherein Path Name generation
The name of this Path of table, Start Point and End Point respectively correspond Path starting and end point, Slack (STA) and
Slack (SIM) is respectively the Slack value that STA and emulator analyze this Path obtained, Slack (Delta) the i.e. difference of the two
Value, Freq(STA) and Freq(SIM) it is respectively STA and the operating frequency value of this Path that emulator analysis obtains.In this way may be used
The difference analyzed with the very clear and intuitive STA for showing all Path and emulator.Secondly it is provided in filtering module several
The mode of kind of filtering, can be according to Delay Type, and the size of Slack value, Path Group type etc. is filtered, in addition exists
The Title that each column in table is clicked in data form can carry out column sequence, and ascending order either descending arrangement is operated by these
The information of special attention can be positioned as soon as possible and is presented in data form by user, further go to analyze and determine that circuit is
It is no to meet index request.In addition analysis module lists three buttons, is Timing Stat, Incr Stat, Sweep respectively
Stat is supplied to user and does different data statistic analysis.
In step 105, the specific data information in Path is checked.Data form display module selects certain in Fig. 6
Row is double-clicked where Path, that is, may bring up the specific data information in this Path, and the mode of table and waveform shows.Figure
7 be the specifying information figure of single Path according to the present invention, as shown in fig. 7, specific data letter in a manner of table and waveform into
Row shows.
In step 106, result is filtered, is sorted.In this step, can according to Delay Type, Slack value it is big
Small, Path Group type etc. is filtered, and carries out column sequence, ascending order either descending arrangement to result.
In step 107, scanning result is checked.
In step 108, the correctness being related to is verified, the problem of Position Design.The analysis module in Fig. 6
Timing Stat button is clicked, then carries out Timing statistics, lists number and variance of the Slack value less than 0 in all Path
The statistical informations such as mean value.Fig. 8 is the statistical information figure of all Path according to the present invention, as shown in figure 8, the form of waveform is drawn
The Slack value of all Path out, it is more intuitive by way of waveform to compare.Fig. 9 is scanning point according to the present invention
Statistical results chart is analysed, as shown in figure 9, then showing the statistics of scanning analysis result, user can see the tool in each scanning element
Body Slack value, and provide the statistical information of scanning analysis.It is analyzed by these, which designer can quickly position
Path can obtain best index in the case of violating setup time constraint rule and which scanning element.
The automatic method for realizing the comparison of static and dynamic timing analysis of the invention, completes timing by operational instrument interface
The importing of circuit static analysis report, the dynamic simulation analysis of sequence circuit, the automatic reading of analysis report and pair of result
Than showing；The input that circuit meshwork list information, model information and excitation information can be completed by this method passes through calling
Emulator can carry out transient circuit analysis, voltage scanning analysis, temperature scanning analysis and Monte Carlo analysis, emulation knot
Shu Zidong read STA generate analysis report file and emulator generate time-ordered measurement destination file, by the two result into
Row comparison is shown；Analysis data be graphically, show in circuit design the Slack of each critical path and
The comparison of Frequency information, while user can be filtered at interface, sort and quickly to position some keys for needing to pay close attention to
Path, and can check specific routing information and scan the result information of simulation analysis.
Those of ordinary skill in the art will appreciate that: the foregoing is only a preferred embodiment of the present invention, and does not have to
In the limitation present invention, although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art
For, still can to foregoing embodiments record technical solution modify, or to part of technical characteristic into
Row equivalent replacement.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all include
Within protection scope of the present invention.
Claims (4)
1. a kind of automatic method for realizing the comparison of static and dynamic timing analysis, which comprises the following steps:
1) Spice Deck file packet is loaded, the STA Time-Series analysis report file in each path and the circuit for emulation are obtained
Net meter file；
2) setting is scanned to voltage, temperature and Monte Carlo analysis respectively；
3) it calls emulator to be emulated, generates corresponding dynamic time sequence measurement result file；
4) STA result and simulation result are compared, verify the correctness of design；
The step 4) further includes steps of
The data information in selected path is analyzed and shown, including, show pathname, path starting point and end point；
STA to path analyze outbound path slack value and show, emulator to path analyze outbound path slack
It is worth and shows；Obtain STA to path analyze outbound path slack value and emulator path is carried out to analyze to obtain outbound path
Slack value difference between the two and displaying；STA to path analyze outbound path operating frequency value and show and imitative
True device obtains operating frequency value and the displaying of outbound path to path analysis；
The analysis statistical information of voltage scanning, temperature scanning and Monte Carlo scanning is shown with chart mode；
Simulation result is filtered and is sorted.
2. the method for automatic realization static state according to claim 1 and dynamic timing analysis comparison, which is characterized in that described
Step 1) further includes steps of required voltage drive value, temperature in specified design, and needs library file.
3. the method for automatic realization static state according to claim 1 and dynamic timing analysis comparison, which is characterized in that step
3) the calling emulator is emulated, and is to carry out transient analysis to the netlist in each path, is generated corresponding dynamic time sequence
Measurement result file.
4. the method for automatic realization static state according to claim 1 and dynamic timing analysis comparison, which is characterized in that described
Step 4) is that the static analysis report file of reading STA tool and the dynamic measurement report file of emulator generation compare,
Verify the correctness of design.
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| CN108090288B (en) * | 2017-12-21 | 2020-05-12 | 北京华大九天软件有限公司 | Method for acquiring time sequence parameters through machine learning |
| CN112613263B (en) * | 2020-12-31 | 2023-03-03 | 成都海光微电子技术有限公司 | Simulation verification method and device, electronic equipment and computer-readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101137990A (en) * | 2005-02-03 | 2008-03-05 | 赛捷软件公司 | Static timing analysis and dynamic simulation for custom and asic designs |
| CN101464921A (en) * | 2008-12-31 | 2009-06-24 | 北京天碁科技有限公司 | Method and system for generating test vector of chip technology regulation |
| CN102147822A (en) * | 2010-12-23 | 2011-08-10 | 上海高性能集成电路设计中心 | Large-scale digital integrated circuit power dissipation dynamic assessment device based on power dissipation bank |
| CN105183062A (en) * | 2015-08-13 | 2015-12-23 | 东南大学 | Adaptive voltage adjusting system based on online monitoring and monitoring path screening method |
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- 2016-12-29 CN CN201611243054.6A patent/CN106650138B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101137990A (en) * | 2005-02-03 | 2008-03-05 | 赛捷软件公司 | Static timing analysis and dynamic simulation for custom and asic designs |
| CN101464921A (en) * | 2008-12-31 | 2009-06-24 | 北京天碁科技有限公司 | Method and system for generating test vector of chip technology regulation |
| CN102147822A (en) * | 2010-12-23 | 2011-08-10 | 上海高性能集成电路设计中心 | Large-scale digital integrated circuit power dissipation dynamic assessment device based on power dissipation bank |
| CN105183062A (en) * | 2015-08-13 | 2015-12-23 | 东南大学 | Adaptive voltage adjusting system based on online monitoring and monitoring path screening method |
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Address after: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 floor 2, block a, No.2, lizezhong 2nd Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |