CN106601766B

CN106601766B - Quantum dot thin film image sensor structure and manufacturing method thereof

Info

Publication number: CN106601766B
Application number: CN201611184326.XA
Authority: CN
Inventors: 杨冰; 周伟; 胡少坚; 耿阳; 肖慧敏
Original assignee: Shanghai IC R&D Center Co Ltd; Chengdu Light Collector Technology Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Chengdu Light Collector Technology Co Ltd
Priority date: 2016-12-20
Filing date: 2016-12-20
Publication date: 2020-03-20
Anticipated expiration: 2036-12-20
Also published as: CN106601766A

Abstract

The invention discloses a quantum dot thin film image sensor structure and a manufacturing method thereof. The quantum dot thin film image sensor structure at least comprises from bottom to top: a substrate layer, a metal interconnection layer, and a photoelectric conversion layer. The isolation of the isolation structure on the layer forms a plurality of photoelectric conversion units corresponding to and divided into the pixel units of the image sensor. Each photoelectric conversion unit is provided with a quantum dot film for photoelectric conversion, and the quantum dot film is electrically connected to the metal interconnection layer. . The invention absorbs and converts light by using a quantum dot film with stronger light sensitivity, and arranges it on the metal interconnection layer to make it closer to the lens, and adopts an isolation structure as the isolation between pixel units, As a result, the quantum dot thin film image sensor of the present invention can ensure the quality of the output image even in the pixel design of small size.

Description

Quantum dot thin film image sensor structure and manufacturing method thereof

Technical Field

The present invention relates to the field of image sensor technology, and more particularly, to an image sensor structure using quantum dot thin film for photoelectric conversion and a method for manufacturing the same.

Background

An image sensor refers to a device that converts an optical signal into an electrical signal. The CCD image sensor and the CMOS image sensor are mainly widely applied at present.

Quantum dots (quantum dots) are quasi-zero-dimensional nanocrystals composed of a small number of atoms, generally spherical or spheroidal in morphology, nanoparticles made of semiconductor materials (usually composed of IIB-VIB or IIIB-VB elements) with stable diameters of 2-20 nm, which can emit light at specific wavelengths. Screens employing quantum dot technology are easier to calibrate during production, have more accurate color performance, and have significant advantages in color saturation. The image sensor manufactured by the quantum dot film has the advantages of thinner volume, stronger light sensitivity, larger dynamic range and optimized stable imaging.

Conventional image sensors improve resolution by making pixels smaller. This means that each pixel is less sensitive to light, thereby degrading image quality. Compared with CMOS technology, the existing quantum dot film forms a photoelectric conversion unit by coating under a convex mirror, and the characteristic closer to a lens enables the photoelectric conversion unit to capture light more fully, so that the performance of the lens can be improved more effectively.

The quantum dot thin film image sensor manufactured by the new technology can collect light twice as much as the traditional image sensor chip and convert the light into an electric signal with twice efficiency, and meanwhile, the production cost is low.

Therefore, after the quantum dot film is used, the thickness and the volume of the camera of the image sensor can be reduced, and the low-light shooting performance of the image sensor, the dynamic range of images and the like can be greatly improved.

Disclosure of Invention

The invention aims to provide a novel quantum dot thin film image sensor structure for performing photoelectric conversion by adopting a quantum dot thin film and a manufacturing method thereof.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a quantum dot thin film image sensor structure at least comprises from bottom to top: the photoelectric conversion device comprises a substrate layer, a metal interconnection layer and a photoelectric conversion layer; the photoelectric conversion layer is isolated by an isolation structure on the metal interconnection layer to form a plurality of photoelectric conversion units which correspond to and are divided by the image sensor pixel units, each photoelectric conversion unit is provided with a quantum dot film for photoelectric conversion, and the quantum dot film is electrically connected with the metal interconnection layer.

Preferably, a pad is arranged at the periphery of the photoelectric conversion layer, and the quantum dot film and the pad are respectively connected with a metal wire in the metal interconnection layer through a metal electrode and a pad wire.

Preferably, the isolation structure is a multi-layered stacked structure formed in a vertical direction.

Preferably, the isolation structure is a three-layer island structure composed of silicon nitride, silicon dioxide and silicon nitride in sequence from top to bottom and located between the pixel units, and serves as isolation between the pixel units.

A manufacturing method of a quantum dot thin film image sensor structure is used for manufacturing the quantum dot thin film image sensor structure, and comprises the following steps:

step S01: providing a substrate, and forming a metal interconnection layer on the substrate;

step S02: forming a plurality of metal electrodes corresponding to pixel units of the image sensor on the metal interconnection layer;

step S03: forming a first protective layer covering the metal electrode on the metal interconnection layer;

step S04: defining and forming a pad on the first protective layer at the periphery of the pixel region;

step S05: covering and forming a second protective layer on the surfaces of the bonding pad and the first protective layer;

step S06: defining the graph of each pixel unit area in the pixel area, then sequentially removing the second protective layer and the first protective layer to form a plurality of grooves corresponding to the pixel units, and taking the second protective layer material and the first protective layer material reserved between the grooves as an isolation structure between the pixel units;

step S07: and filling quantum dot films into the grooves, and at least covering the metal electrodes in the grooves to form the photoelectric conversion units.

Preferably, the first and second protective layers are formed by forming one or more stacked layer structures.

Preferably, the first protective layer includes a silicon nitride layer located at a lower layer and a silicon dioxide layer located at an upper layer, and the second protective layer includes a silicon nitride layer.

Preferably, the quantum dot thin film is filled in each groove by a spin coating method.

Preferably, the filling height of the quantum dot thin film does not exceed the height of the first protective layer.

Preferably, the metal interconnection layer structure is formed by standard CMOS process.

According to the technical scheme, the quantum dot film with higher light sensitivity is used for absorbing and converting light, and is arranged on the metal interconnection layer, so that the quantum dot film is closer to the lens, and meanwhile, the isolation structure is used as isolation between pixel units, so that the light can be captured more fully, the performance of the lens can be improved more effectively, the quality of an output image can be ensured even in a small-size pixel design, and compared with a CMOS image sensor with the same pixel size, the quantum dot film image sensor has higher light sensitivity, a larger dynamic range and more optimized imaging stability.

Drawings

Fig. 1 is a schematic structural diagram of a quantum dot thin film image sensor according to a preferred embodiment of the invention;

fig. 2-26 are process flow diagrams of a method for fabricating a quantum dot thin film image sensor structure according to a preferred embodiment of the invention.

Detailed Description

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.

In the following detailed description of the present invention, please refer to fig. 1, in which fig. 1 is a schematic structural diagram of a quantum dot thin film image sensor according to a preferred embodiment of the present invention. As shown in fig. 1, a quantum dot thin film image sensor structure of the present invention may include, from bottom to top: the photoelectric conversion layer comprises a substrate layer A, a metal interconnection layer B and a photoelectric conversion layer C. Wherein, the substrate layer can be formed by adopting an N-type or P-type double-sided polished silicon wafer 1 material. The substrate silicon wafer 1 can be manufactured with the related control and readout circuits of the image sensor. A layer of oxide material, such as silicon dioxide, may be used as the substrate isolation layer 2 between the substrate silicon wafer 1 and the metal interconnect layer B.

A plurality of metal interconnection layers B (a two-layer metal interconnection layer structure is exemplarily illustrated in the figure) may be provided above the substrate isolation layer 2; the metal connecting wires 5 and 8 in the metal interconnection layers can be connected with each other through holes. Each layer of metal connecting line is arranged in a dielectric layer material of a corresponding metal interconnection layer, for example, silicon dioxide can be used as the dielectric layer material, the first layer of metal connecting line 5 is arranged in the dielectric layer material 3 of the first layer of metal interconnection layer, and the second layer of metal connecting line 8 is arranged in the dielectric layer material 7 of the second layer of metal interconnection layer; and may be isolated between the two metal

interconnect layer dielectrics

3 and 7 using an isolation layer 6 such as a silicon nitride material. The metal interconnect layer may be formed by standard CMOS process fabrication.

The photoelectric conversion layer C is located on the metal interconnection layer B, and includes a plurality of

photoelectric conversion units

15 and 9 corresponding to the image sensor pixel units. The photoelectric conversion units are isolated from each other between pixels by an isolation structure 14 provided on the metal interconnection layer, thereby forming a plurality of

photoelectric conversion units

15 and 9 corresponding to and divided from the image sensor pixel unit. The isolation structure 14 is a multi-layered stacked structure formed in a vertical direction. For example, the isolation structure 14 may adopt a three-layer island-shaped structure composed of a silicon nitride layer 13, a silicon dioxide layer 11, and a silicon nitride layer 10 in this order from top to bottom between pixel units as isolation between the pixel units. The island-shaped isolation structure can greatly reduce crosstalk and electric leakage among pixels.

Each photoelectric conversion unit is provided with a quantum dot film 15 for performing photoelectric conversion, and the quantum dot film 15 may be disposed in a groove formed between the isolation structures 14 by filling. The position of each groove corresponds to the area of a pixel. The quantum dot film 15 of each photoelectric conversion unit can be electrically connected with the uppermost metal interconnection layer through the metal electrode 9 covered by the quantum dot film and arranged below the quantum dot film. The filling height of the quantum dot film 15 should not exceed the height of the isolation structure 14; preferably, since the uppermost silicon nitride layer 13 in the isolation structure 14 is usually thin, the filling height of the quantum dot film 15 should not exceed the height of the silicon dioxide interlayer 11.

A pad structure 12 can be arranged on the periphery of the photoelectric conversion layer, the pad 12 can be established on the

dielectric layers

10 and 11 on the metal interconnection layer on the periphery of the photoelectric conversion layer, and the metal connecting wire 8 in the uppermost metal interconnection layer is connected through a pad connecting wire penetrating through the

dielectric layers

11 and 10. The dielectric layer may include a silicon nitride layer 10 and a silicon dioxide layer 11 from bottom to top, and a pad protection layer 13 may cover the surface of the pad structure 12, for example, a silicon nitride material may be used for pad protection, and an opening area for subsequent electrical testing and packaging is left on the surface of the pad.

There may also be other structures above the photoelectric conversion units that form the image sensor, for example, a lens structure or the like may be provided above the quantum dot film-filled groove in each photoelectric conversion unit.

The following describes in detail a method for manufacturing the quantum dot thin film image sensor structure according to the present invention, with reference to specific embodiments.

Referring to fig. 2-26, fig. 2-26 are process flow diagrams of a method for fabricating a quantum dot thin film image sensor structure according to a preferred embodiment of the invention. As shown in fig. 2 to fig. 26, a method for manufacturing a quantum dot thin film image sensor structure according to the present invention may include the following steps:

step S01: a substrate is provided, and a metal interconnection layer is formed on the substrate.

Please refer to fig. 2. The substrate layer a in fig. 1 can be formed by using an N-type or P-type double-side polished silicon wafer material 1. Then, silicon dioxide is grown on the surface of the substrate silicon wafer 1 as a substrate isolation layer 2. The temperature of the growth process of the silicon dioxide substrate isolation layer 2 can be 900-1050 ℃, and the thickness of the silicon dioxide can be 0.5-1 micron.

Please refer to fig. 3. Next, silicon dioxide continues to grow on the substrate isolation layer 2 as an isolation dielectric 3 between the first (lowermost) metal interconnect layer metal line and the substrate. The silicon dioxide isolation medium 3 may be grown by Chemical Vapor Deposition (CVD), and may be formed of boron glass (BSG), phosphorous glass (PSG), boron phosphorous glass (BPSG) or bd (black diamond), and the silicon dioxide may have a thickness of 0.3 to 0.5 μm.

Please refer to fig. 4. Then, coating photoresist on the surface of the device, and defining a metal connecting line area in the first metal interconnection layer through exposure and development.

Please refer to fig. 5. Then, the silicon dioxide medium 3 of the first metal interconnection layer can be etched by adopting an anisotropic dry etching process, and then the residual photoresist is removed to form a pattern required by the first metal connecting line.

Please refer to fig. 6. Next, a Physical Vapor Deposition (PVD) method may be employed to perform Cu barrier seed (copper seed layer) 4 growth in the first layer metal wiring pattern trench; cu is then grown by ECP (electro-deposition) as the first layer of metal line 5, which may have a thickness of 0.8-1 micron. And then, a CMP method can be adopted for planarization, and the redundant Cu is removed.

Please refer to fig. 7. Then, a layer of silicon nitride can be grown to serve as an isolation layer 6 between the second metal interconnection layer and the first metal interconnection layer; then a layer of silicon dioxide is grown again to be used as a dielectric layer material 7 of the second metal interconnection layer. The silicon nitride layer 6 and the silicon dioxide layer 7 form an isolation between the subsequent second layer metal line and the first layer metal line 5. Silicon nitride and silicon dioxide can be grown using Chemical Vapor Deposition (CVD); the silicon dioxide may be boron glass (BSG), phosphorous glass (PSG), borophosphorous glass (BPSG), or bd (black diamond); the silicon dioxide thickness may be between 0.3 microns and 0.5 microns and the silicon nitride thickness may be about 0.05 microns.

Please refer to fig. 8. Then, coating photoresist on the surface of the obtained structure, and defining a metal connecting line area in the second metal interconnection layer through exposure and development.

Please refer to fig. 9. Then, the silicon dioxide dielectric layer 7 can be etched by adopting an anisotropic dry etching process, and then, the residual photoresist is removed to form a pattern required by the second layer of metal connecting line.

Please refer to fig. 10. Then, a photoresist is coated on the surface of the obtained structure, and through hole areas are defined through exposure and development.

Please refer to fig. 11. Then, the silicon dioxide dielectric layer 7 and the silicon nitride isolation layer 6 can be etched by adopting an anisotropic dry etching process, and then the residual photoresist is removed to form a pattern required by a through hole for connecting the first layer metal connecting wire and the second layer metal connecting wire.

Please refer to fig. 12. Next, Cu barrier seed growth may be performed in the second-layer metal wiring pattern trench and via pattern using a Physical Vapor Deposition (PVD) method, and then Cu may be grown as the second-layer metal wiring 8 using an ECP method, which may have a thickness of 0.8 to 1 μm. Then, a CMP method is used to planarize and remove the excess Cu.

For a structure with more than 2 layers of metal connecting wires, the steps can be repeated, and the structure with a plurality of metal interconnection layers is manufactured through a standard CMOS process.

Step S02: and forming a plurality of metal electrodes corresponding to pixel units of the image sensor on the metal interconnection layer.

Please refer to fig. 13. The metal titanium nitride can be sputtered on the surface of the uppermost metal interconnection layer structure by adopting a Physical Vapor Deposition (PVD) method to serve as a metal electrode layer material 9 of the quantum dot film, and the thickness of the titanium nitride can be 0.5-1 micron.

Please refer to fig. 14. Then, a photoresist is coated on the surface of the titanium nitride metal electrode layer material 9, and then a metal electrode area required by the quantum dot film is defined through exposure and development.

Please refer to fig. 15. Then, an anisotropic dry etching process may be used to etch and remove the titanium nitride in the non-photoresist masking region, and then remove the remaining photoresist to form a plurality of metal electrodes 9 corresponding to the pixel units of the image sensor.

Step S03: and forming a first protective layer covering the metal electrode on the metal interconnection layer.

Please refer to fig. 16. Next, a silicon nitride protective layer 10 and a silicon dioxide protective layer 11 may be grown on the surface of the above structure by using a CVD method to form the first

protective layers

10 and 11. Wherein, the thickness of the silicon nitride layer can be 0.1 to 0.2 microns, and the thickness of the silicon dioxide layer can be 0.3 to 0.5 microns.

Step S04: a pad is defined and formed on the first protective layer at the periphery of the pixel region.

Please refer to fig. 17. Next, a photoresist is coated on the surface of the silicon dioxide protective layer 11, and then a pad opening region is defined at the periphery of the pixel region by exposure and development.

Please refer to fig. 18. Then, the silicon dioxide protective layer 11 and the silicon nitride protective layer 10 can be etched by adopting an anisotropic dry etching process, and the metal interconnection layer on the uppermost layer is stopped; and then removing the residual photoresist to form a metal aluminum filling area.

Please refer to fig. 19. Then, a Physical Vapor Deposition (PVD) method may be used to sputter metallic aluminum on the surface of the above structure as the pad connecting wire and pad material 12, and the thickness of the metallic aluminum may be 0.8 to 1 micron.

Please refer to fig. 20. And then, coating photoresist on the surface of the structure, and then exposing and developing to protect the metal aluminum of the peripheral pad region and expose the metal aluminum of the middle pixel region.

Please refer to fig. 21. Next, the metal aluminum layer 12 in the pixel region may be removed by etching using an anisotropic dry etching process, and then the remaining photoresist is removed, and the remaining metal aluminum layer forms the pad structure 12.

Step S05: and covering and forming a second protective layer on the surface of the bonding pad and the surface of the first protective layer.

Please refer to fig. 22. Then, a layer of silicon nitride can be grown by Chemical Vapor Deposition (CVD) as the protective layer 13 of the pad to avoid damage to the pad by the subsequent etching process, and at the same time, the silicon nitride can also be used as the second protective layer 13 on the first protective layer. The silicon nitride layer may have a thickness of 0.5 to 1 micron.

The first and second protective layers may be formed by forming one or more stacked layers.

Step S06: defining the pattern of each pixel unit area in the pixel area, then removing the second protective layer and the first protective layer in sequence to form a plurality of grooves corresponding to the pixel units, and taking the second protective layer material and the first protective layer material reserved between the grooves as the isolation structure between the pixel units.

Please continue to refer to fig. 22. Then, a photoresist is coated on the surface of the structure, and then through exposure and development, a pattern of each pixel unit area is defined, namely, areas in each pixel unit area, which need to etch the silicon nitride layer 13 (the second protection layer 13), the silicon dioxide layer 11 and the silicon nitride layer 10 (the first protection layers 11 and 10), are defined.

Please refer to fig. 23. Next, the silicon nitride layer 13, the silicon dioxide layer 11 and the silicon nitride layer 10 in the non-photoresist masking region may be removed by etching using an anisotropic dry etching process, so as to expose the titanium nitride metal electrode 9 in each pixel unit region. The remaining photoresist is then removed to form a plurality of recesses corresponding to the pixel units, and the second and first protective layer materials remaining between the recesses form isolation structures 14 between the pixel units. The isolation structure 14 is a three-layer island-like structure consisting of the silicon nitride layer 13, the silicon dioxide layer 11, and the silicon nitride layer 10 in this order from top to bottom, which remains between pixels, as isolation between pixels, which can greatly reduce crosstalk and leakage between pixels.

Please refer to fig. 24. Next, a photoresist is coated on the surface of the structure, and then a pad opening region located above the pad structure 12 is defined through exposure and development.

Please refer to fig. 25. Then, the silicon nitride layer 13 without the photoresist masking region can be removed by adopting an anisotropic dry etching process, and the metal aluminum on the bonding pad 12 is exposed, so that the subsequent electrical test and packaging are facilitated; the remaining photoresist is then removed.

Please refer to fig. 26. Finally, the quantum dot thin film 15 can be filled in each groove by adopting a spin coating method so as to obtain better uniformity. The quantum dot film 15 completely covers the titanium nitride metal electrode 9, thereby forming respective

photoelectric conversion units

15 and 9 for light absorption and conversion in each groove. The filling height of the quantum dot film 15 should not exceed the height of the isolation structure 14; preferably, since the uppermost silicon nitride layer 13 in the isolation structure 14 is generally thin, the filling height of the quantum dot film 15 should not exceed the height of the silicon dioxide intermediate layer 11 (i.e., the first protection layer). The filling height of the quantum dot film 15 may be 100 to 1000 nm, for example, about 500 nm. The quantum dot film can also be filled in each groove by adopting a spraying method or other suitable methods.

Thereafter, the CMOS standard process may be continued to form other structures of the image sensor above the photoelectric conversion units, for example, a lens structure may be fabricated above the quantum dot film-filled groove in each photoelectric conversion unit.

In summary, the quantum dot thin film image sensor of the present invention absorbs and converts light by using the quantum dot thin film with stronger light sensitivity, and the quantum dot thin film is disposed on the metal interconnection layer, so that the quantum dot thin film image sensor is closer to the lens, and meanwhile, the isolation structure is used as isolation between the pixel units, so that light can be captured more fully, and thus the performance of the lens can be improved more effectively, so that the quantum dot thin film image sensor of the present invention can ensure the quality of an output image even in a small-sized pixel design.

The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims

1. A manufacturing method of a quantum dot thin film image sensor structure is characterized by comprising the following steps:

2. The method of claim 1, wherein the first and second passivation layers are formed by forming one or more stacked layers.

3. The method of claim 1, wherein the first protective layer comprises a silicon nitride layer on a lower layer and a silicon dioxide layer on an upper layer, and the second protective layer comprises a silicon nitride layer.

4. The method of claim 1, wherein the quantum dot thin film is filled in each groove by spin coating.

5. The method of claim 1, wherein the filling height of the quantum dot thin film does not exceed the height of the first protective layer.

6. The method of claim 1, wherein the metal interconnect layer structure is formed in multiple layers by standard CMOS process fabrication.