CN106601759B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Abstract

The present invention provides a semiconductor device, a manufacturing method thereof, and an electronic device, and relates to the technical field of semiconductors. Including: providing a top wafer, in which a plurality of pixel units are formed; providing a bottom wafer, bonding the front side of the top wafer and the front side of the bottom wafer; bonding the back side of the top wafer performing a thinning process; depositing a semiconductor material layer on the backside of the top wafer, and patterning the semiconductor material layer to form a plurality of grids; depositing a protective layer to cover the backside of the top wafer and each the grille. According to the manufacturing method of the present invention, the SiGe grid is formed on the area corresponding to the pixel unit on the back side of the top wafer, which can reduce the generation of various crosstalk problems. At the same time, the protective layer is formed after the grid is formed, which can effectively improve the pattern. quality, thereby improving the performance of the device.

Description

A semiconductor device and its manufacturing method and electronic device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device, a manufacturing method thereof, and an electronic device.

Background technique

Backside illuminated (BSI) image sensors can reduce/avoid the absorption and reflection of light by circuit layers or oxide layers, so they have higher sensitivity and signal-to-noise ratio. To improve photon capture efficiency, many high-performance CMOS image sensors are now backside illuminated (BSI) image sensors.

During the development of the BSI process technology, it was suffering from crosstalk problems. It mainly includes the following types of crosstalk: spectral crosstalk, optical crosstalk and electrical crosstalk.

Among them, spectral crosstalk is caused by the characteristics of the color filter. Optical crosstalk is induced by photon penetration into adjacent pixels. Photon reflection or diffraction in the back-end stack structure is improved in BSI sensors, but optical crosstalk in silicon is still a serious problem because it is impossible to suppress optical crosstalk by injection isolation. Electrical crosstalk is the diffusion or drift of electrons to other pixels.

There are several methods to improve the optical crosstalk of BSI image sensors: One method is to form a polysilicon deep trench isolation structure between adjacent pixel regions. However, the deposition temperature of polysilicon is high, about 500 °C, and the high temperature will Negatively affects the functionality of photodiodes and ROC ICs; another approach is to use metal grid shielding to improve optical crosstalk by forming an oxide layer and a silicon nitride layer in sequence on the backside of the wafer, nitrogen A metal layer is formed on the silicon nitride layer, a patterned photoresist is formed on the metal layer, and the patterned photoresist is used as a mask to etch the metal layer and stop on the silicon nitride layer to form a grid. During the process of the metal layer, the silicon nitride layer is easily damaged, and the thickness of the silicon nitride layer affects the quantum efficiency (Quantum Efficiency, QE for short) of the device.

Therefore, it is necessary to propose a new semiconductor device and its manufacturing method to solve the above-mentioned technical problems.

SUMMARY OF THE INVENTION

A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.

In view of the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising:

Step S1: providing a top wafer in which a plurality of pixel units are formed;

Step S2: providing a bottom wafer, and bonding the front side of the top wafer and the front side of the bottom wafer;

Step S3: thinning the backside of the top wafer;

Step S4: depositing a semiconductor material layer on the backside of the top wafer, and patterning the semiconductor material layer to form a plurality of grids;

Step S5: depositing a protective layer to cover the backside of the top wafer and each of the grids.

Further, each of the grids is formed of a box shape surrounded by four strip structures, and each pixel unit of the top wafer corresponds to one of the grids.

Further, between the step S3 and the step S4, the method further includes: forming an oxide layer on the backside of the top wafer.

Further, the thickness of the oxide layer ranges from 80 to 200 angstroms.

Further, in the step S4, the step of patterning the semiconductor material layer includes: forming a patterned photoresist on the semiconductor material layer, and etching the semiconductor material layer by using the patterned photoresist as a mask stopping on the oxide layer to form the plurality of grids.

Further, the thickness of the semiconductor material layer ranges from 1500 to 2500 angstroms.

Further, the material of the semiconductor material layer includes SiGe.

Further, the material of the protective layer includes silicon nitride.

Further, the bottom wafer includes a plurality of CMOS devices formed on the front side of the bottom wafer, an interlayer dielectric layer on the plurality of CMOS devices on the front side of the bottom wafer, and an interlayer dielectric layer on the front side of the bottom wafer. A wiring layer connected to each of the CMOS devices in the layers.

Further, the following steps are also included after the step S5:

Starting from the back of the top wafer, etching the top wafer outside the grid and part of the bottom wafer until the bottom metal layer of the wiring layer in the bottom wafer is exposed to form openings;

forming an intermetallic oxide on the backside of the top wafer and on the sidewalls of the opening;

forming a pad material layer on the backside of the top wafer and on the intermetallic oxide in the opening;

The central area of the pad material layer in the opening is etched, and the pad material layer on the sidewalls and the bottom of the opening is retained to form a pad.

The second embodiment of the present invention provides a semiconductor device, including:

a top wafer having a plurality of pixel units formed in the top wafer, a plurality of grids formed on the backside of the top wafer, and a plurality of grids covering each of the grids and the backside of the top wafer a protective layer, wherein the material of the grid is a semiconductor material;

Bottom wafer, front side of top wafer and front side of bottom wafer are bonded.

Further, an oxide layer is formed on the backside of the top wafer under the grid.

Further, the thickness of the oxide layer ranges from 80 to 200 angstroms.

Further, the height of the grid ranges from 1500 to 2500 angstroms.

Further, the semiconductor material includes SiGe.

Further, each of the grids is formed of a box shape surrounded by four strip structures, and each pixel unit of the top wafer corresponds to one of the grids.

Further, the bottom wafer includes a plurality of CMOS devices formed on the front side of the bottom wafer, an interlayer dielectric layer on the plurality of CMOS devices on the front side of the bottom wafer, and an interlayer dielectric layer on the front side of the bottom wafer. The wiring layers in the layers are respectively connected to each CMOS device.

Further, it also includes an opening that starts from the back of the top wafer and runs through the top wafer outside the grid and part of the bottom wafer, and the bottom of the opening is located at the bottom of the wiring layer in the bottom wafer. On the surface of the bottom metal layer, an intermetallic oxide is formed on the backside of the top wafer and the sidewall of the opening, and the metal on the backside of part of the top wafer and the sidewall and bottom of the opening Pads are formed on the inter-oxide layer.

The second embodiment of the present invention provides an electronic device including the aforementioned semiconductor device.

To sum up, according to the semiconductor device manufacturing method of the present invention, forming a SiGe grid on the area corresponding to the pixel unit on the backside of the top wafer can reduce the generation of various crosstalk problems, and at the same time protect the grid after the grid is formed. The production of layers can effectively improve the quality of the graphics, thereby improving the performance of the device.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

1A-1F show schematic cross-sectional views of a semiconductor device in an embodiment of the present invention;

FIG. 2 shows a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

For a thorough understanding of the present invention, detailed structures and manufacturing processes will be presented in the following description, in order to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Example 1

Hereinafter, with reference to FIGS. 1A to 1F and FIG. 2 , a method for fabricating a semiconductor device provided by an embodiment of the present invention will be described. Exemplarily, the semiconductor device of the present invention is a backside illuminated (BSI) image sensor, wherein FIGS. 1A-1F show schematic cross-sectional views of the semiconductor device in an embodiment of the present invention, and FIG. 2 shows a schematic diagram of a semiconductor device according to an embodiment of the present invention. A schematic flowchart of a method of manufacturing a semiconductor device in an embodiment.

First, as shown in FIG. 1A , a top wafer 100 is provided, and a plurality of CMOS devices 101 are formed on the front side of the top wafer 100 .

Specifically, the top wafer 100 includes a semiconductor substrate 1001, and the semiconductor substrate 1001 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), and the like.

In one embodiment, a pixel region is further included in the top wafer, and the pixel region includes a plurality of pixel units arranged in an array in the semiconductor substrate. The photodiode array includes a plurality of photodiodes and a plurality of pixel transistors distributed throughout the semiconductor substrate in the pixel region.

Exemplarily, a plurality of CMOS devices 101 are formed on the front surface of the semiconductor substrate 1001, wherein the CMOS devices are constituent elements of the pixel unit, and each CMOS device 101 includes a well region formed in the semiconductor substrate 1001 and located in the well region. The source and drain in the source and drain, and the gate structure on the surface of the semiconductor substrate between the source and the drain, etc. Wherein, an isolation structure 102 is also formed in the semiconductor substrate 1001 on the front side of the top wafer 100 to isolate the adjacent CMOS devices 101 . In this embodiment, the isolation structure 102 is preferably a shallow trench isolation structure.

A wiring layer 103 is formed on each of the CMOS devices 101 . Exemplarily, an interlayer dielectric layer 104 covering the surface of the semiconductor substrate 1001 is also formed on the front surface of the top wafer 100 , and the wiring layer 103 is formed in the interlayer dielectric layer 104 . The interlayer dielectric layer 104 may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high density plasma (HDP) manufacturing process, For example undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorous-doped spin-on-glass (SOG), phosphorous-doped tetraethoxysilane (PTEOS) or boron-doped of tetraethoxysilane (BTEOS).

In one example, the wiring layer 103 is composed of multiple metal layers and metal vias connecting adjacent metal layers. The multiple metal layers may include an aluminum metal layer on the lower layer and a copper metal layer on the top layer. The wiring layer 103 can be formed by any method well known to those skilled in the art.

Next, as shown in FIG. 1B , a bottom wafer 200 is provided, and the front side of the top wafer 100 and the front side of the bottom wafer 200 are bonded.

Further, the bottom wafer 200 includes a plurality of CMOS devices 201 formed on the front side of the bottom wafer 200, an interlayer dielectric layer 204 located on the plurality of CMOS devices 201 on the front side of the bottom wafer 200, and A wiring layer 203 in the interlayer dielectric layer 204 is connected to each CMOS device 201 .

Specifically, the bottom wafer 200 includes a semiconductor substrate 2001, which may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), and the like.

A plurality of CMOS devices 201 are formed on the front surface of the semiconductor substrate 2001, and each CMOS device 201 includes a well region formed in the semiconductor substrate 2001, a source electrode and a drain electrode located in the well region, and a source electrode and a drain electrode located in the well region. The gate structure on the surface of the semiconductor substrate between the poles, etc. Wherein, an isolation structure 202 is also formed in the semiconductor substrate 2001 on the front side of the bottom wafer 200 to isolate the adjacent CMOS devices 201 . In this embodiment, the isolation structure 202 is preferably a shallow trench isolation structure.

A wiring layer 203 is formed on each of the plurality of CMOS devices 201 . Exemplarily, an interlayer dielectric layer 204 covering the surface of the semiconductor substrate 2001 is also formed on the front surface of the top wafer 200 , and the wiring layer 203 is formed in the interlayer dielectric layer 204 . The interlayer dielectric layer 204 may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high density plasma (HDP) manufacturing process, For example undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorous-doped spin-on-glass (SOG), phosphorous-doped tetraethoxysilane (PTEOS) or boron-doped of tetraethoxysilane (BTEOS).

In one example, the wiring layer 203 is composed of multiple metal layers and metal vias connecting adjacent metal layers, the wiring layer 203 may be a copper interconnect structure, and the wiring layer 203 is connected to each CMOS transistor 201 . The wiring layer 203 can be formed by any method well known to those skilled in the art.

The front side of the top wafer 100 and the front side of the bottom wafer 200 are bonded. This bonding step may be performed using any suitable bonding method, eg, oxide fusion bonding, and the like.

Continuing to refer to FIG. 1B , a thinning process is performed on the backside of the top wafer 100 .

The thinning process in this step can be performed by any method well known to those skilled in the art, for example, an etching process or a back grinding process. In this embodiment, a back grinding process is preferably used for thinning. Exemplarily, after thinning, the remaining thickness of the top wafer ranges from 2 to 3 μm.

Next, as shown in FIG. 1B , an oxide layer 105 is formed on the backside of the top wafer 100 .

The material of the oxide layer 105 may include materials such as silicon oxide or silicon oxynitride. Exemplarily, the thickness of the oxide layer 105 ranges from 80 to 200 angstroms. In this embodiment, the thickness of the oxide layer 105 is preferably 160 angstroms. The oxide layer 105 may be formed using any deposition method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, and the like.

Next, as shown in FIGS. 1C-1D , a semiconductor material layer 106 a is deposited on the backside of the top wafer 100 , and the semiconductor material layer 106 a is patterned to form a plurality of grids 106 .

The material of the semiconductor material layer 106a can be any suitable semiconductor material, such as Ge, SiGe, etc. In this embodiment, the material of the semiconductor material layer 106a is preferably SiGe. Any suitable deposition method can be used to form SiGe, among which, PECVD process is preferably used, and a relatively low deposition temperature is used, eg, a deposition temperature of 250°C. Optionally, the thickness of the semiconductor material layer ranges from 1500 to 2500 angstroms. The above thicknesses are only exemplary, and any other suitable thickness ranges may also be suitable for use in the present invention.

In one example, the step of patterning the semiconductor material layer 106a includes: forming a patterned photoresist on the semiconductor material layer 106a, and using the patterned photoresist as a mask to stop etching the semiconductor material layer 106a on the oxide layer 105 to form the plurality of grids 106 . Exemplarily, each of the grids 106 is composed of a box shape surrounded by four strip-like structures, and each pixel unit of the top wafer corresponds to one of the grids, in other words, the gaps in the grids 106 The size of can be approximately equal to the size of each pixel unit. Wherein, the grid 106 may be formed by a method of forming a plurality of openings exposing the oxide layer 105 by etching the multi-semiconductor material layer 106a, and the size of the openings may be defined to be substantially the same as the size of each pixel unit, wherein the openings can be square or other suitable shapes. Any suitable dry etching or wet etching process can be used for the etching of the semiconductor material layer 106a. In this embodiment, a dry etching process including etchants Cl ₂ and HBr is preferably used. The method of etching has a high selectivity of semiconductor materials to oxides.

Further, in a plane view, the plurality of grids 106 are formed by a plurality of crisscrossed and parallel strip-like structures at intervals, and the spacing distance between adjacent strip-like structures may be approximately the same as the size of the pixel unit.

Next, as shown in FIG. 1E , a protective layer 107 is deposited to cover the backside of the top wafer 100 and each of the grids 106 .

Specifically, the protective layer 107 may include any suitable insulating material, such as SiO ₂ , SiN, SiON or SiON ₂ . In this embodiment, the material of the protective layer 107 preferably includes SiN. The formation process of the protective layer 107 may adopt any existing technology known to those skilled in the art, and a chemical vapor deposition method is more preferred. Wherein, the thickness of the protective layer 107 is in the range of 100 to 1000 angstroms, for example, 200 angstroms, 500 angstroms, 600 angstroms, and the like.

Next, as shown in FIG. 1F , starting from the backside of the top wafer 100 , the top wafer 100 and part of the bottom wafer 200 outside the grid 106 are etched until the bottom wafer 200 is exposed. up to the bottom metal layer of the wiring layer 203 to form openings; intermetallic oxides 108 are formed on the sidewalls of the openings and on the backside of the top wafer 100 ; in the openings and part of the backside of the top wafer 100 A pad material layer is formed on the intermetallic oxide 108; the central area of the pad material layer in the opening is etched, and the pad material layer on the sidewall and bottom of the opening is retained to form a pad 109 .

Exemplarily, the protective layer 107 , the oxide layer 105 , the semiconductor substrate 1001 and the interlayer dielectric layer 104 on the backside of the top wafer 100 may be etched in sequence, and then part of the interlayer dielectric layer on the front side of the bottom wafer 200 may be etched. layer 204 until the bottom metal layer of the wiring layer 203 in the bottom wafer 200 is exposed to form openings. The etching of the semiconductor substrate 1001 and the interlayer dielectric layers 104 and 204 may be performed by any method known to those skilled in the art, such as dry etching or wet etching.

The material of the intermetallic oxide 108 may include silicon oxide, silicon oxynitride, and the like. The intermetallic oxide 108 may be formed by chemical vapor deposition, physical vapor deposition, thermal oxidation, or the like.

A pad material layer is formed in the opening and on the intermetallic oxide 108 on the back side of part of the top wafer 100; the central area of the pad material layer in the opening is etched, leaving the opening sidewalls and A layer of pad material on the bottom to form pad 109 . Wherein, the material of the pad material layer can be any suitable metal material, such as gold, silver, aluminum, copper, etc. In this embodiment, the material of the pad material layer preferably includes aluminum.

So far, the key fabrication steps of the semiconductor device of the present invention have been completed. In the embodiment of the present invention, other steps may be included after the pad is formed, which is not limited herein.

To sum up, according to the semiconductor device manufacturing method of the present invention, forming a SiGe grid on the area corresponding to the pixel unit on the backside of the top wafer can reduce the generation of various crosstalk problems, and at the same time protect the grid after the grid is formed. The production of layers can effectively improve the quality of the graphics, thereby improving the performance of the device.

Referring to FIG. 2 , it is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which is used to briefly illustrate the flow of the entire manufacturing process.

Step S201: providing a top wafer in which a plurality of pixel units are formed;

Step S202: providing a bottom wafer, and bonding the front side of the top wafer and the front side of the bottom wafer;

Step S203: thinning the backside of the top wafer;

Step S204: depositing a semiconductor material layer on the backside of the top wafer, and patterning the semiconductor material layer to form a plurality of grids;

Step S205 : depositing a protective layer to cover the backside of the top wafer and each of the grids.

Embodiment 2

Hereinafter, the semiconductor device proposed by the embodiment of the present invention will be described with reference to FIG. 1F . Illustratively, the semiconductor device of the present invention is a backside illuminated (BSI) image sensor.

As shown in FIG. 1F , the semiconductor device of the present invention includes a top wafer 100 , a plurality of CMOS devices 101 are formed on the front side of the top wafer 100 , and a wiring layer 103 is formed on each of the CMOS devices 101 . A plurality of grids 106 are formed on the backside of the top wafer 100, and a protective layer 107 covering each of the grids 106 and the backside of the top wafer 100, wherein the material of the grids 106 is semiconductor Material.

Specifically, the top wafer 100 includes a semiconductor substrate 1001, and the semiconductor substrate 1001 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), and the like. Exemplarily, the thickness of the top wafer ranges from 2 to 3 μm.

In one embodiment, the semiconductor device of the present invention is a BSI CMOS image sensor, and the BSI CMOS image sensor includes a pixel area and a peripheral circuit area disposed around the pixel area. The pixel area includes a plurality of pixel units arranged in an array in a semiconductor substrate formed of silicon. The photodiode array includes a plurality of photodiodes and a plurality of pixel transistors distributed throughout the semiconductor substrate in the pixel region.

Among them, a plurality of CMOS devices 101 are formed on the front surface of the semiconductor substrate 1001, and the CMOS devices can be used as components of the pixel unit. Each CMOS device 101 includes a well region formed in the semiconductor substrate 1001, and a The source and drain, and the gate structure on the surface of the semiconductor substrate between the source and the drain, etc. Wherein, an isolation structure 102 is also formed in the semiconductor substrate 1001 on the front side of the top wafer 100 to isolate the adjacent CMOS devices 101 . In this embodiment, the isolation structure 102 is preferably a shallow trench isolation structure.

A wiring layer 103 is formed on each of the plurality of CMOS devices 101 . Exemplarily, an interlayer dielectric layer 104 covering the surface of the semiconductor substrate 1001 is also formed on the front surface of the top wafer 100 , and the wiring layer 103 is formed in the interlayer dielectric layer 104 . The interlayer dielectric layer 104 can be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high density plasma (HDP) manufacturing process, For example undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorous-doped spin-on-glass (SOG), phosphorous-doped tetraethoxysilane (PTEOS), or boron-doped of tetraethoxysilane (BTEOS).

In one example, the wiring layer 103 is composed of multiple metal layers and metal vias connecting adjacent metal layers. The multiple metal layers may include an aluminum metal layer on the lower layer and a copper metal layer on the top layer. The wiring layer 103 can be formed by any method well known to those skilled in the art.

Exemplarily, each of the grids 106 is composed of a square frame surrounded by four strip-like structures, and each pixel unit of the top wafer corresponds to one of the grids, in other words, the bars in the grid 106 The size of the gap between the like structures can be approximately equal to the size of each pixel unit. Further, the plurality of grids 106 are formed by a plurality of crisscrossed and parallel strip-like structures at intervals, and the spacing distance between adjacent strip-like structures may be approximately the same as the size of the pixel unit.

The semiconductor material can be any suitable semiconductor material, such as Ge, SiGe, etc. In this embodiment, the preferred semiconductor material is SiGe. Any suitable deposition method can be used to form SiGe, among which, PECVD process is preferably used, and a relatively low deposition temperature is used, eg, a deposition temperature of 250°C. Optionally, the height of the grid 106 may range from 1500 to 2500 angstroms. The grid 106 can effectively shield crosstalk between pixels.

Further, an oxide layer 105 is formed on the backside of the top wafer 100 and below the grid 106 . The material of the oxide layer 105 may include materials such as silicon oxide or silicon oxynitride. Exemplarily, the thickness of the oxide layer 105 ranges from 80 to 200 angstroms. In this embodiment, the thickness of the oxide layer 105 is preferably 160 angstroms.

The semiconductor device of the present invention further includes a bottom wafer 200, and the front side of the top wafer 100 and the front side of the bottom wafer 200 are bonded.

The bottom wafer 200 includes a plurality of CMOS devices 201 formed on the front side of the bottom wafer 200, an interlayer dielectric layer 204 on the front side of the bottom wafer 200 on the plurality of CMOS devices 201, and an interlayer dielectric layer 204 on the front side of the bottom wafer 200. A wiring layer 203 in the interlayer dielectric layer 204 is connected to each CMOS device 201 .

Specifically, the bottom wafer 200 includes a semiconductor substrate 2001, which may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), and the like.

A plurality of CMOS devices 201 are formed on the front surface of the semiconductor substrate 2001, and each CMOS device 201 includes a well region formed in the semiconductor substrate 2001, a source electrode and a drain electrode located in the well region, and a source electrode and a drain electrode located in the well region. The gate structure on the surface of the semiconductor substrate between the poles, etc. Wherein, an isolation structure 202 is also formed in the semiconductor substrate 2001 on the front side of the bottom wafer 200 to isolate the adjacent CMOS devices 201 . In this embodiment, the isolation structure 202 is preferably a shallow trench isolation structure.

A wiring layer 203 is formed on each of the CMOS devices 201 . Exemplarily, an interlayer dielectric layer 204 covering the surface of the semiconductor substrate 2001 is also formed on the front surface of the top wafer 200 , and the wiring layer 203 is formed in the interlayer dielectric layer 204 . The interlayer dielectric layer 204 may be a silicon oxide layer, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high density plasma (HDP) manufacturing process, For example undoped silica glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer can also be boron-doped or phosphorous-doped spin-on-glass (SOG), phosphorous-doped tetraethoxysilane (PTEOS) or boron-doped of tetraethoxysilane (BTEOS).

In one example, the wiring layer 203 is composed of multiple metal layers and metal vias connecting adjacent metal layers, the wiring layer 203 may be a copper interconnect structure, and the wiring layer 203 is connected to each CMOS transistor 201 . The wiring layer 203 can be formed by any method well known to those skilled in the art.

The front side of the top wafer 100 and the front side of the bottom wafer 200 are bonded. This bonding can be accomplished using any suitable bonding method, eg, oxide fusion bonding, and the like.

In one example, the semiconductor device in the embodiment of the present invention further includes openings from the back side of the top wafer 100, through the top wafer 100 outside the grid 106 and part of the bottom wafer 200, so The bottom of the opening is located on the surface of the bottom metal layer of the wiring layer 203 in the bottom wafer 200, and an intermetallic oxide 108 is formed on the backside of the top wafer 100 and the sidewall of the opening. Pads 109 are formed on the backside of a portion of the top wafer 100 and the intermetallic oxide layer 108 on the sidewalls and bottom of the opening.

The material of the intermetallic oxide 108 may include silicon oxide, silicon oxynitride, and the like. The intermetallic oxide 108 may be formed by chemical vapor deposition, physical vapor deposition, thermal oxidation, or the like.

Wherein, the material of the pad 109 may be any suitable metal material, such as gold, silver, aluminum, copper, etc. In this embodiment, the material of the pad 109 preferably includes aluminum.

To sum up, in the semiconductor device of the present invention, the SiGe grid is formed on the area corresponding to the pixel area on the backside of the top wafer, which can reduce the generation of various crosstalk problems, and the backside illuminated (BSI) image sensor of the present invention of higher performance.

Embodiment 3

The present invention further provides an electronic device, which includes the semiconductor device in the second embodiment, or includes the semiconductor device formed by the manufacturing method in the first embodiment.

The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, notebook computer, netbook, game console, TV, VCD, DVD, navigator, camera, video camera, voice recorder, MP3, MP4, PSP, etc. , and can also be any intermediate product including the aforementioned semiconductor device. Since the above-mentioned semiconductor device is used, the semiconductor device has excellent performance, so the electronic device of the embodiment of the present invention also has better performance.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (17)

1. A method of manufacturing a semiconductor device, comprising:

step S1: providing a top wafer, wherein a plurality of pixel units are formed in the top wafer;

step S2: providing a bottom wafer, and bonding the front surface of the top wafer and the front surface of the bottom wafer;

step S3: thinning the back of the top wafer;

forming an oxide layer on the back side of the top wafer after thinning the back side of the top wafer;

step S4: after the oxide layer is formed, depositing a semiconductor material layer on the back surface of the top wafer, and patterning the semiconductor material layer to form a plurality of grids;

step S5: and depositing to form a protective layer to cover the back side of the top wafer and each grid.

2. The method of claim 1, wherein each of the grids is formed by a square frame surrounded by four stripe structures, and each pixel unit of the top wafer corresponds to one of the grids.

3. The method of claim 1, wherein the oxide layer has a thickness in a range of 80 to 200 angstroms.

4. The manufacturing method according to claim 1, wherein in the step S4, the step of patterning the semiconductor material layer includes: and forming a patterned photoresist on the semiconductor material layer, and etching the semiconductor material layer to stop on the oxide layer by using the patterned photoresist as a mask so as to form the plurality of grids.

5. The method of claim 1, wherein the semiconductor material layer has a thickness in a range of 1500 to 2500 angstroms.

6. The method of manufacturing according to claim 1, wherein the material of the semiconductor material layer comprises SiGe.

7. The manufacturing method according to claim 1, wherein a material of the protective layer includes silicon nitride.

8. The method of manufacturing of claim 1, wherein the bottom wafer comprises a plurality of CMOS devices formed on the front side of the bottom wafer, an interlayer dielectric layer on the plurality of CMOS devices on the front side of the bottom wafer, and a wiring layer in the interlayer dielectric layer connected to each of the CMOS devices.

9. The manufacturing method according to claim 8, further comprising, after the step S5, the steps of:

etching the top wafer and part of the bottom wafer outside the grating from the back side of the top wafer until the bottom metal layer of the wiring layer in the bottom wafer is exposed to form an opening;

forming an intermetallic oxide on the back side of the top wafer and the sidewalls of the opening;

forming a pad material layer on the back side of the top wafer and the intermetallic oxide in the opening;

and etching the central area of the pad material layer in the opening, and reserving the pad material layer on the side wall and the bottom of the opening to form a pad.

10. A semiconductor device, comprising:

the manufacturing method comprises the following steps that a top wafer is formed with a plurality of pixel units, a plurality of grids are formed on the back surface of the top wafer, and a protective layer covers each grid and the back surface of the top wafer, wherein the grids are made of semiconductor materials; oxide layers are further formed on the back surface of the top wafer and below the grids and the protective layers on the side portions of the grids;

and the front surface of the top wafer is bonded with the front surface of the bottom wafer.

11. The semiconductor device according to claim 10, wherein the oxide layer has a thickness in a range of 80 to 200 angstroms.

12. The semiconductor device according to claim 10, wherein the height of the grating is in a range of 1500 to 2500 angstroms.

13. The semiconductor device of claim 10, wherein the semiconductor material comprises SiGe.

14. The semiconductor device of claim 10, wherein each of the grids is formed by a square frame surrounded by four stripe structures, and one of the grids corresponds to each pixel unit of the top wafer.

15. The semiconductor device of claim 10, wherein the bottom wafer comprises a plurality of CMOS devices formed on the front side of the bottom wafer, an interlayer dielectric layer on the plurality of CMOS devices on the front side of the bottom wafer, and a wiring layer in the interlayer dielectric layer respectively connected to each CMOS device.

16. The semiconductor device of claim 15, further comprising an opening through the top wafer and a portion of the bottom wafer outside the grid starting from the back side of the top wafer, a bottom of the opening being located on a surface of the bottom metal layer of the wiring layer in the bottom wafer, an intermetallic oxide being formed on the back side of the top wafer and on sidewalls of the opening, and a pad being formed on the intermetallic oxide layer on the back side of the portion of the top wafer and on the sidewalls and bottom of the opening.

17. An electronic device comprising the semiconductor device according to any one of claims 10 to 16.

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