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CN106601740B - Silicon-based InGaAs channel double-gate CMOS device - Google Patents

Silicon-based InGaAs channel double-gate CMOS device Download PDF

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CN106601740B
CN106601740B CN201611226809.1A CN201611226809A CN106601740B CN 106601740 B CN106601740 B CN 106601740B CN 201611226809 A CN201611226809 A CN 201611226809A CN 106601740 B CN106601740 B CN 106601740B
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CN106601740A (en
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常虎东
刘洪刚
夏庆贞
孙兵
王盛凯
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs

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Abstract

本发明提供一种硅基InGaAs沟道双栅COMS器件。本发明采用介质键合方法实现硅基半导体材料与InGaAs沟道双栅CMOS器件的集成，以提高CMOS器件的异构集成度，且双栅结构能够实现器件的低功耗工作，且器件的阈值电压调节更容易。

The invention provides a silicon-based InGaAs channel double-gate CMOS device. The invention adopts the dielectric bonding method to realize the integration of the silicon-based semiconductor material and the InGaAs channel double-gate CMOS device, so as to improve the heterogeneous integration degree of the CMOS device, and the double-gate structure can realize the low power consumption operation of the device, and the threshold value of the device is Voltage regulation is easier.

Description

Silicon substrate InGaAs channel dual-bar cmos device
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of silicon substrate InGaAs channel dual-bar CMOS devices.
Background technique
Integrated circuit is developed so far, it is already possible to integrate more than one hundred million a transistors on silicon, the power consumption of individual devices and Fuel factor has become the key element for restricting integrated circuit development.IntegratecCMOS devices have become on silicon-based semiconductor Current research hotspot and frontline technology.But two hang-ups that InGaAs cmos device faces at present are as follows: 1) InGaAs The Manufacturing resource of cmos device and silicon substrate；2) power problems of CMOS device after integrating.It needs to improve InGaAs CMOS thus The Manufacturing resource mode of device and silicon substrate, and realize the performance of the low-power consumption of device.
Summary of the invention
Silicon substrate InGaAs channel dual-bar CMOS device provided by the invention realizes that silicon substrate is partly led using medium bonding method Body material is integrated with InGaAs channel dual-bar cmos device, to improve the Manufacturing resource degree of cmos device, and double-gate structure energy Enough realize the low-power consumption work of device, and the threshold voltage adjustments of device are easier.
In a first aspect, the present invention provides a kind of silicon substrate InGaAs channel dual-bar CMOS device, including it is silicon substrate (1), described Bonding medium (2) and (3) on silicon substrate (1) and by InGaAs channel NMOS device (4), InGaAs channel PMOS device (5) and the InGaAs channel dual-bar cmos device that constitutes of interconnection metal (6), wherein the bonding medium (2) and (3) are for general The InGaAs channel dual-bar cmos device is bonded with the silicon substrate (1), and the interconnection metal (6) is described for connecting InGaAs channel NMOS device (4) and the InGaAs channel PMOS device (5)；
The InGaAs channel NMOS device (4) includes eigen I nGaAs channel layer (401), is located at eigen I nGaAs channel The top n-type doping InGaP boundary layer (402) of layer (401) two sides and bottom P type doping InGaP boundary layer (403) are located at institute State GaAs source and drain Ohmic contact cap layers (404), the position of the top n-type doping above top n-type doping InGaP boundary layer (402) The GaAs source and drain Ohmic contact cap layers of bottom p-type doping below bottom p-type doping InGaP boundary layer (403) (405), the Source and drain metal level (406) above the GaAs source and drain Ohmic contact cap layers (404) of the top n-type doping, position Top gate medium (407) above the top n-type doping InGaP boundary layer (402) is located on the top gate medium (407) Side top-gated metal (408), be located at the bottom p-type doping InGaP boundary layer (403) below bottom gate medium (407) and Bottom gate metal (410) below the bottom gate medium (409)；
The InGaAs channel PMOS device (5) includes eigen I nGaAs channel layer (501), is located at eigen I nGaAs channel The top n-type doping InGaP boundary layer (502) of layer (501) two sides and bottom P type doping InGaP boundary layer (503) are located at institute State GaAs source and drain Ohmic contact cap layers (504), the position of the top n-type doping above top n-type doping InGaP boundary layer (502) The GaAs source and drain Ohmic contact cap layers of bottom p-type doping below bottom p-type doping InGaP boundary layer (503) (505), the Source and drain metal level (506) below the GaAs source and drain Ohmic contact cap layers (505) of bottom p-type doping, position Top gate medium (507) above the top n-type doping InGaP boundary layer (502) is located on the top gate medium (507) The top-gated metal (508) of side, the bottom gate medium (509) being located at below bottom p-type doping InGaP boundary layer (503), position Bottom gate metal (510) below the bottom gate medium (509).
Silicon substrate InGaAs channel dual-bar CMOS device provided in an embodiment of the present invention realizes silicon using medium bonding method Base semiconductor material is integrated with InGaAs channel dual-bar cmos device, to improve the Manufacturing resource degree of CMOS device, and double grid Structure can be realized the low-power consumption work of device, and the threshold voltage adjustments of device are easier.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of one embodiment of the invention silicon substrate InGaAs channel dual-bar CMOS device.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The present invention provides a kind of silicon substrate InGaAs channel dual-bar CMOS device, as shown in Figure 1, the device includes Bonding medium 2 and 3 on silicon substrate 1, the silicon substrate 1 and by InGaAs channel NMOS device 4, InGaAs channel PMOS The InGaAs channel dual-bar cmos device that device 5 and interconnection metal 6 are constituted, wherein the bonding medium 2 and 3 is used for will be described InGaAs channel dual-bar CMOS device is bonded with the silicon substrate 1, and the interconnection metal 6 is for connecting the InGaAs Channel NMOS device 4 and the InGaAs channel PMOS device 5；
The InGaAs channel NMOS device 4 includes eigen I nGaAs channel layer 401, is located at eigen I nGaAs channel layer Top n-type doping InGaP boundary layer 402 and bottom p-type doping the InGaP boundary layer 403 of 401 two sides are located at the top N Type adulterates the GaAs source and drain Ohmic contact cap layers 404 of the top n-type doping of 402 top of InGaP boundary layer, is located at the bottom P Type adulterates the GaAs source and drain Ohmic contact cap layers 405 of the bottom p-type doping of 403 lower section of InGaP boundary layer, is located at the top N The Source and drain metal level 406 of 404 top of GaAs source and drain Ohmic contact cap layers of type doping is located at the top n-type doping InGaP The top gate medium 407 of 402 top of boundary layer, is located at the bottom P at the top-gated metal 408 above the top gate medium 407 Type adulterates the bottom gate medium 407 of 403 lower section of InGaP boundary layer and the bottom gate metal positioned at 409 lower section of bottom gate medium 410；
The InGaAs channel PMOS device 5 includes eigen I nGaAs channel layer 501, is located at eigen I nGaAs channel layer Top n-type doping InGaP boundary layer 502 and bottom p-type doping the InGaP boundary layer 503 of 501 two sides are located at the top N Type adulterates the GaAs source and drain Ohmic contact cap layers 504 of the top n-type doping of 502 top of InGaP boundary layer, is located at the bottom P Type adulterates the GaAs source and drain Ohmic contact cap layers 505 of the bottom p-type doping of 503 lower section of InGaP boundary layer, is located at the bottom P The Source and drain metal level 506 of 505 lower section of GaAs source and drain Ohmic contact cap layers of type doping is located at the top n-type doping InGaP The top gate medium 507 of 502 top of boundary layer, is located at the bottom P at the top-gated metal 508 above the top gate medium 507 Type adulterates the bottom gate medium 509 of 503 lower section of InGaP boundary layer, the bottom gate metal 510 positioned at 509 lower section of bottom gate medium.
Silicon substrate InGaAs channel dual-bar CMOS device provided in an embodiment of the present invention realizes silicon using medium bonding method Base semiconductor material is integrated with InGaAs channel dual-bar cmos device, to improve the Manufacturing resource degree of CMOS device, and double grid Structure can be realized the low-power consumption work of device, and the threshold voltage adjustments of device are easier.Specifically, with compound semiconductor As the double-gated devices structure of channel, so that the device has both high mobility characteristic and good grid voltage control characteristic, thus more The low-power consumption of device easy to accomplish works, and threshold voltage adjustments are easier.
Optionally, in the eigen I nGaAs channel layer 401 and the eigen I nGaAs channel layer 501 InGaAs In Group is divided into 0.25-0.4, and the eigen I nGaAs channel layer 401 and the eigen I nGaAs channel layer 501 are received with a thickness of 7 Rice.
Optionally, the top n-type doping InGaP boundary layer 402 and the top n-type doping InGaP boundary layer 502 The In group of middle InGaAs is divided into 0.5, the top n-type doping InGaP boundary layer 402 and the interface top n-type doping InGaP The doping concentration of layer 502 is 5 × 1017-1×1018cm-3, the top n-type doping InGaP boundary layer 402 and the top N-type Adulterate InGaP boundary layer 502 with a thickness of 2 nanometers.
Optionally, the bottom p-type doping InGaP boundary layer 403 and the bottom p-type adulterate InGaP boundary layer 503 The In group of middle InGaAs is divided into 0.4, and bottom p-type doping InGaP boundary layer (403) and the bottom p-type adulterate InGaP The doping concentration of boundary layer 503 is 8 × 1017-2×1018cm-3, bottom p-type doping InGaP boundary layer 403 and the bottom Portion's p-type adulterate InGaP boundary layer 503 with a thickness of 3 nanometers.
Optionally, the GaAs source and drain Ohmic contact cap layers 404 of the top n-type doping and the top N type adulterate GaAs source and drain Ohmic contact cap layers 504 with a thickness of 50 nanometers, the GaAs source and drain Ohmic contact cap layers of the top n-type doping 404 and the top n-type doping GaAs source and drain Ohmic contact cap layers 504 doping concentration be 5 × 1018cm-3。
Optionally, the GaAs source and drain Ohmic contact cap layers 405 and the bottom P type of the bottom p-type doping are adulterated GaAs source and drain Ohmic contact cap layers 505 with a thickness of 50 nanometers, the GaAs source and drain Ohmic contact cap layers of bottom p-type doping 405 and the bottom p-type doping GaAs source and drain Ohmic contact cap layers 505 doping concentration be 2 × 1019cm-3。
Optionally, which is characterized in that the Source and drain metal level 406 be with a thickness of 10 nanometers nickel, with a thickness of 20 nanometers Germanium or with a thickness of 100 nanometers of gold；The top gate medium 407 is the hafnium oxide with a thickness of 2.5 nanometers, the top-gated metal 408 be the tungsten with a thickness of 100 nanometers；The bottom gate medium 409 is the aluminium oxide with a thickness of 3 nanometers, and the bottom gate metal 410 is With a thickness of 100 nanometers of aluminium.
Optionally, which is characterized in that the Source and drain metal level 506 be with a thickness of 10 nanometers platinum, with a thickness of 30 nanometers Titanium or with a thickness of 100 nanometers of gold；The top gate medium 507 is the aluminium oxide with a thickness of 2.5 nanometers, the top-gated metal 508 be the aluminium with a thickness of 100 nanometers；The bottom gate medium 509 is the hafnium oxide with a thickness of 3 nanometers, and the bottom gate metal 510 is With a thickness of 100 nanometers of titanium-tungsten.
Optionally, the bonding medium (2) is SiO2, the bonding medium (3) is BCB or Al2O3.Optionally, described Interconnecting metal 4 is titanium or gold.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.

Claims (10)

1.一种硅基InGaAs沟道双栅CMOS 器件，其特征在于，包括硅衬底(1)、所述硅衬底(1)上的键合介质(2)和(3)以及由InGaAs沟道NMOS器件(4)、InGaAs沟道PMOS器件(5)和互连金属(6)构成的InGaAs沟道双栅CMOS器件，其中，所述键合介质(2)和(3)用于将所述InGaAs沟道双栅CMOS器件与所述硅衬底(1)进行键合，所述互连金属(6)用于连接所述InGaAs沟道NMOS器件(4)和所述InGaAs沟道PMOS器件(5)；1. A silicon-based InGaAs channel double-gate CMOS device, characterized in that it comprises a silicon substrate (1), bonding media (2) and (3) on the silicon substrate (1), and a channel formed by an InGaAs channel. An InGaAs channel double-gate CMOS device composed of a channel NMOS device (4), an InGaAs channel PMOS device (5) and an interconnection metal (6), wherein the bonding mediums (2) and (3) are used to connect the The InGaAs channel double-gate CMOS device is bonded to the silicon substrate (1), and the interconnect metal (6) is used to connect the InGaAs channel NMOS device (4) and the InGaAs channel PMOS device (5); 所述InGaAs沟道NMOS器件(4)包括本征InGaAs沟道层(401)、位于本征InGaAs沟道层(401)两侧的顶部N型掺杂InGaP界面层(402)和底部P型掺杂InGaP界面层(403)、位于所述顶部N型掺杂InGaP界面层(402)上方的顶部N型掺杂的GaAs源漏欧姆接触帽层(404)、位于所述底部P型掺杂InGaP界面层(403)下方的底部P型掺杂的GaAs源漏欧姆接触帽层(405)、位于所述顶部N型掺杂的GaAs源漏欧姆接触帽层(404)上方的源漏金属层(406)、位于所述顶部N型掺杂InGaP界面层(402)上方的顶栅介质(407)、位于所述顶栅介质(407)上方的顶栅金属(408)、位于所述底部P型掺杂InGaP界面层(403)下方的底栅介质(407)以及位于所述底栅介质(409)下方的底栅金属(410)；The InGaAs channel NMOS device (4) includes an intrinsic InGaAs channel layer (401), a top N-type doped InGaP interface layer (402) on both sides of the intrinsic InGaAs channel layer (401), and a bottom P-type doped interface layer (402) A doped InGaP interface layer (403), a top N-type doped GaAs source-drain ohmic contact cap layer (404) above the top N-type doped InGaP interface layer (402), a P-type doped InGaP on the bottom A bottom P-type doped GaAs source-drain ohmic contact cap layer (405) under the interface layer (403), a source-drain metal layer (404) above the top N-type doped GaAs source-drain ohmic contact cap layer (404) 406), a top gate dielectric (407) located above the top N-type doped InGaP interface layer (402), a top gate metal (408) located above the top gate dielectric (407), a top P-type dielectric located on the bottom Doping the bottom gate dielectric (407) under the InGaP interface layer (403) and the bottom gate metal (410) under the bottom gate dielectric (409); 所述InGaAs沟道PMOS器件(5)包括本征InGaAs沟道层(501)、位于本征InGaAs沟道层(501)两侧的顶部N型掺杂InGaP界面层(502)和底部P型掺杂InGaP界面层(503)、位于所述顶部N型掺杂InGaP界面层(502)上方的顶部N型掺杂的GaAs源漏欧姆接触帽层(504)、位于所述底部P型掺杂InGaP界面层(503)下方的底部P型掺杂的GaAs源漏欧姆接触帽层(505)、位于所述底部P型掺杂的GaAs源漏欧姆接触帽层(505)下方的源漏金属层(506)、位于所述顶部N型掺杂InGaP界面层(502)上方的顶栅介质(507)、位于所述顶栅介质(507)上方的顶栅金属(508)、位于所述底部P型掺杂InGaP界面层(503)下方的底栅介质(509)、位于所述底栅介质(509)下方的底栅金属(510)。The InGaAs channel PMOS device (5) includes an intrinsic InGaAs channel layer (501), a top N-type doped InGaP interface layer (502) on both sides of the intrinsic InGaAs channel layer (501), and a bottom P-type doped interface layer (502) A doped InGaP interface layer (503), a top N-type doped GaAs source-drain ohmic contact cap layer (504) above the top N-type doped InGaP interface layer (502), a P-type doped InGaP on the bottom A bottom P-type doped GaAs source-drain ohmic contact cap layer (505) under the interface layer (503), a source-drain metal layer (505) under the bottom P-type doped GaAs source-drain ohmic contact cap layer (505) 506), a top gate dielectric (507) located above the top N-type doped InGaP interface layer (502), a top gate metal (508) located above the top gate dielectric (507), a top P-type dielectric located on the bottom The bottom gate dielectric (509) under the InGaP interface layer (503) and the bottom gate metal (510) under the bottom gate dielectric (509) are doped. 2.根据权利要求1所述的器件，其特征在于，所述本征InGaAs沟道层(401)和所述本征InGaAs沟道层(501)中InGaAs的In组分为0.25-0.4，所述本征InGaAs沟道层(401)和所述本征InGaAs沟道层(501)的厚度为7纳米。2. The device according to claim 1, wherein the In composition of InGaAs in the intrinsic InGaAs channel layer (401) and the intrinsic InGaAs channel layer (501) is 0.25-0.4, so The thickness of the intrinsic InGaAs channel layer (401) and the intrinsic InGaAs channel layer (501) is 7 nanometers. 3.根据权利要求1所述的器件，其特征在于，所述顶部N型掺杂InGaP界面层(402)和所述顶部N型掺杂InGaP界面层(502)中InGaAs的In组分为0.5，所述顶部N型掺杂InGaP界面层(402)和所述顶部N型掺杂InGaP界面层(502)的掺杂浓度为5×1017-1×1018cm-3，所述顶部N型掺杂InGaP界面层(402)和所述顶部N型掺杂InGaP界面层(502)的厚度为2纳米。3. The device according to claim 1, wherein the In composition of InGaAs in the top N-type doped InGaP interface layer (402) and the top N-type doped InGaP interface layer (502) is 0.5 , the doping concentration of the top N-type doped InGaP interface layer (402) and the top N-type doped InGaP interface layer (502) is 5×10 17 -1×10 18 cm -3 , the top N The thickness of the N-type doped InGaP interface layer (402) and the top N-type doped InGaP interface layer (502) is 2 nanometers. 4.根据权利要求1所述的器件，其特征在于，所述底部P型掺杂InGaP界面层(403)和所述底部P型掺杂InGaP界面层(503)中InGaAs的In组分为0.4，所述底部P型掺杂InGaP界面层(403)和所述底部P型掺杂InGaP界面层(503)的掺杂浓度为8×1017-2×1018cm-3，所述底部P型掺杂InGaP界面层(403)和所述底部P型掺杂InGaP界面层(503)的厚度为3纳米。4. The device according to claim 1, wherein the In composition of InGaAs in the bottom P-type doped InGaP interface layer (403) and the bottom P-type doped InGaP interface layer (503) is 0.4 , the doping concentration of the bottom P-type doped InGaP interface layer (403) and the bottom P-type doped InGaP interface layer (503) is 8×10 17 -2×10 18 cm -3 , the bottom P The thickness of the P-type doped InGaP interface layer (403) and the bottom P-type doped InGaP interface layer (503) is 3 nanometers. 5.根据权利要求1所述的器件，其特征在于，所述顶部N型掺杂的GaAs源漏欧姆接触帽层(404)和所述顶部N型掺杂的GaAs源漏欧姆接触帽层(504)的厚度为50纳米，所述顶部N型掺杂的GaAs源漏欧姆接触帽层(404)和所述顶部N型掺杂的GaAs源漏欧姆接触帽层(504)的掺杂浓度为5×1018cm-3。5. The device according to claim 1, wherein the top N-type doped GaAs source-drain ohmic contact cap layer (404) and the top N-type doped GaAs source-drain ohmic contact cap layer (404) 504) has a thickness of 50 nanometers, and the top N-type doped GaAs source-drain ohmic contact cap layer (404) and the top N-type doped GaAs source-drain ohmic contact cap layer (504) have a doping concentration of 5×10 18 cm -3 . 6.根据权利要求1所述的器件，其特征在于，所述底部P型掺杂的GaAs源漏欧姆接触帽层(405)和所述底部P型掺杂的GaAs源漏欧姆接触帽层(505)的厚度为50纳米，所述底部P型掺杂的GaAs源漏欧姆接触帽层(405)和所述底部P型掺杂的GaAs源漏欧姆接触帽层(505)的掺杂浓度为2×1019cm-3。6. The device according to claim 1, wherein the bottom P-type doped GaAs source-drain ohmic contact cap layer (405) and the bottom P-type doped GaAs source-drain ohmic contact cap layer (405) 505) has a thickness of 50 nanometers, and the doping concentration of the bottom P-type doped GaAs source-drain ohmic contact cap layer (405) and the bottom P-type doped GaAs source-drain ohmic contact cap layer (505) is 2×10 19 cm -3 . 7.根据权利要求1所述的器件，其特征在于，所述源漏金属层(406)为厚度为10纳米的镍、厚度为20纳米的锗或者厚度为100纳米的金；所述顶栅介质(407)为厚度为2.5纳米的氧化铪，所述顶栅金属(408)为厚度为100纳米的钨；所述底栅介质(409)为厚度为3纳米的氧化铝，所述底栅金属(410)为厚度为100纳米的铝。7. The device according to claim 1, wherein the source-drain metal layer (406) is nickel with a thickness of 10 nanometers, germanium with a thickness of 20 nanometers, or gold with a thickness of 100 nanometers; the top gate The dielectric (407) is hafnium oxide with a thickness of 2.5 nanometers, the top gate metal (408) is tungsten with a thickness of 100 nanometers; the bottom gate dielectric (409) is aluminum oxide with a thickness of 3 nanometers, and the bottom gate The metal (410) is aluminum with a thickness of 100 nanometers. 8.根据权利要求1所述的器件，其特征在于，所述源漏金属层(506)为厚度为10纳米的铂、厚度为30纳米的钛或者厚度为100纳米的金；所述顶栅介质(507)为厚度为2.5纳米的氧化铝，所述顶栅金属(508)为厚度为100纳米的铝；所述底栅介质(509)为厚度为3纳米的氧化铪，所述底栅金属(510)为厚度为100纳米的钛钨合金。8. The device according to claim 1, wherein the source-drain metal layer (506) is platinum with a thickness of 10 nanometers, titanium with a thickness of 30 nanometers, or gold with a thickness of 100 nanometers; the top gate The dielectric (507) is aluminum oxide with a thickness of 2.5 nanometers, the top gate metal (508) is aluminum with a thickness of 100 nanometers; the bottom gate dielectric (509) is hafnium oxide with a thickness of 3 nanometers, and the bottom gate The metal (510) is a titanium-tungsten alloy with a thickness of 100 nanometers. 9.根据权利要求1所述的器件，其特征在于，所述键合介质(2)为SiO2，所述键合介质(3)为苯并环丁烯BCB或者Al2O3。9 . The device according to claim 1 , wherein the bonding medium ( 2 ) is SiO 2 , and the bonding medium ( 3 ) is benzocyclobutene BCB or Al 2 O 3 . 10 . 10.根据权利要求1所述的器件，其特征在于，所述互连金属(6)为钛或者金。10. The device according to claim 1, wherein the interconnection metal (6) is titanium or gold.
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