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CN106601620B - A kind of semiconductor device and its preparation method, electronic device - Google Patents

A kind of semiconductor device and its preparation method, electronic device Download PDF

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CN106601620B
CN106601620B CN201510674345.XA CN201510674345A CN106601620B CN 106601620 B CN106601620 B CN 106601620B CN 201510674345 A CN201510674345 A CN 201510674345A CN 106601620 B CN106601620 B CN 106601620B
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semiconductor substrate
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CN106601620A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0241Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] doping of vertical sidewalls, e.g. using tilted or multi-angled implants
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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Abstract

本发明涉及一种半导体器件及其制备方法、电子装置。所述方法包括步骤S1:提供半导体衬底,所述半导体衬底包括核心区和输入输出区,其中,在所述核心区和所述输入输出区上均形成有若干鳍片;步骤S2:在所述输入输出区上的所述半导体衬底上以及所述鳍片底部的侧壁上形成衬垫层;步骤S3:在所述核心区的半导体衬底上、所述鳍片的表面上以及所述输入输出区中的所述衬垫层上和所述鳍片顶部的表面上依次形成含硼材料层和覆盖层;步骤S4:在所述覆盖层上形成隔离材料层至所述衬垫层顶部或以上,以部分覆盖所述鳍片;步骤S5:去除露出的所述鳍片上的所述含硼材料层和所述覆盖层;步骤S6:执行退火步骤,以使所述含硼材料中的硼扩散至沟道停止区域中。

The invention relates to a semiconductor device, a preparation method thereof, and an electronic device. The method includes step S1: providing a semiconductor substrate, the semiconductor substrate includes a core area and an input-output area, wherein several fins are formed on both the core area and the input-output area; step S2: in Forming a pad layer on the semiconductor substrate on the input-output area and on the sidewall of the bottom of the fin; Step S3: on the semiconductor substrate in the core area, on the surface of the fin and A boron-containing material layer and a cover layer are sequentially formed on the liner layer in the input-output area and on the surface of the top of the fin; step S4: forming an isolation material layer on the cover layer to the liner layer on or above the top of the fin to partially cover the fin; step S5: remove the boron-containing material layer and the cover layer on the exposed fin; step S6: perform an annealing step to make the boron-containing material The boron in the channel diffuses into the channel stop region.

Description

一种半导体器件及其制备方法、电子装置A kind of semiconductor device and its preparation method, electronic device

技术领域technical field

本发明涉及半导体领域,具体地,本发明涉及一种半导体器件及其制备方法、电子装置。The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device.

背景技术Background technique

集成电路性能的提高主要是通过不断缩小集成电路器件的尺寸以提高它的速度来实现的。目前,由于半导体工业已经进步到纳米技术工艺节点,特别是当半导体器件尺寸降到22nm或以下时,来自制造和设计方面的挑战已经促进了三维设计如鳍片场效应晶体管(FinFET)的发展。The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes, especially as semiconductor device dimensions drop to 22nm or below, manufacturing and design challenges have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs).

相对于现有的平面晶体管,所述FinFET器件在沟道控制以及降低浅沟道效应等方面具有更加优越的性能;平面栅极结构设置于所述沟道上方,而在FinFET中所述栅极环绕所述鳍片设置,因此能从三个面来控制静电,在静电控制方面的性能也更突出。Compared with the existing planar transistors, the FinFET device has more superior performance in terms of channel control and reducing shallow channel effects; the planar gate structure is arranged above the channel, and the gate in the FinFET The fins are arranged around the fins, so static electricity can be controlled from three sides, and the performance in static electricity control is also more outstanding.

其中,在FinFET器件中需要进行沟道停止离子注入,以控制鳍片底部的的源漏由于部分耗尽造成的穿通,此外,沟道停止离子注入过程中造成的损坏的控制成为主要的问题,其中,穿通离子注入掺杂(punch through imp doping)将扩散至FINFET器件的沟道,其将降低由随机掺杂涨落(Random Doping Fluctuation,RDF)引起的失配性能。Among them, channel-stop ion implantation is required in FinFET devices to control the punch-through caused by partial depletion of the source and drain at the bottom of the fin. In addition, the control of damage caused during the channel-stop ion implantation process has become a major issue. Wherein, the punch through imp doping will diffuse into the channel of the FINFET device, which will reduce the mismatch performance caused by random doping fluctuation (Random Doping Fluctuation, RDF).

其中NMOS穿通比PMOS要严重,这主要是由于NMOS穿通是用B或BF2,而PMOS是用AS;B离子是比较容易损失(LOSS)的。Among them, NMOS punch-through is more serious than PMOS, mainly because NMOS punch-through uses B or BF 2 , while PMOS uses AS; B ions are relatively easy to lose (LOSS).

固体源漏掺杂的方法可以用于掺杂沟道底部,通过所述方法向上扩散至沟道和离子注入损坏均可以得到很好的控制,但是在所述方法中存在其他的问题,其中,FinFET器件通常包括核心区和输入输出区,核心区需要更多的沟道停止离子注入以减小由于短沟道效应引起的源漏穿通,但是核心区的沟道停止离子注入对于输入输出区来说则离子注入太多。Solid source-drain doping methods can be used to dope the bottom of the channel, by which both up-diffusion into the channel and ion implantation damage can be well controlled, but there are other problems with this method, among them, FinFET devices usually include a core area and an input and output area. The core area needs more channel stop ion implantation to reduce the source-drain penetration caused by the short channel effect, but the channel stop ion implantation in the core area is more important for the input and output area. In other words, too much ion implantation.

因此需要对目前所述半导体器件的制备方法进行改进,以消除所述问题,提供半导体器件的性能和良率。Therefore, it is necessary to improve the current manufacturing method of the semiconductor device, so as to eliminate the problem and improve the performance and yield of the semiconductor device.

发明内容Contents of the invention

在发明内容部分中引入了一系列简化形式的概念,这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征,更不意味着试图确定所要求保护的技术方案的保护范围。A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

本发明为了克服目前存在问题,提供了一种半导体器件的制备方法,包括:In order to overcome the current existing problems, the present invention provides a method for preparing a semiconductor device, including:

步骤S1:提供半导体衬底,所述半导体衬底包括核心区和输入输出区,其中,在所述核心区和所述输入输出区上均形成有若干鳍片;Step S1: providing a semiconductor substrate, the semiconductor substrate includes a core area and an input-output area, wherein several fins are formed on both the core area and the input-output area;

步骤S2:在所述输入输出区上的所述半导体衬底上以及所述鳍片底部的侧壁上形成衬垫层;Step S2: forming a pad layer on the semiconductor substrate on the input-output region and on the sidewalls of the bottom of the fin;

步骤S3:在所述核心区的所述半导体衬底上、所述鳍片的表面上以及所述输入输出区中的所述衬垫层上和所述鳍片顶部的表面上依次形成含硼材料层和覆盖层;Step S3: sequentially forming a boron-containing substrate on the semiconductor substrate in the core area, on the surface of the fin, on the liner layer in the input-output area, and on the surface of the top of the fin. material layers and covering layers;

步骤S4:在所述覆盖层上形成隔离材料层至所述衬垫层顶部或以上,以部分覆盖所述鳍片,形成目标高度的鳍片;Step S4: forming an isolation material layer on the cover layer to the top of the liner layer or above to partially cover the fins to form fins with a target height;

步骤S5:去除露出的所述鳍片上的所述含硼材料层和所述覆盖层,以露出所述鳍片;Step S5: removing the boron-containing material layer and the covering layer on the exposed fins to expose the fins;

步骤S6:执行退火步骤,以使所述含硼材料中的硼扩散至沟道停止区域中。Step S6: performing an annealing step to diffuse boron in the boron-containing material into the channel stop region.

可选地,所述步骤S2包括:Optionally, the step S2 includes:

步骤S21:在所述核心区和所述输入输出区的所述半导体衬底上和所述鳍片上形成所述衬垫层,以覆盖所述半导体衬底上和所述鳍片;Step S21: forming the liner layer on the semiconductor substrate and the fins in the core area and the input-output area, so as to cover the semiconductor substrate and the fins;

步骤S22:在所述输入输出区的所述衬垫层上形成第一保护层,以覆盖所述衬垫层;Step S22: forming a first protective layer on the liner layer of the input-output area to cover the liner layer;

步骤S23:去除所述核心区中的所述衬垫层,以露出所述半导体衬底和所述鳍片;Step S23: removing the pad layer in the core area to expose the semiconductor substrate and the fins;

步骤S24:在所述核心区中露出所述半导体衬底上和所述鳍片上形成具有第一高度的第二保护层,以完全覆盖所述核心区中的所述半导体衬底和所述鳍片,同时在所述输入输出区中形成具有第二高度的第二保护层,以部分覆盖所述鳍片表面的所述衬垫层,形成所述目标高度的鳍片;Step S24: forming a second protective layer having a first height on the exposed semiconductor substrate and the fins in the core area, so as to completely cover the semiconductor substrate and the fins in the core area sheet, and at the same time form a second protective layer having a second height in the input-output region to partially cover the liner layer on the surface of the fin to form a fin of the target height;

步骤S25:去除所述输入输出区中露出的所述衬垫层,以在所述鳍片底部的侧壁上形成所述衬垫层。Step S25 : removing the liner layer exposed in the input-output area, so as to form the liner layer on the sidewall of the bottom of the fin.

可选地,所述步骤S24包括:Optionally, the step S24 includes:

步骤S241:在所述核心区的所述鳍片上和所述输入输出区的所述衬垫层上形成具有所述第一高度的所述第二保护层,以完全覆盖所述鳍片和所述衬垫层;Step S241: forming the second protection layer with the first height on the fins in the core area and the liner layer in the input-output area, so as to completely cover the fins and the pad layer. the cushion layer;

步骤S242:在所述核心区的第二保护层上形成掩膜层;Step S242: forming a mask layer on the second protection layer of the core region;

步骤S243:以所述掩膜层为掩膜蚀刻所述输入输出区中的所述第二保护层至第二高度,以露出所述输入输出区中所述鳍片顶部的所述衬垫层。Step S243: using the mask layer as a mask to etch the second protection layer in the input-output area to a second height, so as to expose the pad layer on the top of the fin in the input-output area .

可选地,所述含硼材料层选用含硼玻璃层。Optionally, the boron-containing material layer is a boron-containing glass layer.

可选地,所述步骤S4包括:Optionally, the step S4 includes:

步骤S41:沉积所述隔离材料层,以覆盖所述鳍片;Step S41: depositing the isolation material layer to cover the fins;

步骤S42:回蚀刻所述隔离材料层,以露出部分所述鳍片,形成目标高度的所述鳍片。Step S42: Etching back the isolation material layer to expose part of the fins to form the fins at a target height.

可选地,所述步骤S1包括:Optionally, the step S1 includes:

步骤S11:提供所述半导体衬底,在所述半导体衬底上形成有图案化的掩膜层;Step S11: providing the semiconductor substrate on which a patterned mask layer is formed;

步骤S12:以所述掩膜层为掩膜蚀刻所述半导体衬底,以形成所述鳍片。Step S12: Etching the semiconductor substrate using the mask layer as a mask to form the fins.

可选地,在所述步骤S6之后还进一步包括去除所述鳍片上的所述掩膜层的步骤。Optionally, after the step S6, a step of removing the mask layer on the fin is further included.

可选地,所述覆盖层选用氮化物层。Optionally, the covering layer is a nitride layer.

本发明还提供了一种基于上述的方法制备得到的半导体器件。The present invention also provides a semiconductor device prepared based on the above method.

本发明还提供了一种电子装置,包括上述的半导体器件。The present invention also provides an electronic device, including the above-mentioned semiconductor device.

本发明为了解决现有技术中存在的问题,提供了一种半导体器件的制备方法,在所述方法中为了降低所述输入输出区中沟道离子注入量,在所述输入输出区的鳍片底部(有效鳍片以下)的侧壁上形成衬垫层,然后在所述核心区和所述输入输出区中鳍片侧壁上形成含硼材料层和覆盖层,沉积隔离材料并回蚀刻至目标高度的鳍片,去除露出的所述硼材料层和覆盖层,最后执行退火步骤,在所述目标高度以下的鳍片底部进行硼离子扩散,使以使所述含硼材料中的硼扩散至沟道停止区域中,在所述输入输出区中所述衬垫层作为硼离子扩散到阻挡层,可以阻挡硼离子的扩散,从而避免了输入输出区中沟道停止离子注入过量,同时还能使核心区进行更多的沟道停止离子注入以减小由于短沟道效应引起的源漏穿通。In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device. In the method, in order to reduce the amount of channel ion implantation in the input-output region, the fins in the input-output region Form a liner layer on the sidewall of the bottom (below the effective fin), then form a boron-containing material layer and a cover layer on the sidewall of the fin in the core area and the input-output area, deposit an isolation material and etch back to Fins at a target height, removing the exposed boron material layer and covering layer, and finally performing an annealing step, performing boron ion diffusion at the bottom of the fin below the target height, so that boron in the boron-containing material can be diffused In the channel stop region, the liner layer in the input and output region diffuses to the barrier layer as boron ions, which can block the diffusion of boron ions, thereby avoiding excessive implantation of channel stop ions in the input and output region, and at the same time More channel-stop ion implantation can be performed in the core region to reduce the source-drain breakthrough caused by the short-channel effect.

附图说明Description of drawings

本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述,用来解释本发明的装置及原理。在附图中,The following drawings of the invention are hereby included as part of the invention for understanding the invention. Embodiments of the present invention and their descriptions are shown in the drawings to explain the device and principle of the present invention. In the attached picture,

图1为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 1 is a schematic diagram of the preparation process of the semiconductor device described in a specific implementation of the present invention;

图2为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 2 is a schematic diagram of the preparation process of the semiconductor device described in a specific implementation of the present invention;

图3为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 3 is a schematic diagram of the preparation process of the semiconductor device described in a specific implementation of the present invention;

图4为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 4 is a schematic diagram of the preparation process of the semiconductor device described in a specific implementation of the present invention;

图5为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 5 is a schematic diagram of the preparation process of the semiconductor device described in a specific implementation of the present invention;

图6为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 6 is a schematic diagram of the preparation process of the semiconductor device described in a specific implementation of the present invention;

图7为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 7 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图8为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 8 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图9为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 9 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图10为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 10 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图11为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 11 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图12为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 12 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图13为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 13 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图14为本发明一具体地实施中所述半导体器件的制备过程示意图;Fig. 14 is a schematic diagram of the manufacturing process of the semiconductor device described in a specific implementation of the present invention;

图15为本发明一具体地实施中所述半导体器件的制备的工艺流程图。Fig. 15 is a flow chart of the process of manufacturing the semiconductor device described in a specific implementation of the present invention.

具体实施方式Detailed ways

在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。然而,对于本领域技术人员而言显而易见的是,本发明可以无需一个或多个这些细节而得以实施。在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

应当理解的是,本发明能够以不同形式实施,而不应当解释为局限于这里提出的实施例。相反地,提供这些实施例将使公开彻底和完全,并且将本发明的范围完全地传递给本领域技术人员。在附图中,为了清楚,层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

应当明白,当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本发明教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等,在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语意图还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,然后,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

为了彻底理解本发明,将在下列的描述中提出详细的步骤以及详细的结构,以便阐释本发明的技术方案。本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。In order to thoroughly understand the present invention, detailed steps and detailed structures will be provided in the following description, so as to illustrate the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

实施例一Embodiment one

本发明为了解决现有技术中存在的问题,提供了一种新的半导体器件的制备方法,下面结合附图对本发明所述方法作进一步的说明。In order to solve the problems in the prior art, the present invention provides a new method for manufacturing a semiconductor device. The method of the present invention will be further described below in conjunction with the accompanying drawings.

其中,图1-13为本发明一具体地实施中所述半导体器件的制备过程示意图。1-13 are schematic diagrams of the manufacturing process of the semiconductor device described in a specific implementation of the present invention.

首先,执行步骤101,提供半导体衬底101。First, step 101 is performed to provide a semiconductor substrate 101 .

具体地,如图1所示,在该步骤中所述半导体衬底可以是以下所提到的材料中的至少一种:硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。Specifically, as shown in FIG. 1, the semiconductor substrate in this step may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator Silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc.

在该实施例中半导体衬底101选用硅。In this embodiment, silicon is selected as the semiconductor substrate 101 .

其中所述半导体衬底包括核心区和输入输出区,以在后续的步骤中形成不同的元件。Wherein the semiconductor substrate includes a core area and an input and output area, so as to form different elements in subsequent steps.

接着在所述半导体衬底上形成垫氧化物层(Pad oxide),其中所述垫氧化物层(Pad oxide)的形成方法可以通过沉积的方法形成,例如化学气相沉积、原子层沉积等方法,还可以通过热氧化所述半导体衬底的表面形成,在此不再赘述。Next, a pad oxide layer (Pad oxide) is formed on the semiconductor substrate, wherein the formation method of the pad oxide layer (Pad oxide) can be formed by a deposition method, such as chemical vapor deposition, atomic layer deposition and other methods, It can also be formed by thermally oxidizing the surface of the semiconductor substrate, which will not be repeated here.

进一步,在该步骤中还可以进一步包含执行离子注入的步骤,以在所述半导体衬底中形成阱,其中注入的离子种类以及注入方法可以为本领域中常用的方法,在此不一一赘述。Further, this step may further include the step of performing ion implantation to form a well in the semiconductor substrate, wherein the implanted ion species and the implantation method may be methods commonly used in the art, and will not be described here one by one. .

接着执行步骤102,在半导体衬底上形成多个鳍片102。Next, step 102 is performed to form a plurality of fins 102 on the semiconductor substrate.

具体地,鳍片的宽度全部相同,或者鳍片分为具有不同宽度的多个鳍片组。Specifically, the widths of the fins are all the same, or the fins are divided into a plurality of fin groups with different widths.

可选地,如图1所示,所述鳍片的形成方法并不局限于某一种,下面给出一种示例性的形成方法:在半导体衬底上形成硬掩膜层(图中未示出),形成所述硬掩膜层可以采用本领域技术人员所熟习的各种适宜的工艺,例如化学气相沉积工艺,所述硬掩膜层可以为自下而上层叠的氧化物层和氮化硅层;图案化所述硬掩膜层,形成用于蚀刻半导体衬底以在其上形成鳍片的多个彼此隔离的掩膜,在一个实施例中,采用自对准双图案(SADP)工艺实施所述图案化过程;蚀刻半导体衬底以在其上形成鳍片结构。Optionally, as shown in FIG. 1, the forming method of the fins is not limited to a certain one, and an exemplary forming method is given below: forming a hard mask layer (not shown in the figure) on a semiconductor substrate shown), the hard mask layer can be formed using various suitable processes familiar to those skilled in the art, such as a chemical vapor deposition process, and the hard mask layer can be an oxide layer stacked from bottom to top and a silicon nitride layer; patterning the hard mask layer to form a plurality of isolated masks for etching the semiconductor substrate to form fins thereon, in one embodiment, using self-aligned double patterning ( SADP) process implements the patterning process; the semiconductor substrate is etched to form fin structures thereon.

接着执行步骤103,在所述输入输出区上的所述半导体衬底表面以及所述鳍片底部的侧壁上形成衬垫层103。Next, step 103 is performed, forming a pad layer 103 on the surface of the semiconductor substrate on the input-output region and on the sidewall of the bottom of the fin.

具体地,其中,所述衬垫层103可以选用氧化物层等,并不局限于某一种。Specifically, the pad layer 103 may be an oxide layer or the like, and is not limited to a certain one.

在所述输入输出区上的所述半导体衬底表面以及所述鳍片底部的侧壁上形成衬垫层103的方法可以包括以下步骤:The method for forming the pad layer 103 on the surface of the semiconductor substrate on the input-output region and the sidewall of the bottom of the fin may include the following steps:

步骤1031:如图2所示,在所述核心区和所述输入输出区的所述半导体衬底上和所述鳍片(102)上形成所述衬垫层(103),以覆盖所述半导体衬底上和所述鳍片(102);Step 1031: As shown in Figure 2, form the pad layer (103) on the semiconductor substrate and the fins (102) in the core area and the input-output area to cover the on the semiconductor substrate and said fins (102);

在该步骤中所述衬垫层103的形成方法可以通过加热氧化的方法,例如可以通过原位水蒸气氧化(ISSG)等方法,但是并不局限于所述示例,还可以选用本领域中常用的其他方法In this step, the formation method of the liner layer 103 can be through thermal oxidation, for example, through in-situ steam oxidation (ISSG) and other methods, but it is not limited to the above examples, and can also be used commonly used in this field. other methods of

其中,所述垫氧化物层103的厚度并不局限于某一数值范围,可以选用常规的厚度。Wherein, the thickness of the pad oxide layer 103 is not limited to a certain value range, and a conventional thickness can be selected.

步骤1032:在所述输入输出区的所述衬垫层103上形成第一保护层,以覆盖所述衬垫层103,如图3所示;Step 1032: forming a first protective layer on the liner layer 103 of the input-output area to cover the liner layer 103, as shown in FIG. 3 ;

步骤1033:去除所述核心区中的所述衬垫层103,以露出所述半导体衬底上和所述鳍片102,如图3所示;Step 1033: removing the pad layer 103 in the core area to expose the semiconductor substrate and the fins 102, as shown in FIG. 3 ;

步骤1034:在所述核心区中露出所述半导体衬底上和所述鳍片102上形成具有第一高度的第二保护层,以完全覆盖所述核心区中的所述半导体衬底和所述鳍片102,同时在所述输入输出区中形成具有第二高度的第二保护层,以部分覆盖所述鳍片表面的所述衬垫层103,露出部分鳍片以形成所述目标高度的鳍片,如图6所示;Step 1034: forming a second protection layer with a first height on the semiconductor substrate exposed in the core area and on the fins 102, so as to completely cover the semiconductor substrate and the semiconductor substrate in the core area. The fins 102, while forming a second protection layer with a second height in the input and output area to partially cover the liner layer 103 on the surface of the fins, exposing part of the fins to form the target height The fins, as shown in Figure 6;

步骤1035:去除所述输入输出区中露出的所述衬垫层103,以露出所述目标高度的鳍片同时所述鳍片底部的侧壁上形成所述衬垫层103,如图7所示。Step 1035: remove the liner layer 103 exposed in the input and output area, so as to expose the fins of the target height and form the liner layer 103 on the sidewall of the bottom of the fin, as shown in FIG. 7 Show.

进一步,所述步骤1034还可以包括:Further, the step 1034 may also include:

步骤10341:在所述核心区的所述鳍片上和所述输入输出区的所述衬垫层上形成具有所述第一高度的所述第二保护层,以完全覆盖所述鳍片和所述衬垫层,如图5所示;Step 10341: Form the second protective layer with the first height on the fins in the core area and the liner layer in the input-output area to completely cover the fins and the pad layer. Described backing layer, as shown in Figure 5;

步骤10342:在所述核心区的第二保护层上形成掩膜层,如图5所示;Step 10342: forming a mask layer on the second protective layer in the core area, as shown in FIG. 5 ;

步骤10343:以所述掩膜层为掩膜蚀刻所述输入输出区中的所述第二保护层至第二高度,以露出目标高度的所述鳍片,露出所述输入输出区中所述鳍片顶部的所述衬垫层,如图6所示。Step 10343: Using the mask layer as a mask, etch the second protection layer in the input-output area to a second height to expose the fins at a target height, exposing the The liner layer on top of the fins is shown in Figure 6.

最后去除所述掩膜层和所述第二保护层,如图8所示。Finally, the mask layer and the second protective layer are removed, as shown in FIG. 8 .

在本发明中在该步骤中仅在所述输入输出区中所述目标鳍片底部的侧壁上形成所述衬垫层,在后续的执行退火步骤使所述含硼材料中的硼扩散至沟道停止区域的过程中,所述输入输出区中所述衬垫层作为硼离子扩散到阻挡层,可以阻挡硼离子的扩散,从而避免了输入输出区中沟道停止离子注入过量,同时还能使核心区进行更多的沟道停止离子注入以减小由于短沟道效应引起的源漏穿通。In the present invention, in this step, the liner layer is only formed on the sidewall of the bottom of the target fin in the input-output region, and the boron in the boron-containing material is diffused to the In the process of the channel stop region, the liner layer in the input and output region diffuses to the barrier layer as boron ions, which can block the diffusion of boron ions, thereby avoiding excessive implantation of channel stop ions in the input and output region, and at the same time More channel-stop ion implantation can be performed in the core region to reduce the source-drain breakthrough caused by the short-channel effect.

接着执行步骤104,在所述核心区的所述半导体衬底上、所述鳍片的表面上以及所述输入输出区中的所述衬垫层上和所述鳍片表面上依次形成含硼材料层104和覆盖层105。Next, step 104 is performed to sequentially form boron-containing material layer 104 and cover layer 105 .

具体地,如图9-10所示,在该步骤中所述含硼材料层104用于在后续的步骤中执行固体源漏掺杂沟道停止离子注入工艺,即通过退火步骤使所述含硼材料层104中的B扩散,以形成沟道停止离子注入区域。Specifically, as shown in FIGS. 9-10 , in this step, the boron-containing material layer 104 is used to perform a solid source-drain doped channel stop ion implantation process in subsequent steps, that is, the annealing step makes the boron-containing material layer 104 B in the boron material layer 104 is diffused to form a channel stop ion implantation region.

可选地,所述含硼材料层104可以选用含硼玻璃层,例如硼磷玻璃(BSG),但并不局限于所述示例。Optionally, the boron-containing material layer 104 may be a boron-containing glass layer, such as boron phosphorous glass (BSG), but is not limited to the above examples.

其中,所述覆盖层105可以选用本领域中常用的材料,例如各种氮化物,以防止在后续实施的工艺对鳍片结构的高度和特征尺寸造成损失。在一个实施例中,采用具有可流动性的化学气相沉积工艺(FCVD)形成覆盖层。Wherein, the cover layer 105 can be selected from commonly used materials in the field, such as various nitrides, so as to prevent loss of the height and feature size of the fin structure in subsequent processes. In one embodiment, the capping layer is formed by a flowable chemical vapor deposition process (FCVD).

在一具体实施方式中,所述覆盖层的材料可以为氮化硅。In a specific implementation manner, the material of the covering layer may be silicon nitride.

接着执行步骤105,在所述覆盖层105上形成隔离材料层106至所述衬垫层或以上,以部分覆盖所述鳍片,形成目标高度的鳍片。Next, step 105 is performed to form an isolation material layer 106 on the cover layer 105 to the liner layer or above to partially cover the fins to form fins with a target height.

具体地,在所述覆盖层105上形成隔离材料层106至所述衬垫层或以上,以部分覆盖所述鳍片,形成目标高度的鳍片的方法可以包括以下步骤:Specifically, forming an isolation material layer 106 on the cover layer 105 to the liner layer or above to partially cover the fins, the method for forming fins with a target height may include the following steps:

首先,沉积隔离材料层106,以覆盖所述鳍片结构并回蚀刻所述隔离材料层106,以露出部分所述鳍片至目标高度。First, an isolation material layer 106 is deposited to cover the fin structure, and the isolation material layer 106 is etched back to expose part of the fins to a target height.

具体地,如图11所示,沉积隔离材料层106,以完全填充鳍片结构之间的间隙。在一个实施例中,采用具有可流动性的化学气相沉积工艺实施所述沉积。Specifically, as shown in FIG. 11 , a layer of isolation material 106 is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process.

其中,隔离材料层的材料可以选择氧化物,但是并不局限于所述示例,在该实施例中选用HARP。Wherein, the material of the isolation material layer may be oxide, but is not limited to the above example, and HARP is selected in this embodiment.

然后回蚀刻所述隔离材料层,至所述鳍片的目标高度,如图12所示。具体地,回蚀刻所述隔离材料层,以露出部分所述鳍片,进而形成具有特定高度的鳍片。The isolation material layer is then etched back to the target height of the fins, as shown in FIG. 12 . Specifically, the isolation material layer is etched back to expose part of the fins, thereby forming fins with a specific height.

其中,所述隔离材料层的沉积方法可以选用干法蚀刻或者湿法蚀刻,并不局限于某一种。Wherein, the deposition method of the isolation material layer may be dry etching or wet etching, and is not limited to a certain one.

接着执行步骤106,去除露出的所述鳍片上的所述含硼材料层104和所述覆盖层105,以露出目标高度的所述鳍片。Next, step 106 is performed, removing the boron-containing material layer 104 and the covering layer 105 on the exposed fins, so as to expose the fins at a target height.

具体地,如图13所示,在该步骤中去除露出的所述含硼材料层104和所述覆盖层105,而保留所述鳍片底部被所述隔离材料层覆盖的所述含硼材料层104和所述覆盖层105。Specifically, as shown in FIG. 13 , in this step, the exposed boron-containing material layer 104 and the covering layer 105 are removed, while the boron-containing material at the bottom of the fin covered by the isolation material layer remains. layer 104 and the cover layer 105 .

在该步骤中可以选用干法蚀刻或者湿法蚀刻,选用和所述鳍片具有较大蚀刻选择比的方法去除所述第一衬里层和所述第二衬里层,以防止对所述鳍片造成损害。In this step, dry etching or wet etching can be selected, and the first liner layer and the second liner layer can be removed by using a method with a larger etching selectivity with the fins to prevent damage to the fins. cause damage.

接着执行步骤107,执行退火步骤,以使所述含硼材料105中的硼进行扩散掺杂,以使所述含硼材料中的硼扩散至沟道停止区域中。Next, step 107 is performed, performing an annealing step, so that the boron in the boron-containing material 105 is diffused and doped, so that the boron in the boron-containing material 105 is diffused into the channel stop region.

具体地,如图13所示,所述退火的温度可以为700℃-1000℃。Specifically, as shown in FIG. 13 , the annealing temperature may be 700°C-1000°C.

在该步骤中通过退火使所述含硼材料104中的硼扩散,以实现沟道停止离子注入,以控制鳍片底部的的源漏由于部分耗尽造成穿通。In this step, the boron in the boron-containing material 104 is diffused by annealing, so as to implement channel-stop ion implantation, so as to control the source-drain at the bottom of the fin to cause punch-through due to partial depletion.

最后还进一步包括去除所述鳍片上的所述掩膜层的步骤,以露出所述鳍片,如图14所示。Finally, a step of removing the mask layer on the fins is further included to expose the fins, as shown in FIG. 14 .

至此,完成了本发明实施例的半导体器件制备的相关步骤的介绍。在上述步骤之后,还可以包括其他相关步骤,此处不再赘述。并且,除了上述步骤之外,本实施例的制备方法还可以在上述各个步骤之中或不同的步骤之间包括其他步骤,这些步骤均可以通过现有技术中的各种工艺来实现,此处不再赘述。So far, the introduction of the relevant steps of manufacturing the semiconductor device according to the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which will not be repeated here. Moreover, in addition to the above steps, the preparation method of this embodiment can also include other steps in the above steps or between different steps, and these steps can be realized by various processes in the prior art, here No longer.

本发明为了解决现有技术中存在的问题,提供了一种半导体器件的制备方法,在所述方法中为了降低所述输入输出区中沟道离子注入量,在所述输入输出区的鳍片底部(有效鳍片以下)的侧壁上形成衬垫层,然后在所述核心区和所述输入输出区中鳍片侧壁上形成含硼材料层和覆盖层,沉积隔离材料并回蚀刻至目标高度的鳍片,去除露出的所述硼材料层和覆盖层,最后执行退火步骤,在所述目标高度以下的鳍片底部进行硼离子扩散,使以使所述含硼材料中的硼扩散至沟道停止区域中,在所述输入输出区中所述衬垫层作为硼离子扩散到阻挡层,可以阻挡硼离子的扩散,从而避免了输入输出区中沟道停止离子注入过量,同时还能使核心区进行更多的沟道停止离子注入以减小由于短沟道效应引起的源漏穿通。In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device. In the method, in order to reduce the amount of channel ion implantation in the input-output region, the fins in the input-output region Form a liner layer on the sidewall of the bottom (below the effective fin), then form a boron-containing material layer and a cover layer on the sidewall of the fin in the core area and the input-output area, deposit an isolation material and etch back to Fins at a target height, removing the exposed boron material layer and covering layer, and finally performing an annealing step, performing boron ion diffusion at the bottom of the fin below the target height, so that boron in the boron-containing material can be diffused In the channel stop region, the liner layer in the input and output region diffuses to the barrier layer as boron ions, which can block the diffusion of boron ions, thereby avoiding excessive implantation of channel stop ions in the input and output region, and at the same time More channel-stop ion implantation can be performed in the core region to reduce the source-drain breakthrough caused by the short-channel effect.

参照图15,其中示出了本发明制备所述半导体器件的工艺流程图,用于简要示出整个制造工艺的流程,包括以下步骤:Referring to FIG. 15 , there is shown a process flow diagram for preparing the semiconductor device according to the present invention, which is used to briefly illustrate the flow of the entire manufacturing process, including the following steps:

步骤S1:提供半导体衬底,所述半导体衬底包括核心区和输入输出区,其中,在所述核心区和所述输入输出区上均形成有若干鳍片;Step S1: providing a semiconductor substrate, the semiconductor substrate includes a core area and an input-output area, wherein several fins are formed on both the core area and the input-output area;

步骤S2:在所述输入输出区上的所述半导体衬底上以及所述鳍片底部的侧壁上形成衬垫层;Step S2: forming a pad layer on the semiconductor substrate on the input-output region and on the sidewalls of the bottom of the fin;

步骤S3:在所述核心区的所述半导体衬底上、所述鳍片的表面上以及所述输入输出区中的所述衬垫层上和所述鳍片顶部的表面上依次形成含硼材料层和覆盖层;Step S3: sequentially forming a boron-containing substrate on the semiconductor substrate in the core area, on the surface of the fin, on the liner layer in the input-output area, and on the surface of the top of the fin. material layers and covering layers;

步骤S4:在所述覆盖层上形成隔离材料层至所述衬垫层顶部或以上,以部分覆盖所述鳍片,形成目标高度的鳍片;Step S4: forming an isolation material layer on the cover layer to the top of the liner layer or above to partially cover the fins to form fins with a target height;

步骤S5:去除露出的所述鳍片上的所述含硼材料层和所述覆盖层,以露出所述鳍片;Step S5: removing the boron-containing material layer and the covering layer on the exposed fins to expose the fins;

步骤S6:执行退火步骤,以使所述含硼材料中的硼扩散至沟道停止区域中。Step S6: performing an annealing step to diffuse boron in the boron-containing material into the channel stop region.

实施例二Embodiment two

本发明还提供了一种半导体器件,所述半导体器件选用实施例一所述的方法制备。The present invention also provides a semiconductor device, which is prepared by the method described in the first embodiment.

半导体衬底101,所述半导体衬底包括核心区和输入输出区;A semiconductor substrate 101, the semiconductor substrate includes a core area and an input and output area;

鳍片102,位于所述核心区和输入输出区上;Fins 102 located on the core area and the input and output areas;

隔离材料层106,位于所述半导体衬底上并且覆盖部分所述鳍片;an isolation material layer 106 located on the semiconductor substrate and covering part of the fins;

其中,所述鳍片中被所述隔离材料层106覆盖部分的表面依次形成有含硼材料层104和覆盖层105,其中,在所述输入输出区中在所述鳍片和所述含硼材料层104之间还形成有衬垫层层103。Wherein, a boron-containing material layer 104 and a covering layer 105 are sequentially formed on the surface of the part of the fin covered by the isolation material layer 106, wherein, in the input-output region, the fin and the boron-containing A liner layer 103 is also formed between the material layers 104 .

其中,所述半导体衬底101可以是以下所提到的材料中的至少一种:硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。Wherein, the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI) , silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

其中所述半导体衬底包括核心区和输入输出区,以在后续的步骤中形成不同的元件。Wherein the semiconductor substrate includes a core area and an input and output area, so as to form different elements in subsequent steps.

其中,所述鳍片的宽度全部相同,或者鳍片分为具有不同宽度的多个鳍片组。Wherein, the widths of the fins are all the same, or the fins are divided into multiple fin groups with different widths.

其中,所述衬垫层103包括氮化物层,在所述输入输出区域中,所述衬垫层103作为后续离子掺杂步骤中的离子扩散阻挡层,以防止在输入输出区中所述离子扩散形成过量掺杂。Wherein, the liner layer 103 includes a nitride layer, and in the input-output region, the liner layer 103 acts as an ion diffusion barrier layer in the subsequent ion doping step to prevent the ion diffusion in the input-output region Diffusion forms overdoping.

其中,所述衬垫层103可以通过加热氧化的方法形成,在一个实施例中,采用现场蒸汽生成工艺(ISSG)形成衬里层。Wherein, the liner layer 103 may be formed by heating and oxidation. In one embodiment, the liner layer is formed by an in-situ steam generation process (ISSG).

其中,所述含硼材料层104用于在后续的步骤中执行固体源漏掺杂沟道停止离子注入工艺,即通过退火步骤使所述含硼材料层104中的B扩散,以形成沟道停止离子注入区域。Wherein, the boron-containing material layer 104 is used to perform a solid source-drain doping channel stop ion implantation process in subsequent steps, that is, the B in the boron-containing material layer 104 is diffused through an annealing step to form a channel Stop ion implantation in the region.

可选地,所述含硼材料层104可以选用含硼玻璃层,例如硼磷玻璃(BSG),但并不局限于所述示例。Optionally, the boron-containing material layer 104 may be a boron-containing glass layer, such as boron phosphorous glass (BSG), but is not limited to the above examples.

其中,所述覆盖层105位于含硼材料层104的上方,所述可以选用本领域中常用的材料,例如各种氮化物,以防止在后续实施的工艺对鳍片结构的高度和特征尺寸造成损失。在一个实施例中,采用具有可流动性的化学气相沉积工艺(FCVD)形成覆盖层。Wherein, the cover layer 105 is located above the boron-containing material layer 104, and the materials commonly used in this field can be selected, such as various nitrides, so as to prevent the height and feature size of the fin structure from being affected by subsequent processes. loss. In one embodiment, the capping layer is formed by a flowable chemical vapor deposition process (FCVD).

所述覆盖层的材料可以为氮化硅。The material of the covering layer may be silicon nitride.

其中,隔离材料层的材料可以选择氧化物,例如HARP。在一个实施例中,采用具有可流动性的化学气相沉积工艺实施所述沉积。Wherein, the material of the isolation material layer may be oxide, such as HARP. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process.

本发明还提供了一种半导体器件,所述半导体器件中在所述输入输出区中所述目标鳍片底部的侧壁上形成所述衬垫层,在后续的执行退火步骤使所述含硼材料中的硼扩散至沟道停止区域的过程中,所述输入输出区中所述衬垫层作为硼离子扩散到阻挡层,可以阻挡硼离子的扩散,从而避免了输入输出区中沟道停止离子注入过量,同时还能使核心区进行更多的沟道停止离子注入以减小由于短沟道效应引起的源漏穿通。The present invention also provides a semiconductor device, in which the liner layer is formed on the sidewall of the bottom of the target fin in the input-output region, and the boron-containing During the process of boron in the material diffusing to the channel stop region, the liner layer in the input and output region diffuses to the barrier layer as boron ions, which can block the diffusion of boron ions, thereby avoiding the channel stop in the input and output region The ion implantation is excessive, and at the same time, more channel stop ion implantation can be performed in the core region to reduce the source-drain breakthrough caused by the short channel effect.

实施例三Embodiment three

本发明还提供了一种电子装置,包括实施例二所述的半导体器件。其中,半导体器件为实施例二所述的半导体器件,或根据实施例一所述的制备方法得到的半导体器件。The present invention also provides an electronic device, including the semiconductor device described in the second embodiment. Wherein, the semiconductor device is the semiconductor device described in the second embodiment, or the semiconductor device obtained according to the preparation method described in the first embodiment.

本实施例的电子装置,可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备,也可为任何包括所述半导体器件的中间产品。本发明实施例的电子装置,由于使用了上述的半导体器件,因而具有更好的性能。The electronic device of this embodiment can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV set, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. , can also be any intermediate product including the semiconductor device. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (10)

1. a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, the semiconductor substrate includes core space and I/O area, wherein in the core Heart district and the I/O area have been respectively formed on several fins;
Step S2: dew is formed in the semiconductor substrate on the I/O area and on the side wall of the fin bottom The laying of the fin of object height out;
Step S3: in the semiconductor substrate of the core space, on the surface of the fin and the I/O area In the laying on and the fin at the top of surface on sequentially form boracic material layer and coating;
Step S4: forming spacer material layer on the coating, partially to cover the fin, forms the object height Fin;
Step S5: the boracic material layer and the coating on the fin of exposing are removed, to expose the fin;
Step S6: annealing steps are executed, so that the boron containing in boron material diffuses in channel stop region.
2. the method according to claim 1, wherein the step S2 includes:
Step S21: in the semiconductor substrate of the core space and the I/O area and institute is formed on the fin Laying is stated, to cover in the semiconductor substrate and the fin;
Step S22: forming the first protective layer on the laying of the I/O area, to cover the laying;
Step S23: removing the laying in the core space, to expose the semiconductor substrate and the fin;
Step S24: exposing in the semiconductor substrate in the core space and being formed on the fin has the first height Second protective layer, with the semiconductor substrate being completely covered in the core space and the fin, and meanwhile it is defeated in the input Second protective layer with the second height is formed in area out, partially to cover the laying on the fin surface, forms institute State the fin of object height;
Step S25: removing the laying exposed in the I/O area, to be formed on the side wall of the fin bottom The laying.
3. according to the method described in claim 2, it is characterized in that, the step S24 includes:
Step S241: being formed on the fin of the core space and on the laying of the I/O area has institute Second protective layer of the first height is stated, the fin and the laying is completely covered;
Step S242: mask layer is formed on the second protective layer of the core space;
Step S243: being second protective layer in I/O area described in mask etch to second high using the mask layer Degree, to expose the laying at the top of fin described in the I/O area.
4. the method according to claim 1, wherein the boracic material layer selects boron-containing glass layer.
5. the method according to claim 1, wherein the step S4 includes:
Step S41: depositing the spacer material layer, to cover the fin;
Step S42: spacer material layer described in etch-back forms the fin of object height with fin described in exposed portion.
6. the method according to claim 1, wherein the step S1 includes:
Step S11: providing the semiconductor substrate, is formed with patterned mask layer on the semiconductor substrate;
Step S12: using the mask layer as semiconductor substrate described in mask etch, to form the fin.
7. according to the method described in claim 6, it is characterized in that, being still further comprised described in removal after the step S6 The step of mask layer on fin.
8. the method according to claim 1, wherein the coating selects nitride layer.
9. a kind of semiconductor devices being prepared based on method described in one of claim 1 to 8.
10. a kind of electronic device, including semiconductor devices as claimed in claim 9.
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