CN106601293A - Method and system for processing data in flash memories - Google Patents
Method and system for processing data in flash memories Download PDFInfo
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- CN106601293A CN106601293A CN201611181783.3A CN201611181783A CN106601293A CN 106601293 A CN106601293 A CN 106601293A CN 201611181783 A CN201611181783 A CN 201611181783A CN 106601293 A CN106601293 A CN 106601293A
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- 238000002347 injection Methods 0.000 claims description 7
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- 238000005452 bending Methods 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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Abstract
The invention discloses a method for processing data in flash memories. The method comprises the following steps: S10, dividing a memory array into 2n lines and m rows of memory units, wherein each flash memory is formed by at least one memory array, and the flash memories comprise NOR flash memories and NAND flash memories; and S30, when data is wiped off each flash memory, carrying out data wiping processing on the corresponding memory units on the alternate lines. The method provided by the invention has the advantages that through the alternate line wiping mode, both sides of each memory unit in a wiping status can be affected by voltage coupling of the memory units in a non-wiping status, so that a consistent overall wiping speed and the data wiping accuracy of each flash memory are ensured.
Description
Technical field
It is more particularly to a kind of to process in FLASH memory the method for data and be the invention belongs to memory technology field
System.
Background technology
FLASH memory belongs to one kind of memory devices also known as flash memory, not only possesses the programmable property of Electrical Erasable
Can, will not also power-off lose data, and can quickly read data.At present, FLASH memory mainly has following two on market
Kind：NOR FLASH memories and NAND FLASH memories.Wherein, FLASH flash memories have several memory element, each
Memory element includes multiple floating-gate pipes.
Traditionally, it is that the data in continuous line storage unit are wiped when wiping data in FLASH flash memories.
However, when wiping data in the memory unit, in memory element cathetus electric field (as shown in Figure 6) of erase status, easily
By neighbouring side, coupled interference is affected in the memory element in non-erase status, is caused in the unit of erase status
Straight line electric field can bend.(as shown in Figure 7).
During due to wiping data to memory element, apply just low on to the wordline in the memory element of non-erase status
Pressure (positive low pressure is generally supply voltage, such as 3.3V, 1.8V etc.) makes that it is hanging (hanging wordline can be coupled into the by source
One pre-set forward voltage), and cause memory element cathetus electric field of the neighbouring side in erase status to produce bending.Further,
So that the erasing speed of memory element is inconsistent in FLASH flash memories, it is final affect in FLASH flash memories overall efficiency of erasing and
Erasing accuracy.
The content of the invention
The technical scheme that the present invention is provided is as follows：
The present invention provides a kind of method for processing data in FLASH memory, comprises the following steps：S10, by one piece storage
Array is divided into 2n row * m array storage units, at least constitutes a FLASH memory by one piece of storage array；The FLASH is deposited
Reservoir includes NOR FLASH memories and NAND FLASH memories；S30, in the FLASH memory wipe data when,
Data erasing process is carried out to the memory element on interval setting row.
Further, it is further comprising the steps of：S20, in the FLASH memory write data when, to interval setting row
On memory element carry out data write process.
Further, it is further comprising the steps of：S21, when writing data again in the FLASH memory, then it is pointed to
Memory element between interval setting row carries out data write process；S31, data are wiped in the FLASH memory again
When, then be pointed to the memory element between interval setting row and carry out data erasing process.
Further, step S10 is further included：11st, when the FLASH memory is NOR FLASH memories,
The control gate of floating-gate pipe in every line storage unit is connected and 2n bar wordline is formed, by the leakage of floating-gate pipe in every array storage unit
Extremely it is connected and forms m bar bit lines, the source electrode of floating-gate pipe in each row and column memory element is connected and a source is formed.
Further, step S30 is further included：S301, in the NOR FLASH memories wipe data when,
Apply the first default negative voltage in wordline in memory element on interval setting row；Bit line in the memory element is hanged
It is empty；Apply the first pre-set forward voltage in source in the memory element；S302, according to the first default negative sense electricity for applying
Pressure and the first pre-set forward voltage；Tunnel-effect is formed in memory element on interval setting row, to the FLASH memory
The memory element of upper discontinuous row carries out data erasing.
Further, step S31 is further included：S311, in the NOR FLASH memories data are wiped again
When, then apply the first default negative voltage in the wordline between positioned at interval setting row in memory element；The storage is single
Bit line in unit is hanging；Apply the first pre-set forward voltage in source in the memory element；S312, according to for applying
One default negative voltage and the first pre-set forward voltage；Tunnel effect is formed in memory element between positioned at interval setting row
Should, data erasing is carried out to the memory element of discontinuous row in the FLASH memory.
Further, step S20 is further included：S201, in the NOR FLASH memories write data when,
Apply the second pre-set forward voltage in wordline in memory element on interval setting row；On bit line in the memory element
Apply the 3rd pre-set forward voltage；Source in the memory element is grounded；S202, according to apply the second pre-set forward electricity
Pressure and the 3rd pre-set forward voltage；Thermoelectron injection is formed in memory element on interval setting row, the FLASH is stored
The memory element of discontinuous row carries out data write on device.
Further, step S21 is further included：S211, in the NOR FLASH memories data are write again
When, then apply the second pre-set forward voltage in the wordline between positioned at interval setting row in memory element；It is single in the storage
Apply the 3rd pre-set forward voltage on bit line in unit；Source in the memory element is grounded；S212, according to for applying
Two pre-set forward voltages and the 3rd pre-set forward voltage；Thermoelectron note is formed in memory element between positioned at interval setting row
Enter, data write is carried out to the memory element of discontinuous row in the FLASH memory.
The present invention also provides a kind of system for applying the data in FLASH memory is processed, including：FLASH memory, extremely
It is few to be made up of one piece of storage array, one piece of storage array is divided into into 2n row * m array storage units；The FLASH memory includes
NOR FLASH memories and NAND FLASH memories；Data wipe module, when wiping data in the FLASH memory,
Data erasing process is carried out to the memory element on interval setting row；Data write. module, writes in the FLASH memory
During data, data write process is carried out to the memory element on interval setting row.
Further, when the FLASH memory is NOR FLASH memories, the control of floating-gate pipe in every line storage unit
Grid processed is connected and forms 2n bar wordline, per array storage unit in the drain electrode of floating-gate pipe be connected and form m bar bit lines, each row and column
The source electrode of floating-gate pipe is connected and forms a source in memory element.
Compared with prior art, the method and system of data, have in a kind of process FLASH memory that the present invention is provided
Following beneficial effect：
1) present invention wipes mode so that the storage list in erase status in FLASH memory using spaced rows
Unit, both sides are subject to because of the memory cell voltages coupling influence in erase status；When avoiding continuous erasing, in erasing
Memory element in state, only by side because the coupled interference of the memory element in non-erase status is affected；So as to protect
Overall erasing speed is consistent in card FLASH memory, and guarantees data erasing accuracy in FLASH memory.
2) present invention is abandoned using continuous row writing mode in FLASH memory, and adopts spaced rows writing mode,
Collocation spaced rows erasing mode, can disposably wipe the data of spaced rows write, be conducive to improving efficiency of erasing；Avoid utilization
During continuous row writing mode, because wiping mode using spaced rows, and need to wipe twice, the number that continuous row write enters could be wiped
According to.
3) the memory element write one in the present invention in write-once data, on interval setting (odd number or even number) row
Data；When data are write again, in the memory element between interval setting (even number or odd number) row another data are write；
Collocation interval erasing mode, not only ensure that overall erasing speed is consistent in FLASH memory, and guarantee FLASH memory
Middle data wipe accuracy；The memory space of the efficiency of erasing and FLASH memory that also improve FLASH memory is utilized
Rate.
Description of the drawings
Below by clearly understandable mode, preferred implementation is described with reference to the drawings, to a kind of FLASH memory is processed
The above-mentioned characteristic of the method and system of middle data, technical characteristic, advantage and its implementation are further described.
Fig. 1 is a kind of schematic flow sheet for processing the method for data in FLASH memory of the present invention；
Fig. 2 is another kind of schematic flow sheet for processing the method for data in FLASH memory of the invention；
Fig. 3 is the schematic flow sheet of the method for data in another process FLASH memory of the invention；
Fig. 4 is a kind of composition structural representation for processing the system of data in FLASH memory of the present invention；
Fig. 5 is another kind of composition structural representation for processing the system of data in FLASH memory of the invention；
Fig. 6 is that electric field is not affected by the structural representation for disturbing in floating-gate pipe of the present invention；
Fig. 7 is the structural representation that electric field side is interfered in floating-gate pipe of the present invention；
Fig. 8 is the structural representation that electric field both sides are interfered in floating-gate pipe of the present invention；
Fig. 9 is the structural representation of neutrality line continuous data write programming of the present invention；
Figure 10 is the structural representation of neutrality line non-continuous data write programming of the present invention；
Figure 11 is the schematic flow sheet of the method for data in another process FLASH memory of the invention.
Drawing reference numeral explanation：
10th, FLASH memory, 11, control gate, 12, floating grid, 13, substrate, 20, line decoder, 21, voltage control
Molding block, 30, column decoder, 31, voltage control submodule, 40, voltage controller, 50, Data write. module, 60, data wipe
Except module.
Specific embodiment
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below by control description of the drawings
The specific embodiment of the present invention.It should be evident that drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, can be obtaining other according to these accompanying drawings
Accompanying drawing, and obtain other embodiments.
To make simplified form, part related to the present invention is only schematically show in each figure, they are not represented
Its practical structures as product.In addition, so that simplified form is readily appreciated, with identical structure or function in some figures
Part, only symbolically depicts one of those, or has only marked one of those.Herein, " one " is not only represented
" only this ", it is also possible to represent the situation of " more than one ".
As shown in figure 1, according to one embodiment of present invention, a kind of method for processing data in FLASH memory, including
Following steps：S10, one piece of storage array is divided into 2n row * m (m, n are positive integer) array storage unit, at least by one piece of storage
Array constitutes a FLASH memory；The FLASH memory includes NOR FLASH memories and NAND FLASH memories；
The storage array is arranged on the same substrate, and each memory element includes multiple floating-gate pipes；The floating-gate pipe includes being arranged on
Source electrode, control gate and drain electrode on the substrate 13, is arranged in each floating-gate pipe between the substrate 13, control gate 11
There is floating grid 12.
S30, in the FLASH memory wipe data when, to depositing on interval setting row (odd-numbered line or even number line)
Storage unit (multiple floating-gate pipes) carries out data erasing process.
Specifically, when wiping data in the FLASH memory, when using traditionally continuous row writing mode (such as
Shown in Fig. 9), write in the memory element on continuous row after data, can first wipe odd-numbered line to wipe mode using spaced rows
Data in (or even number line) in memory element；Wiped using spaced rows erasing mode again and store in even number line (or odd-numbered line) single
Data in unit；Data in memory element on continuous row can be wiped.(such as Figure 10 institutes when using spaced rows writing mode
Show), write after data in memory element in odd-numbered line (or even number line)；Directly mode is wiped using spaced rows, in odd-numbered line
Data are wiped in (or even number line) in memory element.
As shown in Fig. 2 according to another embodiment of the invention, a kind of method for processing data in FLASH memory, bag
Include following steps：S10, one piece of storage array is divided into 2n row * m array storage units, at least constitutes one by one piece of storage array
Individual FLASH memory；The FLASH memory includes NOR FLASH memories and NAND FLASH memories；The storage battle array
Row are arranged on the same substrate, and each memory element includes multiple floating-gate pipes；The floating-gate pipe includes being arranged on the substrate 13
On source electrode, control gate and drain electrode, be provided with floating grid between the substrate 13, control gate 11 in each floating-gate pipe
12。
S20, in the FLASH memory write data when, to memory element (the multiple floating booms on interval setting row
Pipe) carry out data write process.
S21, when writing data again in the FLASH memory, then the storage list being pointed between interval setting row
First (multiple floating-gate pipes) carries out data write process；
S30, in the FLASH memory wipe data when, to depositing on interval setting row (odd-numbered line or even number line)
Storage unit (multiple floating-gate pipes) carries out data erasing process.
S31, when wiping data again in the FLASH memory, then the storage list being pointed between interval setting row
First (multiple floating-gate pipes) carries out data erasing process.
Specifically, when using spaced rows writing mode, can in odd-numbered line (or even number line) memory element it is (multiple floating
Bank tube) one data of middle write；Again write data when, can in even number line (or odd-numbered line) memory element (multiple floating-gate pipes)
It is middle to write another data.Using interval writing mode collocation interval erasing mode, can not only guarantee erasing speed it is consistent and
The accuracy of erasing data, can also once wipe the data of spaced rows storage, be conducive to improving efficiency of erasing.
As shown in figure 3, according to still a further embodiment, a kind of method for processing data in FLASH memory, bag
Include following steps：S10, one piece of storage array is divided into 2n row * m array storage units, at least constitutes one by one piece of storage array
Individual FLASH memory；The FLASH memory includes NOR FLASH memories and NAND FLASH memories；The storage battle array
Row are arranged on the same substrate, and each memory element includes multiple floating-gate pipes；The floating-gate pipe includes arranging over the substrate
Source electrode, control gate and drain electrode, be provided with floating grid between the substrate, control gate in each floating-gate pipe.
S11, when the FLASH memory be NOR FLASH memories when, by the control of floating-gate pipe in every line storage unit
Grid is connected and forms 2n bar wordline, and the drain electrode of floating-gate pipe in every array storage unit is connected and m bar bit lines are formed, and will often go every
The source electrode of floating-gate pipe is connected and forms a source in array storage unit.The source electrode of floating-gate pipe is arranged in adjacent rows memory element
In opposite inner side, the drain electrode of floating-gate pipe in adjacent rows memory element is arranged on mutually laterally, floats in adjacent rows memory element
The source electrode of bank tube shares a connecting line.
S201, in the NOR FLASH memories write data when, it is (multiple in memory element on interval setting row
Floating-gate pipe) wordline on apply the second pre-set forward voltage；Apply on the bit line of (multiple floating-gate pipes) in the memory element
3rd pre-set forward voltage；By the source ground connection of (multiple floating-gate pipes) in the memory element；
S202, according to the second pre-set forward voltage and the 3rd pre-set forward voltage for applying, second pre-set forward electricity
Press as 8～11V, the 3rd pre-set forward voltage is 4～6V；In memory element (multiple floating-gate pipes) on interval setting row
Thermoelectron injection is formed, data write is carried out to the memory element (multiple floating-gate pipes) of discontinuous row in the FLASH memory.
S211, when writing data again in the NOR FLASH memories, then store between positioned at interval setting row
Apply the second pre-set forward voltage in unit in the wordline of (multiple floating-gate pipes)；In the memory element (multiple floating-gate pipes)
Apply the 3rd pre-set forward voltage on bit line；By the source ground connection of (multiple floating-gate pipes) in the memory element；
S212, according to apply the second pre-set forward voltage and the 3rd pre-set forward voltage；Positioned at interval setting row it
Between memory element (multiple floating-gate pipes) on formed thermoelectron injection, the storage list to discontinuous row in the FLASH memory
First (multiple floating-gate pipes) carries out data write.
S301, in the NOR FLASH memories wipe data when, it is (multiple in memory element on interval setting row
Floating-gate pipe) wordline on apply the first default negative voltage；Bit line in the memory element is hanging；In the memory element
In source on apply the first pre-set forward voltage；The first pre-set forward voltage is 4～6V, and the described first default negative sense is electric
- 8～-10V of pressure；
S302, according to the first default negative voltage and the first pre-set forward voltage for applying；Depositing on interval setting row
Tunnel-effect is formed on storage unit (multiple floating-gate pipes), it is (multiple floating to the memory element of discontinuous row in the FLASH memory
Bank tube) carry out data erasing.
S311, when wiping data again in the NOR FLASH memories, then store between positioned at interval setting row
Apply the first default negative voltage in unit in the wordline of (multiple floating-gate pipes)；By (multiple floating-gate pipes) in the memory element
Bit line is hanging；Apply the first pre-set forward voltage in the source of (multiple floating-gate pipes) in the memory element；
S312, according to the first default negative voltage and the first pre-set forward voltage for applying；Positioned at interval setting row it
Between memory element (multiple floating-gate pipes) on form tunnel-effect, the memory element to discontinuous row in the FLASH memory
(multiple floating-gate pipes) carries out data erasing.
Specifically, NOR FLASH memories include 2n row * m array storage units, with 2n bar wordline, m bar bit lines, one
Source, if：Wordline is WL1, WL2, WL3 ... ..., and WL (t-1) arrives WL2n, as shown in Figure 5.
When using continuous row data writing mode, therebetween interlaced data erase process is as follows：
WL2, WL4 ... ..., WL (t-2) are wiped for the first time, it is assumed that when t is even number, the floating-gate pipe in these even wordlines；
To WL2, WL4 ... ..., WL (t-2) these even wordlines apply first default negative voltages；All bit lines are hanging, in source
Apply the first pre-set forward voltage；And to WL3, WL5 ... ..., WL (t-1) these positions of odd wordlines apply positive high voltage (4～6V) or
Make its hanging.
Due to wordline WL2, adjacent wordline WL1 in WL4 ... ..., WL (t-2) both sides, WL3, WL5 ... ..., WL (t-1) is
(positive low pressure is generally supply voltage, for example to be applied with positive low pressure：3.3V, 1.8V) or it has been coupled the first pre-set forward pressure, institute
With wordline WL2, the electric field of the floating-gate pipe both sides on WL4 ... ..., WL (t-2) is no longer vertical, all can bend.Due to word
The electric field of the floating-gate pipe both sides on line WL2, WL4 ... ..., WL (t-2) bends (as shown in Figure 8), and F-N tunnel-effects are produced
Raw current value is identical, and its erasing speed is consistent.
In the same manner, when second erasing WL3, floating-gate pipe in WL5 ... ..., WL (t-1) these positions of odd wordlines；To WL3,
WL5 ... ..., WL (t-1) these positions of odd wordlines apply a default negative voltages；All bit lines are hanging, apply first in source
Pre-set forward voltage；And to WL2, WL4 ... ..., WL (t-2) these even wordlines apply positive low pressure (generally supply voltage, example
Such as 3.3V, 1.8V) or hanging (hanging wordline can be coupled into the first pre-set forward pressure by source).
Wordline WL3, the electric field of the floating-gate pipe both sides on WL5 ... ..., WL (t-1) is no longer vertical, all can bend.
Now wordline WL3, the floating-gate pipe electric field all same on WL5 ... ..., WL (t-1), so during erasing, what F-N tunnel-effects were produced
Current value is identical, and erasing speed is also consistent.
Traditionally, mode is wiped using continuous row, when to wordline WL2, the floating-gate pipe on WL3, WL4 to WL (t-1) is carried out
During continuous erasing (as shown in Figure 10), wherein t is positive integer, t>3, negative height is applied in wordline WL2, WL3, WL4 to WL (t-1)
Pressure (- 8～-10V), but due to being wiped to the floating-gate pipe on WL2n wordline WL1, WLt and WL (t+1), wherein n
For positive integer, n>2 (t-1), so in wordline WL1, WLt and WL (t+1) applies positive low pressure on WL2n, and (generally chip is electric
Source voltage, such as 3.3V, 1.8V etc.) or make its hanging.
Due to wordline WL3, the floating-gate pipe on WL4 to WL (t-2) adjacent word line is in erase status, so wordline WL3,
Floating-gate pipe electric field on WL4 to WL (t-2), electric field is vertically upward.But wordline WL2, WL (t-1) adjacent word line WL1, on WLt
Floating-gate pipe is in non-erase status, now wordline WL2, and the floating-gate pipe electric field on WL (t-1) is (with wordline WL1, the adjacent sides of WLt
Electric field) will be no longer vertical, and wordline WL1 can be subject to, malleation on WLt (as it is possible that being positive low pressure, it is also possible to be by
First pre-set forward pressure of source coupling) affect, bending is produced, such case is referred to as edge effect.Therefore, wordline WL2, WL
(t-1) floating-gate pipe on and wordline WL3, the data erasing speed of the floating-gate pipe on WL4 to WL (t-2) is inconsistent.
As shown in figure 4, according to one embodiment of present invention, a kind of system for processing data in FLASH memory, bag
Include：FLASH memory 10, is at least made up of one piece of storage array and for one piece of storage array to be divided into 2n row * m array storage units；
The FLASH memory includes NOR FLASH memories and NAND FLASH memories；The storage array is arranged on same lining
On bottom, each memory element includes multiple floating-gate pipes；The floating-gate pipe includes source electrode, the control gate being arranged on the substrate 13
Pole and drain electrode, are provided between the substrate 13, control gate 11 floating grid 12 in each floating-gate pipe.
When the FLASH memory is NOR FLASH memories, the control gate phase of floating-gate pipe in every line storage unit
Connect and formed 2n bar wordline, be connected and formed m bar bit lines, each row and column memory element per the drain electrode of floating-gate pipe in array storage unit
The source electrode of middle floating-gate pipe is connected and forms a source.The source electrode of floating-gate pipe is arranged on mutually inwardly in adjacent rows memory element
Side, the drain electrode of floating-gate pipe in adjacent rows memory element is arranged on mutually laterally, the source of floating-gate pipe in adjacent rows memory element
Extremely share a connecting line.
Line decoder 20, column decoder 30 and voltage controller 40, in the NOR FLASH memories data are write
When, the line decoder 20 includes voltage control module 21, in memory element on interval setting row (multiple floating-gate pipes)
Wordline on apply the second pre-set forward voltage；The column decoder 30 includes voltage control submodule 31, for depositing described
Apply the 3rd pre-set forward voltage in storage unit on the bit line of (multiple floating-gate pipes)；The voltage controller 40, for will be described
The source ground connection of (multiple floating-gate pipes) in memory element；
Data write. module 50, for according to the second pre-set forward voltage and the 3rd pre-set forward voltage for applying；
Thermoelectron injection is formed in the memory element (multiple floating-gate pipes) arranged on row, to discontinuous row in the FLASH memory
Memory element (multiple floating-gate pipes) carry out data write.
When writing data again in the NOR FLASH memories, the voltage control module 21, for being located at again
Apply the second pre-set forward voltage between interval setting row in memory element in the wordline of (multiple floating-gate pipes)；The voltage control
Submodule 22, for applying the 3rd pre-set forward voltage on the bit line of (multiple floating-gate pipes) in the memory element；The electricity
Pressure controller 40, for the source of (multiple floating-gate pipes) in the memory element to be grounded；
Data write. module 60, for according to the second pre-set forward voltage and the 3rd pre-set forward voltage for applying；In place
Thermoelectron injection is formed in memory element (multiple floating-gate pipes) between interval setting row, to non-in the FLASH memory
Consecutive rows of memory element (multiple floating-gate pipes) carries out data write.
When wiping data in the NOR FLASH memories, the voltage control module 21, in interval setting row
Apply the first default negative voltage in upper memory element in the wordline of (multiple floating-gate pipes)；The voltage control submodule 31, uses
In the bit line in the memory element is hanging；The voltage controller 40, for applying in the source in the memory element
Plus the first pre-set forward voltage；The first pre-set forward voltage is 6～8V, the first preset direction -8～-10V of voltage；
Data wipe module 60, according to the first default negative voltage and the first pre-set forward voltage that apply；Set at interval
Put and form tunnel-effect in the memory element (multiple floating-gate pipes) on row, the storage to discontinuous row in the FLASH memory
Unit (multiple floating-gate pipes) carries out data erasing.
When wiping data again in the NOR FLASH memories, the voltage control module 21, for being located at again
Apply the first default negative voltage between interval setting row in memory element in the wordline of (multiple floating-gate pipes)；The voltage control
Submodule 31, for the bit line of (multiple floating-gate pipes) in the memory element is hanging；The voltage controller 40, in institute
State and apply in the source of (multiple floating-gate pipes) in memory element the first pre-set forward voltage；
Data wipe module 60, according to the first default negative voltage and the first pre-set forward voltage that apply；Between being located at
Tunnel-effect is formed in the memory element (multiple floating-gate pipes) arranged between row, to discontinuous row in the FLASH memory
Memory element (multiple floating-gate pipes) carry out data erasing.
Specifically, in order to ensure the correctness of data storage, impact of the unstable factor to edge memory element is excluded,
The bit error rate is reduced, preposition isolation area is set before first trip memory element, rearmounted isolation area is set after footline memory element, it is described
Preposition isolation area, rearmounted isolation area are a line or two line storage units.Only between preposition isolation area and rearmounted isolation area
Data storage and erasing data in memory element.
Wherein, the minimum erasing unit of NOR FLASH memories is a memory element.During erasing, source class applies positive high voltage,
Bit line is hanging, and wordline applies negative high voltage, and so both voltage differences can form F-N tunnel-effects so that the electronics in floating boom flows out,
Change the threshold voltage of storage unit tube.Simultaneously the wordline of non-erasing regional memory cell is to positive low pressure or makes it hanging, will not
Produce F-N tunnel-effects.
As shown in figure 11, according to still another embodiment of the invention, a kind of method for processing data in FLASH memory,
Comprise the following steps：
S1, NOR FLASH memory receiving data store instruction.The NOR FLASH memories include one piece of storage battle array
Row, described storage array is divided into multiple memory element, and described memory element is divided into multiple storage sections, described storage battle array again
Row make on the same substrate, and each memory element wipes unit for the minimum of NOR FLASH memories.
S2, decoder carry out the discontinuous decoding on physical address, make data that discontinuous storage is carried out on physical address.
S3, NOR FLASH memory receiving data erasing instruction.
S4, due to data on physical address be discontinuous storage, therefore decoder carry out it is discontinuous on physical address
Decoding.
S5, the bit line being vacantly connected with storage array, and apply positive high voltage to source.
The control gate of S6, the positive low pressure of applying to non-erasing memory element makes its hanging.
S7, applying negative high voltage need to extremely wipe the control gate of memory element.The negative high voltage of control gate and the positive height of source electrode
Pressure produces F-N tunnel-effects, realizes erasing.
S8, on physical address discontinuous erasing is carried out to data.
NOR FLASH memories include：Storage array 10, line decoder 11, column decoder 12.Storage array includes：2n
Bar wordline and m bar bit lines, wherein, n and m is positive integer, n>2, m>2.Each floating-gate pipe is a memory element, each storage
Unit has control gate, floating grid, source electrode and drain electrode.Wordline is connected on the grid end of floating-gate pipe, and bit line is connected on floating-gate pipe
Drain terminal, the source of all floating-gate pipes is connected together.Line decoder chooses the wordline of memory element, column decoder to choose storage single
The bit line of unit.
When programming to described NOR FLASH memories, and non-logarithmic is according to the seriality programming carried out on physical address,
I.e. in wordline WL1 floating-gate pipe programming after, not continue in wordline WL2 floating-gate pipe program, but jump directly to it is right
In wordline WLk floating-gate pipe programming, wherein k be positive integer, k>2, it is herein simplified explanation, it is assumed that wherein k=3.Then redirect
To on to wordline WLm floating-gate pipe programming, wherein m be positive integer, m>K+1, it is also assumed that m=5, by that analogy, vacation herein
If being not limited to the present invention.Finally make data that discontinuous storage is defined on physical address, i.e., be stored in word in the past
Data in the upper floating-gate pipe of line WL1, WL2, WL3 to WLn will be stored in wordline WL1, and WL3, WL5 ... ... are floating on WL (2n-1)
In bank tube, wherein n be positive integer, n>2.
When sector erasing is carried out to described NOR FLASH memories, due to data define on physical address it is non-
Coutinuous store, i.e., be stored in wordline WL1 in the past, and WL2, the data in floating-gate pipe on WL3 to WLt will be stored in wordline WL1,
WLk, WLm ... ..., in the floating-gate pipe on WLn, wherein t be positive integer, t>3, wherein n be positive integer, n>2 (t-1), physically
Continuation address become discontinuous address physically.Originally to wordline WL1, WL2, the floating-gate pipe on WL3 to WLt is wiped
Remove, also become in order to wordline WL1, WLk, WLm ... ..., the floating-gate pipe on WLn is wiped.I.e. to the wiping of continuous physical address
Except change is for the erasing to non-contiguous physical address.Now except wordline WL1, WLk, WLm ... ..., other wordline beyond WLn
On floating-gate pipe be in non-erase status.
When wiping the memory element in described NOR FLASH memories, wherein NOR FLASH memories are minimum
Erasing unit is a storage sector.Both during erasing, source class applies positive high voltage, and bit line is hanging, and wordline applies negative high voltage, so
Voltage difference can form F-N tunnel-effects so that the electronics in floating boom flows out, and change the threshold voltage of storage unit tube.It is simultaneously non-
The wordline of erasing regional memory cell will not produce F-N tunnel-effects to positive high voltage.
Script is stored in into wordline WL1, WL2, the data in floating-gate pipe on WL3 to WLn will be stored in wordline WL1,
WL3, WL5 ... ..., are also to wordline WL1, WL3, WL5 ... ..., on WL (2n-1) during erasing in the floating-gate pipe on WL (2n-1)
Floating-gate pipe erasing, due to wordline WL1, WL3, WL5 ... ..., the floating-gate pipe on WL (2n-1) adjacent word line is in non-erasing
State, in the wordline of non-erasing floating-gate pipe positive high voltage can be applied, so now wordline WL1, WL3, WL5 ... ..., on WL (2n-1)
Floating-gate pipe electric field as shown in figure 4, so during erasing, the current value that F-N tunnel-effects are produced is identical, erasing speed
It is consistent.
Line decoder, when programming to described NOR FLASH memories, and non-logarithmic is according to the company carried out on physical address
Continuous property programming, after programming the floating-gate pipe in wordline WL1, not continues to program the floating-gate pipe in wordline WL2, but directly jumps
Go to in wordline WLk floating-gate pipe program, wherein k be positive integer, k>2, then branch to compile the floating-gate pipe in wordline WLm
Journey, wherein m be positive integer, m>K+1, by that analogy.Finally make data that discontinuous storage is defined on physical address.It is discontinuous
Storage mode, when the data stored to this noncontinuity are wiped, referred to as noncontinuity wipes mode, noncontinuity erasing
Erasing speed is inconsistent caused by edge effect when mode solves the problems, such as that seriality is wiped, and optimizes erasing accuracy and effect
Rate.
Specifically, because data become noncontinuity storage, said method can't be wiped such as traditional noncontinuity
Equally increase erasing times, i.e., be stored in wordline WL1 in the past, WL2, the data in floating-gate pipe on WL3 to WLn will be stored in word
Line WL1, WL3, WL5 ... ..., in the floating-gate pipe on WL (2n-1), during erasing and need not respectively to the floating boom in positions of odd wordlines
Floating-gate pipe on pipe and even number is wiped, i.e., will not increase erasing times.
In the present embodiment, the discontinuous decoding on physical address is carried out due to decoder so that data are on physical address
Discontinuous storage is carried out, and then makes to be similarly discrete during erasing data.This mode greatly reduces wordline coupling to be caused
The inconsistent problem of erasing speed so that the memory element erasing speed being wiped free of is consistent, and then causes after erasure completion
No longer need erasing to repair operation, reduce the time overhead of erasing, improve erasing speed, the accuracy of FLASH memory
And efficiency.
First make that data are discontinuous to be stored in storage array, and then discontinuous erasing mode is carried out on physical address, this
Mode neither increases erasing times, while each floating-gate pipe erasing speed being wiped free of can also be kept to be consistent.
When floating-gate pipe is wiped free of, negative high voltage, when floating-gate pipe is not wiped free of, the word of floating-gate pipe are added in the wordline of floating-gate pipe
Add positive high voltage on line.The floating-gate pipe being wiped free of can be subject to the coupled interference of surrounding wordline, have influence on the electricity being wiped free of on floating-gate pipe
Field distribution, if each floating-gate pipe being wiped free of is subject to the coupled interference of surrounding wordline identical, then all to be wiped free of floating boom
Electric Field Distribution on pipe will be all identical, so as to the erasing speed of each floating-gate pipe being wiped free of will be consistent, otherwise if having some quilts
When the floating-gate pipe of erasing is subject to the coupled interference of surrounding wordline different, then the Electric Field Distribution on the floating-gate pipe will be differed also,
Now the erasing speed of the floating-gate pipe will differ from the floating-gate pipe that other are wiped free of, and this will cause overall erasing speed to differ
Cause, have influence on erasing accuracy and efficiency.
It should be noted that above-described embodiment can independent assortment as needed.The above is only the preferred of the present invention
Embodiment, it is noted that for those skilled in the art, in the premise without departing from the principle of the invention
Under, some improvements and modifications can also be made, these improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
1. it is a kind of process FLASH memory in data method, it is characterised in that comprise the following steps：
S10, one piece of storage array is divided into 2n row * m array storage units, at least a FLASH is constituted by one piece of storage array
Memorizer；The FLASH memory includes NOR FLASH memories and NAND FLASH memories；
S30, in the FLASH memory wipe data when, the memory element on interval setting row is carried out at data erasing
Reason.
2. the method for processing data in FLASH memory as claimed in claim 1, it is characterised in that further comprising the steps of：
S20, in the FLASH memory write data when, the memory element on interval setting row is carried out at data write
Reason.
3. the method for processing data in FLASH memory as claimed in claim 2, it is characterised in that further comprising the steps of：
S21, when writing data again in the FLASH memory, then the memory element being pointed between interval setting row is entered
The write of row data is processed；
S31, when wiping data again in the FLASH memory, then the memory element being pointed between interval setting row is entered
The erasing of row data is processed.
4. in the process FLASH memory as described in any one in claims 1 to 3 data method, it is characterised in that institute
State step S10 to further include：
S11, when the FLASH memory be NOR FLASH memories when, by the control gate of floating-gate pipe in every line storage unit
It is connected and is formed 2n bar wordline, the drain electrode of floating-gate pipe in every array storage unit is connected and m bar bit lines are formed, each row and column is deposited
The source electrode of floating-gate pipe is connected and forms a source in storage unit.
5. the method for processing data in FLASH memory as claimed in claim 4, it is characterised in that step S30 enters
Step includes：
S301, in the NOR FLASH memories wipe data when, apply in the wordline in memory element on interval setting row
Plus the first and preset negative voltage；Bit line in the memory element is hanging；Apply in source in the memory element
One pre-set forward voltage；
S302, according to the first default negative voltage and the first pre-set forward voltage for applying；Storage list on interval setting row
Tunnel-effect is formed in unit, data erasing is carried out to the memory element of discontinuous row in the FLASH memory.
6. the method for processing data in FLASH memory as claimed in claim 4, it is characterised in that step S31 enters
Step includes：
S311, when wiping data again in the NOR FLASH memories, then the memory element between positioned at interval setting row
In wordline on apply the first default negative voltage；Bit line in the memory element is hanging；In the memory element
Apply the first pre-set forward voltage in source；
S312, according to the first default negative voltage and the first pre-set forward voltage for applying；Between interval setting row
Tunnel-effect is formed in memory element, data erasing is carried out to the memory element of discontinuous row in the FLASH memory.
7. the method for processing data in FLASH memory as claimed in claim 4, it is characterised in that step S20 enters
Step includes：
S201, in the NOR FLASH memories write data when, apply in the wordline in memory element on interval setting row
Plus the second pre-set forward voltage；Apply the 3rd pre-set forward voltage on bit line in the memory element；The storage is single
Source ground connection in unit；
S202, according to apply the second pre-set forward voltage and the 3rd pre-set forward voltage；Storage list on interval setting row
Thermoelectron injection is formed in unit, data write is carried out to the memory element of discontinuous row in the FLASH memory.
8. the method for processing data in FLASH memory as claimed in claim 4, it is characterised in that step S21 enters
Step includes：
S211, when writing data again in the NOR FLASH memories, then the memory element between positioned at interval setting row
In wordline on apply the second pre-set forward voltage；Apply the 3rd pre-set forward voltage on bit line in the memory element；
Source in the memory element is grounded；
S212, according to apply the second pre-set forward voltage and the 3rd pre-set forward voltage；Between interval setting row
Thermoelectron injection is formed in memory element, data write is carried out to the memory element of discontinuous row in the FLASH memory.
9. it is a kind of apply in the process FLASH memory as described in any one in claim 1～8 method of data be
System, it is characterised in that include：
FLASH memory, is at least made up of one piece of storage array, and one piece of storage array is divided into into 2n row * m array storage units；
The FLASH memory includes NOR FLASH memories and NAND FLASH memories；
Data wipe module, when wiping data in the FLASH memory, to the memory element on interval setting row line number are entered
Process according to erasing；
Data write. module, when writing data in the FLASH memory, to the memory element on interval setting row line number is entered
Process according to write.
10. the system for processing data in FLASH memory as claimed in claim 9, it is characterised in that：
When the FLASH memory is NOR FLASH memories, the control gate of floating-gate pipe is connected simultaneously in every line storage unit
2n bar wordline is formed, the drain electrode of floating-gate pipe in every array storage unit is connected and forms m bar bit lines, floats in each row and column memory element
The source electrode of bank tube is connected and forms a source.
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