CN106575676B - Solar battery with interdigital back contacts - Google Patents

Abstract

A solar cell using interdigital back contacts is provided. The solar cell may include a crystalline silicon base layer and an electron collector region on the backside of the base layer. The electron collector region may include a first conductive oxide material electrically coupled to the base layer. The solar cell may also include a hole collector region on the backside of the base layer. The hole collector region may include a second conductive oxide material electrically coupled to the base layer. The electron collector region and the hole collector region may form an interdigitated pattern. Furthermore, the first conductive oxide material and the second conductive oxide material have different work functions.

Description

Solar cells with interdigitated back contacts

CROSS-REFERENCE TO OTHER APPLICATIONS

This application claims the benefit of US Provisional Application No. 62/025,924 (Attorney Docket No. P76-1PUS), filed July 17, 2014, the disclosure of which is incorporated herein in its entirety.

technical field

This application relates to solar cell structure and fabrication, including the design of solar cells using tunnel oxide junctions and interdigital back contacts, and fabrication processes for such solar cells.

definition

A "solar cell" or "battery" is a photovoltaic structure capable of converting light into electricity. Batteries can be of any size and shape, and can be produced from a variety of materials. For example, a solar cell may be a photovoltaic structure fabricated on a silicon wafer or one or more thin films on a substrate material (eg, glass, plastic, or any other material capable of supporting a photovoltaic structure), or a combination thereof.

A "solar cell tape," "photovoltaic tape," or "tape" is a portion or segment of a photovoltaic structure, such as a solar cell. Solar cells can be divided into multiple bands. Bands can have any shape and any size. The width and length of the belts can be the same or different from each other. Multiple bands may be formed by further dividing previously divided bands.

A "cascade" is a physical arrangement of solar cells or ribbons that are electrically coupled via electrodes on or near their edges. There are many ways of physically connecting adjacent photovoltaic structures. One way is to physically overlap them at or near the edges of adjacent structures (eg, one edge on the anode side and another edge on the cathode side). This overlapping process is sometimes referred to as "lapping". Two or more cascaded photovoltaic structures or strips may be referred to as "cascade strings", or more simply strings.

"Fingerline", "digital electrode" and "finger" refer to the elongated, conductive (eg, metallic) electrodes of a photovoltaic structure for collecting charge carriers.

"Bus bar," "bus," or "bus electrode" refers to an elongated, conductive (eg, metallic) electrode of a photovoltaic structure for collecting current collected by two or more finger wires. Bus bars tend to be wider than finger lines and can be deposited or otherwise arranged anywhere on or within a photovoltaic structure. A single photovoltaic structure may have one or more bus bars.

A "photovoltaic structure" may refer to a solar cell, segment or solar cell ribbon. Photovoltaic structures are not limited to devices fabricated by a particular method. For example, the photovoltaic structure may be a crystalline silicon based solar cell, a thin film solar cell, an amorphous silicon based solar cell, a polycrystalline silicon based solar cell, or a strip thereof.

The "front side" of a photovoltaic structure refers to the side of the structure that is typically used to absorb direct sunlight.

The "back side" of a photovoltaic structure refers to the side of the structure that typically faces away from direct line of sight.

"Emitter" refers to the portion of the photovoltaic structure that collects carriers (holes or electrons). If such an emitter has the same conductivity type as that of the base layer, the emitter can also be called a surface field (SF) layer, which can be a back surface field (BSF) layer or a front surface field (FSF) Floor. Generally, the p-emitter collects holes generated by the solar cell (ie, it "emits" p-type carriers or holes to an external circuit), while the n-emitter collects electrons (ie, it "emits" to the external circuit n-type carriers or electrons). Therefore, the p-emitter may also be referred to as the hole collector, and the n-emitter may also be referred to as the electron collector.

Background technique

Advances in photovoltaic technology used to make solar panels have helped solar gain a lot of traction among those looking to reduce their carbon footprint and lower their monthly energy costs. The energy conversion efficiency of photovoltaic structures has always been the focus of solar technology development. The latest photovoltaic structural designs have produced solar cells with efficiencies of 20% or higher, but the quest for more efficient devices continues.

Figure 1 shows an exemplary silicon heterojunction (SHJ) solar cell (prior art). SHJ solar cell 100 may include front gate electrode 102 , heavily doped amorphous silicon (a-Si) emitter layer 104 , intrinsic a-Si layer 106 , crystalline Si (c-Si) substrate 108 and back gate electrode 110 . Arrows in Figure 1 indicate directly incident gaze. Because there is an inherent bandgap shift between the a-Si layer 106 and the c-Si layer 108, the a-Si layer 106 can be used to reduce the surface recombination velocity by creating a barrier to minority carriers. The intrinsic a-Si layer 106 can also passivate the surface of the c-Si layer 108 by repairing existing Si dangling bonds. Furthermore, the thickness of the heavily doped a-Si emitter layer 104 can be much thinner compared to the thickness of the emitter layer of a homojunction solar cell. Therefore, SHJ solar cells can be utilized with higher open circuit voltage (V _oc ) and larger short circuit current (J _sc ) to provide higher efficiency. However, the efficiency of such solar cells is limited by the amount of light shielding caused by the front-side electrode 102 . One way to address this limitation is to have both p-type and n-type electrodes on the backside of the photovoltaic structure. Nonetheless, this configuration requires complex fabrication steps and prevents the solar cell from absorbing light from the backside.

SUMMARY OF THE INVENTION

One embodiment of the present invention provides a solar cell using interdigital back contacts. The solar cell may include a crystalline silicon base layer and an electron collector region on the backside of the base layer. The electron collector region may include a first conductive oxide material electrically coupled to the base layer. The solar cell may also include a hole collector region on the backside of the base layer. The hole collector region may include a second conductive oxide material electrically coupled to the base layer. The electron collector region and the hole collector region may form an interdigitated pattern. Furthermore, the first conductive oxide material and the second conductive oxide material have different work functions.

In a variation of this embodiment, the solar cell may comprise a quantum tunneling barrier layer between the base layer and the electron collector region.

In another embodiment, the solar cell may include an intrinsic amorphous silicon layer between the quantum tunneling barrier layer and the electron collector region.

In a variation of this embodiment, the electron collector region or the hole collector region does not contain doped amorphous silicon.

In a variation of this embodiment, at least one of the first conductive oxide material and the second conductive oxide material is transparent.

In a variant of this embodiment, the base layer may be doped with a p-type dopant. The first conductive oxide material may have a work function less than or equal to 4.2 eV.

In another variation, the first conductive oxide material comprises at least one material selected from the group consisting of aluminum doped zinc oxide, tungsten doped indium oxide, tin doped indium oxide, fluorine doped tin oxide, zinc doped oxide Indium and indium oxide doped with zinc and tungsten.

In a variant of this embodiment, the base layer is doped with an n-type dopant. The first conductive oxide material may have a work function greater than or equal to 5.0 eV.

In another variation, the first conductive oxide material may comprise at least one material selected from the group consisting of tungsten doped indium oxide, tin doped indium oxide, gallium indium oxide, gallium indium tin oxide, zinc Indium oxide, zinc indium tin oxide, tungsten oxide, titanium-doped indium oxide, cerium oxide, manganese oxide, and indium oxide.

In another embodiment, the electron collector region and the hole collector region are at least partially transparent, allowing the solar cell to absorb light from the backside.

Description of drawings

Figure 1 shows an exemplary silicon heterojunction solar cell (prior art).

Figure 2 shows an exemplary double-sided tunnel junction solar cell (prior art).

3 illustrates an exemplary tunneling oxide interdigitated back contact (TIBC) solar cell according to an embodiment of the present invention.

Figure 4 shows an exemplary TIBC solar cell according to an embodiment of the present invention.

5A shows an energy band diagram between crystalline Si and a conductive oxide material according to an embodiment of the present invention.

5B shows an energy band diagram between crystalline Si and a conductive oxide material according to an embodiment of the present invention.

6A shows an energy band diagram between crystalline Si and a conductive oxide material according to an embodiment of the present invention.

6B shows an energy band diagram between crystalline Si and a conductive oxide material according to an embodiment of the present invention.

6C shows an energy band diagram between crystalline Si and a conductive oxide material according to an embodiment of the present invention.

7 shows an exemplary layout of a TIBC solar cell according to an embodiment of the present invention.

8A shows an exemplary layout of a TIBC solar cell according to an embodiment of the present invention.

8B shows an exemplary cascade of TIBC solar cell ribbons in accordance with embodiments of the present invention.

9 illustrates an exemplary fabrication process for a TIBC solar cell according to an embodiment of the present invention.

In the drawings, like reference numerals refer to the same drawing elements.

Detailed ways

The following descriptions are presented to enable any person skilled in the art to make and use the embodiments, and are provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Overview

Embodiments of the present invention solve the problem of shading of the front side electrodes on solar cells by providing tunnel junction solar cells with interdigital back contacts. A solar cell may include a lightly doped base layer, the front and back sides of which are covered with thin layers of silicon oxide serving as quantum tunneling barrier (QTB) layers. Electron collector regions and hole collector regions, often formed in finger-like shapes, form an interdigitated pattern on the backside of the solar cell. An electron collector and a hole collector can then be formed on the electron collector region and the hole collector region, respectively. These electrodes can accordingly form interdigital back contacts (IBCs) for solar cells. The electron collector region may comprise p-type doped hydrogenated a-Si or a conducting oxide (CO) with a sufficiently low work function. The hole collector region may comprise n-type doped a-Si or CO with a sufficiently high work function. Using a conductive oxide material with a properly tuned work function can obviate the need to use doped a-Si material as electron and hole collectors, respectively. Furthermore, the backside of the solar cell can be covered in whole or in part with a transparent conductive oxide (TCO) material, which allows the solar cell to operate in a bifacial mode and absorb light from both the front and back sides.

To improve passivation, a thin layer of intrinsic a-Si can be arranged between the backside QTB layer and the electron and hole collector regions. Additionally, the electrodes may be copper based and formed using electroplating, physical vapor deposition, or a combination thereof. Because all electrical connections are on the backside of the solar cell, and because the backside of the cell can now be transparent, tunnel junction solar cells with IBCs can absorb light from both the front and back sides, resulting in more high efficiency. In addition, the IBC construction can facilitate more efficient module fabrication and modules with higher encapsulation factors, since there is no longer a need to weave tabs from one side of a solar cell to the other side of an adjacent solar cell.

Tunneling oxide interdigital back contact (TIBC) solar cells

It has been shown that certain types of SHJ solar cells (i.e., tunneling junction solar cells) can provide excellent performance because a quantum tunneling barrier (QTB) layer can effectively passivate the surface of the base layer without compromising current carrying Subcollection efficiency. Tunneling junctions can be located on either or both sides of the solar cell. Figure 2 shows an exemplary double-sided tunnel junction solar cell. The double-sided tunneling junction solar cell 200 can include a base layer 202 and quantum tunneling barrier (QTB) layers 204 and 206 that overlie both sides of the base layer 202 and can passivate surface defect states. The solar cell 200 also includes a doped a-Si layer as the front side of the front surface field (FSF) layer 208, a doped a-Si layer as the back side of the emitter layer 210, a front transparent conductive oxide (TCO) layer 212 , the back TCO layer 214 , the front metal gate line 216 and the back metal gate line 218 . Note that, depending on the doping type of base layer 202, FSF layer 208 and emitter 210 may have different doping types. In general, "emitter" may also refer to a layer having a doping type opposite to that of the base layer so that majority carriers generated in the base layer can be efficiently collected. The surface field layer (on the front or back side of the base layer) may have the same doping type as the base layer to collect minority carriers generated in the base layer. For example, if base layer 202 is n-doped, emitter 210 may be p-doped, and FSF layer 208 may be n-doped. Similarly, if base layer 202 is p-doped, emitter 210 may be n-doped, and FSF layer 208 may be p-doped.

Ultrathin tunneling oxide layers (eg, QTB layers 204 and 206 ) deposited on either or both sides of the base layer can result in layers that can be less than 1×10 ¹¹ /cm due to tunneling through the quantum barrier ^A low interfacial defect density (D _it ) of 2 without a significant increase in the associated series resistance. As a result, a high-efficiency solar cell with an open circuit voltage (V _oc ) greater than 715 mV can be realized. Details of the double-sided tunneling junction solar cell 200, including the fabrication method, can be found in a paper entitled "Solar Cell with Oxide Tunneling" submitted by inventors Jiunn Benjamin Heng, Chentao Yu, Zheng Xu and Jianming Fu on November 12, 2010 Junctions", US Patent No. 8,686,283, the disclosure of which is incorporated herein by reference in its entirety.

Note that it is also possible to have an emitter layer on the front side of the solar cell and a back surface field (BSF) layer on the back side to achieve a back junction solar cell with improved performance. However, placing the emitter (ie the majority carrier collector) on the backside can have certain advantages. For example, for an n-doped base layer, placing a heavily p-doped emitter with a higher defect density on the backside can reduce the absorption of short wavelength light near the front surface of the solar cell. Furthermore, when placed on the backside, the p-doped emitter can be relatively thick to eliminate emitter depletion effects without inducing excessive short wavelength absorption. As a result of reducing carrier depletion, the open circuit voltage and fill factor of the cell can be increased. Additionally, the back junction structure may provide more flexibility to tune the work function of the p-type doped emitter to better match the work function of the back TCO material, and/or allow for a better matched back TCO material, while Not limited by the light transmission properties of the TCO material. Furthermore, because the back junction can be affected primarily by long wavelength, low energy absorption, it is less affected by high energy, excess carrier junction recombination. Details on back junction solar cells with tunnel oxides, including fabrication methods, can be found in a paper entitled "Back Junction Solar Cells," submitted by inventors Jiunn Benjamin Heng, Jianming Fu, Zheng Xu, and Zhigang Xie on August 31, 2012 Cell with Tunnel Oxide" US Patent Application No. 13/601,441 (Attorney Docket No. SCTY-P52-2NUS), the disclosure of which is incorporated herein by reference in its entirety.

Despite the many benefits provided, back junction solar cells with tunnel oxides may still exhibit certain deficiencies. For example, there is an inherent loss of current flow because the back junction structure requires longer diffusion lengths to allow excess carriers to be swept by the built-in potential at the back junction.

To further improve the performance of back junction solar cells with tunnel oxides, in some embodiments of the present invention, interdigital back contacts (IBCs) are incorporated into such back junction solar cells to form tunnel oxide interdigital backs Contact (TIBC) solar cells. IBC can eliminate the need for front side electrodes that cause shading in conventional solar cells, thereby improving solar cell performance by increasing short circuit current (I _sc ). In addition, TIBC solar cells have enhanced _Voc compared to other conventional IBC-based solar cells because the tunneling oxide layer can improve passivation on the subsequent positive and negative electrodes. In some embodiments, an intrinsic a-Si layer may be inserted between the tunneling oxide layer and the electron and hole collector layers to facilitate better passivation and separation between the electron and hole collector regions , which can lead to improved V _oc and fill factor.

Figure 3 shows an exemplary TIBC solar cell according to an embodiment of the present invention. Solar cell 300 includes base layer 302, front QTB layer 304, back QTB layer 306, anti-reflection coating (ARC) layer 308, optional intrinsic a-Si layer 310, carrier collector layer 312, and multiple electrodes, such as electrodes 318 and 320, the carrier collector layer 312 includes an electron collector (also referred to as an n-emitter) and a hole collector (also referred to as a p-emitter) that may form an interdigitated pattern, Such as n-emitter 314 and p-emitter 316 . Arrows indicate incident light.

The base layer 302 may comprise an epitaxially grown c-Si layer, or a c-Si wafer cut from an ingot obtained via a Czochralski (CZ) or floating zone (FZ) process, and lightly doped There are n-type or p-type dopants. The thickness of the base layer 302 may be between 80 and 200 μm. In some embodiments, the thickness of the base layer 302 is between 80 and 120 μm. The resistivity of the base layer 302 may be between 1 ohm-cm and 10 ohm-cm. In one embodiment, the resistivity of the base layer 302 is between 1 ohm-cm and 5 ohm-cm, and the bulk minority carrier lifetime (MCL) is at least 1 ms. In another embodiment, the base layer 302 may be graded with an n-type dopant and may include a textured surface.

The QTB layers 304 and 306 may be in direct contact with the base layer 302 and may include dielectric thin films and/or layers of low or undoped wide bandgap semiconductor material. Exemplary materials for dielectric films include, but are not limited to: silicon oxide ( _SiOx ), hydrogenated _SiOx , silicon nitride ( _SiNx ), hydrogenated _SiNx , silicon oxynitride (SiON), hydrogenated SiON, aluminum oxide (AlO _x or Al ₂ O ₃ ) and aluminum nitride (AlN _x ). Examples of wide bandgap materials include, but are not limited to, amorphous silicon (a-Si), hydrogenated a-Si, carbon-doped a-Si, and silicon carbide (SiC). In one embodiment, the back QTB layer 306 may include _SiOx , such as SiO or _SiO2 , and/or hydrogenated _SiOx . The front QTB layer 304 may include one or more of the following: intrinsic a _- Si, amorphous SiO, _SiOx , _SiNx , and _Al2O3 . _SiOx or hydrogenated _SiOx layers can be formed by using various oxidation techniques such as: immersion of the wafer in hot deionized water (DIW), low pressure radical oxidation, ozone oxygen oxidation, atomic oxygen oxidation, thermal oxidation, chemical oxidation, Steam or wet oxidation, atomic layer deposition, ozone bubbling in DIW, and plasma enhanced chemical vapor deposition (PECVD). The thickness of QTB layers 304 and 306 may be between 1 and 20 Angstroms. In one embodiment, QTB layers 304 and 306 may each comprise a _SiOx layer having a thickness between 8 and 15 Angstroms. In some embodiments, the D _it of QTB layers 304 and 306 may be less than 5×10 ¹¹ /cm ² .

An ARC layer 308 may be deposited on the front QTB layer 304 to maximize the amount of light absorbed by the solar cell 300 . In some embodiments, the ARC layer 308 may include one or more of the following: transparent conductive _oxide (TCO), _SiNx , _SiOx , and _AlxO3 .

Intrinsic a-Si layer 310 may be deposited on back QTB layer 306 . In some embodiments, the thickness of the intrinsic a-Si layer 310 may be between arrive within the range between. In another embodiment, the thickness of the intrinsic a-Si layer 310 is approximately The intrinsic a-Si layer 310 may be deposited by using a plasma enhanced chemical vapor deposition (PECVD) technique. The optional intrinsic a-Si layer 310 can further reduce minority carrier recombination.

The carrier collector layer 312 may include p-emitter and n-emitter of an interdigitated pattern (eg, interleaved, parallel fingers). More specifically, an n-emitter such as emitter 314 may include p-type doped a-Si and may be in contact with intrinsic a-Si layer 310 . In some embodiments, the n-emitter may comprise hydrogenated a-Si with a graded doping profile. If base layer 302 is n-type doped, the n-emitter may have the opposite conductivity type as base layer 302 . The p-doped a-Si layer, the intrinsic a-Si layer 310, the QTB layer 306 and the base layer 302 together form a hetero-tunneling back junction. In some embodiments, the n-emitter (having the opposite conductivity type to that of the n-doped base layer 302 ) may have a thickness between 3 and 20 nm and between 1×10 ¹⁵ /cm ³ to 5 Doping concentration between ×10 ²⁰ /cm ³ . This doped and sufficiently thick n-emitter can ensure a good ohmic contact and a large built-in potential to promote strong tunneling effects.

Similarly, a p-emitter such as emitter 316 may comprise n-type doped a-Si and be in contact with intrinsic a-Si layer 310 . In some embodiments, the p-emitter may comprise hydrogenated a-Si with a graded doping profile. If the base layer 302 is n-doped, the p-emitter has the same conductivity type as the base layer 302 . In some embodiments, the p-emitter may have a thickness between 1 and 30 nm and a doping concentration between 1×10 ¹⁵ /cm ³ and 5×10 ²⁰ /cm ³ . The interdigitated pattern may facilitate multiple p-emitter contacts to the underlying a-Si layer 310 and QTB layer 306 . The interdigitated pattern of both n and p emitters allows adjacent emitters to have opposite conductivity doping types. Forming an emitter often involves epitaxially growing doped Si on one or more patterned masks, so a carefully designed mask can ensure that a properly sized gap is maintained between emitters of opposite doping type. This prevents short circuits from forming between electrodes with opposite polarities.

Electrodes deposited on the p-type and n-type emitters, such as electrodes 318 and 320, provide electrical coupling to the emitters. As shown in Figure 3, there may be gaps between adjacent emitters of opposite doping type to ensure that the electrodes are not shorted. For example, p-type emitter 314 and n-type emitter 316 are separated by a gap 330, which ensures that electrodes 318 and 320 are sufficiently isolated from each other.

In some embodiments, a conductive oxide (CO) layer 322 may be formed between the carrier collector layer 312 and the electrode metal layer. The CO layer 322 can facilitate the formation of good ohmic contacts to the p-type and n-type emitters. In some embodiments, the CO layer 322 may include one or more transparent conductive oxide (TCO) materials. As a result, the backside of the solar cell 300 may be transparent in whole or in part in areas not covered by the electrodes. Using a TCO allows solar cell 300 to receive and absorb light incident on its backside, which in turn allows solar cell 300 to operate in a bifacial mode.

The CO layer 322 may be deposited by using one or more of the following techniques: plasma vapor deposition, thermal evaporation, ion plating, and remote plasma deposition. The metal layer can be deposited on the CO layer 322 or directly on the p-type or n-type doped a-Si. In some embodiments, the metal layer may include one or more layers of metals such as Cu, Ag, Ni, etc. Various techniques including, but not limited to, the following may be used to deposit the one or more metal layers: physical vapor deposition (PVD), screen printing, evaporation, inkjet printing, aerosol printing, patterned electroplating, or electroless plating. In one embodiment, the metal electrodes may include copper and may be formed using electroplating techniques. In another embodiment, a seed layer of copper may be deposited by using a PVD process, and bulk copper may be formed on the seed layer by using an electroplating process. More details on how to form plated metal gridlines on photovoltaic structures can be found in US Patent Application No. 13 entitled "SOLAR CELL WITH ELECTROPLATED METAL GRID" by inventors Jianming Fu, Zheng Xu, Chentao Yu and Jiunn Benjamin Heng/ 220,532, the disclosure of which is incorporated herein by reference in its entirety.

Instead of using a-Si based emitters, in some embodiments of the present invention, n or p emitters can be formed by using CO materials (which may be transparent or opaque) without using any doped a-Si Material. Figure 4 shows an exemplary TIBC solar cell according to an embodiment of the present invention. Solar cell 400 includes base layer 402 , front QTB layer 404 , back QTB layer 406 , anti-reflective coating (ARC) layer 408 , optional intrinsic a-Si layer 410 , CO layer 412 . The CO layer 412 may include a high work function CO region serving as a hole collector and a low work function CO region serving as an electron collector. These two CO regions with different work functions form an interdigitated pattern (such as a low work function CO region 414 (electron collector) and a high work function CO region 416 (hole collector)). A plurality of metal electrodes (such as metal electrodes 418 and 420 ) may be formed on CO layer 142 .

Base layer 402, front and back QTB layers 404 and 406, ARC layer 408, and intrinsic a-Si layer 410 may be associated with base layer 302, front and back QTB layers 304 and 306, ARC layer 308, and intrinsic a-Si layer, respectively. Si layer 310 is similar. However, instead of graded doped a-Si, a CO layer 412 (which may include both types of CO materials deposited in two or more steps) may be deposited on either the intrinsic a-Si layer 410 or the back QTB layer 406 (if the a-Si layer 410 is not present) and in direct contact therewith. As shown in FIG. 4, CO layer 412 includes a low work function CO region, such as CO region 414, and a high work function CO region, such as CO region 416. Both the high work function CO regions and the low work function CO regions may be interleaved in an interdigitated pattern. Metal electrodes 418 and 420 may be similar to metal electrodes 318 and 320 .

As mentioned above, in order to collect holes, a high work function CO material can be used instead of using n-doped a-Si. Ideally, the high work function CO material has an absolute value close to or greater than the value Ev (about 5.17 eV) of the valence band edge of c-Si (lightly doped or intrinsic) used in base layer 402 Work function in a small range (eg, 0.3 eV). When engaged with c-Si base layer 402, this high work function CO region, such as CO region 416, can generate a built-in electric field that can pull holes away from generating carriers (ie, both electrons and holes) ) of the base layer 402. Because the work function of the CO material is large enough, the potential difference at this interface is large enough to cause hole tunneling through the backside QTB layer 406 . If the base layer 402 is n-doped, the high work function CO layer can act as a surface field region because it attracts minority carriers (ie, holes). If the base layer 403 is p-type doped, the high work function CO layer can function as an emitter region because it attracts majority carriers (ie, holes).

Similarly, to collect electrons, a low work function CO material can be used instead of using p-type doped a-Si. Ideally, the low work function CO material has a small range (eg, 0.1 eV) whose absolute value is close to or less than the conduction band edge of the c-Si (lightly doped or intrinsic) used in base layer 402 ~0.3 eV) work function. When bonded to c-Si base layer 402 , this low work function CO region, such as CO region 414 , can generate a built-in electric field that can pull electrons away from base layer 402 . Because the work function of the CO material is small enough, the potential difference at this interface is large enough to cause electron tunneling through the backside QTB layer 406 . If the base layer 402 is n-type doped, the low work function CO layer can act as an emitter because it attracts majority carriers (ie, electrons). If the base layer 402 is p-type doped, the low work function CO layer can act as a surface field region because it attracts minority carriers (ie, electrons).

In addition, due to the passivation effect of the intrinsic a-Si layer 410, a CO film with a low interface defect density can be formed. In one embodiment, the interface defect density (D _it ) may be less than 1e ¹¹ /cm ² , which makes it possible to eliminate the Fermi level pinning effect at the CO-semiconductor interface. The Fermi level pinning effect can be caused by surface states associated with defects and will make band bending on the semiconductor side nearly impossible. As a result of Fermi level pinning, the Schottky barrier height can be insensitive to the work function of the conductor (in this case the CO material). Due to the low interfacial defect density caused by the intrinsic a-Si layer 410, the carrier transport performance can now be manipulated based on the Fermi level of the CO layer. Therefore, when the CO/intrinsic a-Si/QTB structure is in contact with the lightly doped c-Si base, the degenerate carrier distribution in the CO layer with the proper work function and low D _it makes it possible to have strong tunneling effect. According to the Wentzel-Kramers-Brillouin (WKB) approximation, the tunneling process can depend on the available carrier concentration at the initiation side (c-Si side) and the density of states at the receiving side (CO side). As explained in more detail below in conjunction with Figures 5A, 5B, 6A, 6B and 6C, depending on the different work functions of the CO material, strong tunneling can exist in two different scenarios.

In one embodiment, the CO material can be transparent, opaque, or partially transparent when using CO materials with different work functions instead of p-type and n-type doped a-Si as electron and hole collectors. In one embodiment, the high work function and low work function CO materials are transparent (ie, both are TCO materials). As a result, the solar cell can absorb light from both the front side and the back side. Such solar cells can then be used to build double-sided solar panels that can produce more energy than conventional single-sided solar panels.

Figure 5A shows a band diagram at the interface between crystalline Si and a CO material with a work function close to the Si valence band edge. In Figure 5A, the work function of the CO material is close to the c-Si valence band edge (within 0.1 eV). When the CO material is bonded to the c-Si base layer through the QTB layer, the Fermi levels of the CO material and c-Si should be aligned to maintain electrical neutrality. As a result, the energy band on the c-Si side bends upward, and a potential difference occurs between the c-Si valence bands (where the holes generated by the solar cell are located as a result of electrons in the valence band being excited to the conduction band) , the holes will migrate towards the CO region through the QTB due to the tunneling effect. Depending on the doping type of lightly doped c-Si, there may be hole accumulation (if c-Si is p-doped) or carrier inversion (if c-Si is n-doped) at the interface ), and the highest hole concentration can be close to the doping concentration in the CO material (eg, about 1×10 ²⁰ /cm ³ ). As shown in Figure 5A, there is band bending at the QTB/Si interface, pushing the Fermi level closer to the valence band edge (Ev) of c-Si. Because the band offset between c-Si and CO can be quite small, and considering thermal broadening, the tunneling effect can be strong.

5B shows a band diagram at the interface between c-Si and a CO material having a work function much larger than the c-Si valence band edge, according to an embodiment of the present invention. In Figure 5B, the work function of the CO material is much larger than the c-Si valence band edge (approximately 5.17 eV). At the QTB/Si interface, the slope of the band bending can be large enough that quantum wells for holes appear. So the lowest energy level for strongly degenerate holes on the Si side is not at the valence band edge, but at the first bound energy level, which can be 0.1 eV above the valence band edge (the circle in Figure 5B shown). Furthermore, heavy and light holes have different mass and energy states. As a result, it is relatively easy to achieve energy level alignment, which is required due to energy saving requirements for in-band tunneling of holes. On the other hand, electrons will be repelled by the barrier. Since the receiving side is within the forbidden band, there will be no tunneling of electrons.

Note that if the work function of the CO material is much smaller than the c-Si valence band edge, there may not be enough band bending and therefore not enough to tunnel through the QTB layer.

In some embodiments, high work function CO materials may include, but are not limited to: tungsten doped indium oxide (IWO), Sn doped indium oxide (ITO), GaInO (GIO), GaInSnO (GITO), ZnInO (ZIO), ZnInSnO (ZITO), WOx, _MnOx , _ITiO , InO, CeO, and combinations thereof. The work function of most CO materials can be tuned by adjusting the carrier concentration and doping. For example, ITO with 3% or 5% Sn has a work function between 5.0 and 5.3 eV. Additionally, the CO work function can be controlled by controlling the crystal orientation and surface conditions. To ensure a sufficiently low D _it , in one embodiment, a CO layer is deposited on the intrinsic a-Si layer by using a low damage deposition method. Examples of low damage deposition methods include, but are not limited to: radio frequency (RF) sputtering (RF frequency at least 13 MHz, preferably greater than 13.56 MHz), thermal evaporation, epitaxy such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) Growth, Atomic Layer Deposition (ALD), Remote Plasma Deposition and Ion Plating Deposition (IPD). In one embodiment, D _it at the interface can be less than 1×10 ¹¹ /cm ² , which ensures good surface passivation. The high work function CO layer can be heavily doped (with metal ions) with a doping concentration of at least 1×10 ¹⁹ /cm ³ . In one embodiment, the doping concentration of the high work function CO layer may be greater than 2×10 ²⁰ /cm ³ .

Details on solar cells with TCO-based hole collectors, including fabrication methods, can be found in a question submitted by inventors Zhigang Xie, Jiunn Benjamin Heng, Wei Wang, Jianming Fu, Zheng Xu on October 10, 2013 Found in US Patent Application No. 14/051,336 (Attorney Docket No. P64-1NUS) for "NOVEL HOLE COLLECTORS FOR SILICON PHOTOVOLTAIC CELLS," the disclosure of which is incorporated herein by reference in its entirety.

Similarly, to collect electrons, a low work function CO material can be used instead of using p-type doped a-Si. Ideally, the low work function CO material has an absolute value in a small range (eg, 0.3 eV) close to or less than the value Ec of the conduction band edge of c-Si (lightly doped or intrinsic) used in the base layer ) in the work function. When bonded to c-Si base layer 402, this low work function CO region, such as CO region 414, can generate a built-in electric field that can pull electrons away from base layer 402 and thus act as an electron collector (or n emitter). Similar to the mechanism in the high work function region, low D at the _interface can reduce or eliminate the Fermi level pinning effect, and the tunneling process depends on the available current carrying at the initiation side (c-Si side) subconcentration and density of states at the receiving side (CO side). Based on the difference between the CO work function and the c-Si conduction band edge, there are three different scenarios (described below) when there is strong tunneling.

Details on solar cells with TCO-based electron collectors, including fabrication methods, can be found in a paper entitled Oct. 15, 2013, by inventors Zhigang Xie, Wei Wang, Jiunn Benjamin Heng, Jianming Fu, and Zheng Xu "NOVEL ELECTRON COLLECTORS FOR SILICON PHOTOVOLTAIC CELLS," US Patent Application No. 14/054,688 (Attorney Docket No. P65-1NUS), the disclosure of which is incorporated herein by reference in its entirety.

There may be gaps between adjacent CO regions with different work functions to ensure that the electrodes are not shorted. For example, low work function CO region 414 and high work function CO region 416 may be separated by a gap to ensure electrodes 418 and 420 are not shorted. The formation of CO regions can involve PECVD on one or more patterned masks, so a carefully designed mask can ensure that properly sized gaps are maintained between CO regions with different work functions.

6A shows a band diagram at the interface between c-Si and a CO material having a work function slightly lower than the c-Si conduction band edge, according to an embodiment of the present invention. In Figure 6A, the work function of the CO material is slightly lower than the c-Si conduction band edge (within 0.1 eV). When the CO material is bonded to the c-Si base layer through the QTB layer, the Fermi levels of the CO material and c-Si should be aligned to maintain electrical neutrality. As a result, the energy band on the c-Si side bends downward and a potential difference appears between the conduction bands of c-Si (where the electrons generated by the solar cell are located), the electrons will migrate through the QTB towards the CO region due to the tunneling effect . Depending on the doping type of lightly doped c-Si, there may be electron accumulation (if c-Si is n-doped) or carrier inversion (if c-Si is p-doped) at the interface ), and the highest electron concentration can be close to the doping concentration in the CO material (eg, about 1×10 ²⁰ /cm ³ ). As shown in Figure 6A, there is band bending at the QTB/Si interface, pushing the Fermi level closer to the conduction band edge (Ec) of c-Si. Because the energy band offset between Si and TCO can be quite small, and considering thermal broadening, the tunneling effect can be strong.

6B shows a band diagram at the interface between c-Si and a CO material having a much smaller work function than the c-Si conduction band edge, according to an embodiment of the present invention. In Figure 6B, the work function of the CO material is much smaller than that of the c-Si conduction band edge. At the QTB/Si interface, the slope of the band bending can be large enough that a quantum well for electrons emerges, while the triangular-shaped quantum barrier can be only a few nanometers thick. As a result, the lowest energy level for strongly degenerate electrons on the Si side is not at the conduction band edge, but at the first bound energy level, which can be within 0.1 eV from the conduction band edge (as the point in Fig. 6B ) shown). Therefore, there may not be a significant energy level shift for in-band tunneling of electrons. On the other hand, holes can be repelled by the barrier.

6C shows a band diagram at the interface between c-Si and a CO material having a work function slightly larger than the c-Si conduction band edge, according to an embodiment of the present invention. In Figure 6C, the work function of CO material is about 0.05-0.15 eV larger than the Ec of c-Si. Electrons with energy levels starting from the conduction band edge Ec will enter the unfilled conduction band of CO from the c-Si side. Due to the potential difference, there will be fewer electrons transferred from the CO side to the c-Si side. As a result, the electron concentration at the QTB/Si interface will be less than eg 1×10 ¹⁸ /cm ³ . Therefore, there may not be sufficient band bending at the interface and passivation is compromised. To improve passivation, shallow n-type doping can be applied on the surface of the c-Si substrate. Note that in order to minimize undesired absorption of short wavelength light, the shallow doping ideally has a peak concentration of at least 1×10 ¹⁹ /cm ³ and a depth of less than or equal to 100 nm.

In one embodiment, the low work function CO material has a work function less than or equal to 4.2 eV. Examples of low work function CO materials include, but are not limited to: aluminum doped zinc oxide (AZO), tungsten doped indium oxide (IWO), Sn doped indium oxide (ITO), fluorine doped tin oxide (F:SnO ₂ ), zinc doped oxide Indium (IZO), indium oxide doped with zinc and tungsten (IZWO), and combinations thereof. Note that the work function of most CO materials can be tuned by adjusting the carrier concentration and doping. Additionally, the CO work function can be controlled by controlling the crystal orientation and surface conditions. Similar to the deposition of high work function CO materials, low work function CO materials can be deposited by using low damage deposition methods. Examples of low damage deposition methods include, but are not limited to: radio frequency (RF) sputtering, thermal evaporation, epitaxial growth such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), remote Plasma Deposition and Ion Plating Deposition (IPD). In one embodiment, D _it at the interface can be less than 1×10 ¹¹ /cm ² , which can ensure adequate surface passivation.

In some embodiments, p-type doped a-Si may be replaced with only low work function CO material or n-type doped a-Si may be replaced with only high work function CO material, instead of low work function and high work function respectively The work function CO material replaces both p-type doped and n-type doped a-Si. Furthermore, it is also possible not to include an intrinsic a-Si layer (layer 310 or 410) in the TIBC solar cell by depositing the a-Si emitter or CO emitter directly onto the backside QTB layer.

Figure 7 shows an exemplary IBC solar cell layout according to one embodiment of the present invention. In this example, the solar cell 700 has a lightly n-doped c-Si base layer with two regions on the backside: a high work function TCO region 702 (shown in a dotted pattern) that acts as a hole collector ) and a low work function TCO region 704 (shown in a cross-hatched pattern) as an electron collector. Both regions are arranged in a finger line pattern, and the fingers are interleaved, forming an interdigitated pattern. Metal electrodes such as electrodes 708 and 712 may be formed on each region, respectively. In one embodiment, the width of each electrode may be smaller than the width of the corresponding TCO finger to reduce shading. In each region (ie, the electron collector region or the hole collector region), the metal fingers are connected by bus bars, which are placed near the edges of the solar cell. Because of the transparent nature of the TCO, and because the metal electrode covers only a portion of the backside, light can pass through the backside and reach the base layer, allowing the solar cell to operate in bifacial mode.

In another embodiment, the electron collector and hole collector may be formed by using opaque CO materials with different work functions. Alternatively, the electron collector and the hole collector can be formed by using p-type doped a-Si and n-type doped a-S, respectively. These two regions can then be covered with the same transparent or opaque CO material.

Figure 8A shows another IBC solar cell layout according to an embodiment of the present invention. In this example, a conventional square or quasi-square cell 800 can be divided into three strips 802 , 804 and 806 . Each strip has an IBC configuration similar to that of solar cell 700 shown in FIG. 7 . In one embodiment, multiple such strips can be cascaded into a string, which can have the same output voltage as a conventional solar panel with square or quasi-square solar cells connected in series in a single string . Multiple cascades formed with these strips can then be connected in series and in parallel within a single board. Therefore, the total internal resistance of the entire solar panel can be significantly reduced, and the output power of the panel can be increased accordingly. More details of this cascading (also known as "lap") configuration can be found in a paper titled "HIGH EFFICIENCY SOLAR PANEL" by inventors Bobby Yang, Peter P. Nguyen, Jiunn Benjamin Heng, Anand J. Reddy, and Zheng Xu US Patent Application No. 14/563,867 (Attorney Docket No. P67-3US), the disclosure of which is incorporated herein by reference in its entirety.

8B illustrates an exemplary cascade configuration of solar cell ribbons using IBCs according to one embodiment of the present invention. In this example, three strips 802, 804 and 806 are cascaded in series along their long edges. Because the busbars of each strip are on the backside, and the busbars with opposite polarity are placed on opposite edges, the strips can be placed next to each other, and adjacent busbars from two adjoining strips have opposite polarity. For example, the positive bus bar 808 of strip 802 may be placed next to the negative bus bar 810 of strip 804 . In one embodiment, metal sheet 812 may be used to connect bus bars 808 and 810 to form a series connection between strips 802 and 804 . In one embodiment, the straps may be placed close to each other to reduce the gap between them. Other methods can also be used to connect two adjacent bus bars. For example, a conductive adhesive may be applied to the bus bars 808 and 810 to connect them.

Manufacturing method

TIBC solar cells can be fabricated using either n- or p-type doped high quality solar-grade silicon (SG-Si) wafers. 9 illustrates an exemplary process for fabricating a TIBC solar cell according to an embodiment of the present invention.

In operation 9A, an SG-Si substrate may be prepared to form a base layer 900 . The resistivity of the SG-Si substrate can be in, but not limited to, the range between 1 ohm-cm to 10 ohm-cm. In one embodiment, the resistivity of the SG-Si substrate may be between 1 ohm-cm and 6 ohm-cm. The base layer 900 may include a c-Si wafer cut from an ingot obtained using a CZ/FZ process. In some embodiments, the base layer 900 may have a thickness ranging from 80 μm to 200 μm. Fabrication operations may include a saw damage etch, which removes approximately 10-30 μm of silicon. In one embodiment, surface texturing may also be performed to produce a random pyramid-like textured surface. Subsequently, the SG-Si substrate can undergo surface cleaning. In addition, the base layer 900 may also be formed by using an epitaxy process such as MOCVD, in which a c-Si epitaxial film may be grown on a growth substrate and then removed from the growth substrate. In one embodiment, the base layer 900 may be lightly doped, with a doping concentration ranging from 5×10 ¹⁴ /cm ³ to 1×10 ¹⁶ /cm ³ .

In operation 9B, thin layers of high quality (with D _it less than 1×10 ¹¹ /cm ² ) dielectric material may be formed on the front and back surfaces of base layer 900 to form front side QTB layer 902 and Backside QTB layer 904. Various types of dielectric materials may be used to form the QTB layer, including but not limited to: silicon oxide ( _SiOx , including silicon dioxide and silicon monoxide), hydrogenated _SiOx , silicon nitride ( _SiNx ), hydrogenated SiN _x , silicon oxynitride (SiON), hydrogenated SiON, aluminum oxide (AlO _x ), and aluminum nitride (AlN _x ). In one embodiment, the backside QTB layer 904 may include _SiOx and/or hydrogenated _SiOx . Such oxide layers can be formed using various techniques including, but not limited to, immersion of the substrate in hot deionized water (DIW), low pressure radical oxidation, ozone oxygen oxidation, atomic oxygen oxidation, thermal oxidation, chemical oxidation, Steam or wet oxidation, atomic layer deposition, ozone bubbling in DIW and/or plasma enhanced chemical vapor deposition (PECVD). The thickness of the QTB layer can range from 1 to between. In some embodiments, in addition to dielectric materials, various wide bandgap semiconductor materials such as a-Si, hydrogenated a-Si, carbon-doped a-Si, and SiC can also be used to form the front QTB layer 902 . In some embodiments, the D _it of QTB layers 902 and 904 may be less than 5×10 ¹¹ /cm ² .

In operation 9C, an anti-reflective coating (ARC) layer 906 may be formed on the QTB layer 902 . In some embodiments, the ARC layer 906 may include one or more _of the following: TCO material, _SiNx , _SiOx , and _AlxO3 . The thickness of the ARC layer 906 may be about 100 nm.

In operation 9D, which may be optional, an intrinsic a-Si layer 908 may be formed on the backside QTB layer 904. This intrinsic a-Si layer 908 can improve passivation and promote isolation between the n and p emitters. In some embodiments, the thickness of the intrinsic a-Si layer 908 may vary from arrive range. In another embodiment, the thickness of the intrinsic a-Si layer 908 is approximately Intrinsic a-Si layer 908 may be formed by using plasma enhanced chemical vapor deposition (PECVD) techniques.

In operation 9E, a first emitter layer (n or p) such as emitter 910 may be deposited on the intrinsic a-Si layer 908 . This emitter layer, together with a subsequently formed second emitter layer of opposite polarity, can form an interdigitated pattern. In some embodiments, the emitter may include an a-Si layer with graded doping. The conductivity type of the emitter may be opposite to that of the base layer 900 . In another embodiment, the graded doped a-Si emitter may have a thickness between 1 and 20 nm, and the graded doped a-Si has a doping concentration of 1×10 ¹⁵ /cm ³ to 5×10 ²⁰ /cm ³ . In some embodiments, the emitter may comprise a conductive oxide (CO) material with an appropriate work function. For example, CO materials with high work function may include, but are not limited to: tungsten doped indium oxide (IWO), Sn doped indium oxide (ITO), GaInO (GIO), GaInSnO (GITO), ZnInO (ZIO), ZnInSnO (ZITO) ), WO _x , ITiO, MnO _x , InO, CeO _x and combinations thereof. Preferably, the work function of CO may be at least 5.0 eV. In another embodiment, the CO material may have a work function greater than the energy level of the c-Si valence band edge. To facilitate the interdigitated pattern, a process involving applying a mask, material deposition (which may involve PECVD or PVD) and mask removal can be used. Note that because these emitters are located on the backside of solar cell 900, they are not required to be transparent.

In operation 9F, a second emitter layer (such as emitter 912 ) having an opposite polarity may be formed on the intrinsic a-Si layer 908 . The second emitter layers are interleaved with the first emitter layers formed in operation 9E, thereby forming an interdigitated pattern. In some embodiments, the second emitter layer may include an a-Si layer with graded doping. In another embodiment, the second emitter layer may have a thickness between 1 and 30 nm, and, if graded doped a-Si is used as the second emitter layer, the graded doped a-Si The doping concentration can be between 1×10 ¹⁵ /cm ³ to 5×10 ²⁰ /cm ³ . In some embodiments, the second emitter layer may be a CO material with an appropriate work function. For example, the second emitter layer may include a low work function TCO material including but not limited to: aluminum doped zinc oxide (AZO), tungsten doped indium oxide (IWO), Sn doped indium oxide (ITO), fluorine doped tin oxide (F : SnO ₂ ), zinc-doped indium oxide (IZO), zinc- and tungsten-doped indium oxide (IZWO), and combinations thereof. In another embodiment, the low work function TCO may have a work function of less than 4.2 eV. To form an interdigitated pattern, a process involving applying a mask, material deposition, and mask removal can be used. The mask for depositing the two emitter layers can be designed in such a way that adjacent emitter regions with opposite polarities are separated by a gap. For example, emitter 910 and emitter 912 are separated by gap 930 .

In another embodiment, the emitter 910 may be deposited as a blanket blanket, and the emitter 912 may be deposited in selected areas such that the portion of the emitter 910 below the emitter 912 may become reverse doped , to actually have the same doping type as emitter 912, especially after thermal treatments that can cause dopant diffusion.

It is possible to have one type of emitter formed with doped a-Si and another type of emitter formed with CO material with the appropriate work function, and vice versa. In one example, the base layer 900 may be p-type doped, the p-emitter may be n-type doped a-Si, and the n-emitter may include a high work function CO material. In another example, the base layer 900 may be p-type doped, the p-emitter may be a low work function CO material, and the n-emitter may be p-type doped a-Si. In another example, the base layer 900 may be n-type doped, the n-emitter may be p-type doped a-Si, and the p-emitter may include a low work function CO material. In yet another example, the base layer 900 may be n-doped, the n-emitter may be a high work function CO material, and the p-emitter may be n-doped a-Si.

In operation 9G, backside electrodes, such as electrodes 914 and 916, are formed on the n and p emitter regions. The electrodes may include one or more metal layers and CO layers. If both types of emitters are made of doped a-Si, the electrodes may include a CO layer to facilitate ohmic contact. On the other hand, if the emitter is formed by using CO material, no additional CO layer will be required. In some embodiments, the metal layer may be formed using various techniques including, but not limited to, screen printing, evaporation, inkjet printing, aerosol printing, electroplating, or electroless plating. In some embodiments, the metal layer may include Cu gate lines formed using various techniques including, but not limited to: electroless plating, electroplating, sputtering, and evaporation.

The foregoing descriptions of various embodiments have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the invention to the form disclosed. Accordingly, many modifications and variations will be apparent to those skilled in the art. Additionally, the above disclosure is not intended to limit the present invention.

Claims (17)

1. a kind of solar battery, comprising:

Crystalline silicon base layer；

Intrinsic amorphous silicon layer on the first side of the crystalline silicon base layer；

Electron collector region, the electron collector region include one layer of first conductive oxide material；And

Hole collector region, the hole collector region include one layer of second conductive oxide material；

Wherein the electron collector region and the hole collector region form interdigital pattern；

Wherein the first conductive oxide material layer and the second conductive oxide material layer are directly contacted with the intrinsic amorphous silicon layer； And

Wherein first conductive oxide material and second conductive oxide material have different work functions.

2. solar battery according to claim 1, further includes: between the base layer and the intrinsic amorphous silicon layer Quantum tunneling barrier layer.

3. solar battery according to claim 1, wherein the electron collector region or the hole collector area Domain does not include the amorphous silicon of doping.

4. solar battery according to claim 1, wherein first conductive oxide material and second conduction At least one of oxide material is transparent.

5. solar battery according to claim 1 is less than or equal to wherein first conductive oxide material has The work function of 4.2eV.

6. solar battery according to claim 5, wherein first conductive oxide material includes being selected from following material Expect at least one of the group of composition material:

Al-Doped ZnO；

Tungsten-doped indium oxide；

Tin-doped indium oxide；

Fluorine-doped tin oxide；

Mix zinc indium oxide；And

Adulterate the indium oxide of zinc and tungsten.

7. solar battery according to claim 1 is greater than or equal to wherein second conductive oxide material has The work function of 5.0eV.

8. solar battery according to claim 7, wherein second conductive oxide material includes being selected from following material Expect at least one of the group of composition material:

Tungsten-doped indium oxide；

Tin-doped indium oxide；

Gallium indium oxide；

Gallium indium tin oxide；

Zinc indium oxide；

Zinc indium tin oxide；

Mix titanium indium oxide；

Cerium oxide；

Tungsten oxide；

Manganese oxide；And

Indium oxide.

9. a kind of solar battery, comprising:

Crystalline silicon base layer；

Intrinsic amorphous silicon layer on the first side of the crystalline silicon base layer；

Electron collector region；And

Hole collector region；

Wherein the electron collector region and the hole collector region form interdigital figure on the back side of the base layer Case；

Wherein the electron collector region and the hole collector region are at least partly transparent, thus described in allowing too Positive energy battery absorbs light from the back side；

Wherein the electron collector region includes one layer of first transparent conductive oxide material；

Wherein the hole collector region includes one layer of second transparent conductive oxide material；

Wherein the first transparent conductive oxide material layer and the second transparent conductive oxide material layer and the intrinsic amorphous silicon layer Directly contact；And

Wherein the first transparent conductive oxide material and the second transparent conductive oxide material have different work contents Number.

10. solar battery according to claim 9, wherein the electron collector region and the hole collector area Domain is at least partly covered by transparent conductive oxide material.

11. solar battery according to claim 9, further includes:

It is coupled to the electron collector region and partly covers the electron collector in the electron collector region；And

It is coupled to the hole collector region and partly covers the hole collector of the hole collector region.

12. solar battery according to claim 9, wherein the electron collector region includes p-type doping amorphous silicon； And

Wherein the hole collector region includes n-type doping amorphous silicon.

13. solar battery according to claim 9, further includes: the base layer and the intrinsic amorphous silicon layer it Between quantum tunneling barrier layer.

14. a kind of photovoltaic structure, comprising:

Crystalline silicon base layer；

Intrinsic amorphous silicon layer on the first side of the crystalline silicon base layer；

First transparent conductive oxide region；And

Second transparent conductive oxide region；

Wherein first transparent conductive oxide region and second transparent conductive oxide region are located at the base layer Same side on and form interdigital pattern；

Wherein first transparent conductive oxide region and second transparent conductive oxide region and the intrinsic amorphous Silicon layer directly contacts；And

Wherein first transparent conductive oxide region and second transparent conductive oxide region have different work contents Number.

15. photovoltaic structure according to claim 14, wherein first transparent conductive oxide region and described second Transparent conductive oxide region is coupled to the base layer in the case where amorphous silicon not adulterated.

16. photovoltaic structure according to claim 14, further includes:

It is coupled to first transparent conductive oxide region and partly covers first transparent conductive oxide region First electrode；And

It is coupled to second transparent conductive oxide region and partly covers second transparent conductive oxide region Second electrode.

17. photovoltaic structure according to claim 14, wherein first transparent conductive oxide region and described second Transparent conductive oxide region is coupled to the base layer via quantum tunneling barrier layer and the intrinsic amorphous silicon layer.