CN106571825A - Asynchronous clock signal generation circuit based on TSPC circuit - Google Patents

Abstract

The invention discloses an asynchronous clock signal generating circuit based on a True Single Phase Clocked (TSPC) circuit. This circuit is used for the function of generating asynchronous clock signal inside the analog-to-digital conversion chip (ADC). The circuit includes a TSPC flip-flop with a reset function, a chain of TSPC flip-flops, and other functional units. The present invention has the following beneficial effects: it provides an asynchronous clock signal generating circuit based on a true single-phase clock control circuit, overcomes the shortcoming of the existing ADC synchronous control circuit that takes a long time to convert, further improves the conversion speed of the circuit, and because it contains a reset The functional TSPC flip-flop eliminates the wrong output signal due to the uncertainty of nodes X and Y, and improves the reliability of the asynchronous clock signal generation circuit.

Description

Asynchronous Clock Signal Generation Circuit Based on TSPC Circuit

technical field

The invention relates to the field of an asynchronous clock signal generation circuit used inside an analog-to-digital conversion ADC chip, in particular to an asynchronous clock signal generation circuit based on a TSPC circuit.

Background technique

Circuit design can be classified into synchronous circuit and asynchronous circuit design. Synchronous circuits use clock pulses to make their subsystems operate synchronously, while asynchronous circuits do not use clock pulses for synchronization, and their subsystems use special "start" and "finish" signals to make them synchronized. Due to the following advantages of asynchronous circuits: no clock skew problem, low power consumption, average performance instead of worst-case performance, modularity, combinability, and reusability, research on asynchronous circuits has increased rapidly in recent years. Asynchronous circuits are mainly combinational logic circuits, which are used to generate read and write control signal pulses for address decoders, first-in-first-out buffers, or memories. The logic output has nothing to do with any clock signal, and the glitches generated by the decoding output can usually be monitored. of. A synchronous circuit is a circuit composed of sequential circuits (registers or various flip-flops) and combinational logic circuits, and all operations are completed under strict clock control. These sequential circuits share the same clock, and all state changes are completed on the rising or falling edge of the clock.

The successive approximation (Successive Approximation Register, SAR) analog-to-digital converter is a medium-speed analog-to-digital converter, and its biggest feature is low power consumption, and it is easy to achieve zero static power consumption. Therefore, it is a meaningful research direction to use the low power consumption characteristics of SAR ADC to improve the conversion speed of SAR ADC, thereby replacing high-speed and high-power analog-to-digital converters such as pipelined ADC. Improving the conversion speed of SAR ADC is a hot research direction of SAR ADC at present. The SAR ADC completes the analog-to-digital conversion through a step-by-step approximation method, and at least N+1 steps are required to obtain an N-bit result, of which 1 step is used for sampling and N steps are used for conversion. Each conversion step consists of three parts: control circuit delay, DAC stabilization time, and comparator resolution time. These three delays are closely related to the process. So the speed can be increased by adjusting the control circuit.

SAR ADC control circuits generally include synchronous and asynchronous. The synchronous control circuit needs an internal clock with a frequency of about (N+1) f _s , and the time consumed by each step of conversion is the same during conversion. The system clock frequency of the asynchronous control circuit is equal to the system conversion rate, and the SAR ADC automatically generates the clock required for conversion after sampling. After each step of conversion, the next step of conversion is automatically started, and the time consumed by each step of conversion is different. The time for each conversion step is related to the remaining signal (headroom). The larger the margin, the faster the comparator resolves and the faster the comparison is completed. Because the larger the margin, the faster a certain step conversion is completed, and the synchronous method can only meet the slowest situation when setting the conversion time of each step, so the asynchronous control circuit is faster than the synchronous control circuit.

Contents of the invention

The purpose of the present invention is to provide an asynchronous clock signal generation circuit based on a true single phase clock control (True Single Phase Clocked, TSPC) circuit to further improve the circuit conversion speed.

The minimum ratio of the consumption time of the synchronous control circuit to the asynchronous control circuit is:

If N is large enough, the ratio can be reduced to 0.5. It can be seen that the asynchronous control method is quite effective in improving the switching speed.

In order to realize the above-mentioned purpose of the invention, the present invention adopts the following technical solutions:

An asynchronous clock signal generating circuit based on a TSPC circuit, the asynchronous clock signal generating circuit is composed of an internal asynchronous clock circuit, a valid signal generating circuit and a clkc signal generating circuit;

The internal asynchronous clock circuit is composed of ten TSPC flip-flop circuits, wherein the input terminal of the first flip-flop of the internal asynchronous clock circuit is connected to the VDD signal, the trigger signal is connected to the valid signal output by the valid signal generating circuit, and the reset terminal Connect to the CLK signal, the output signal of the first trigger is clk1; the input terminal of the second trigger is connected to the output terminal of the first trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, the second The output signal of the trigger is clk2; the input terminal of the third trigger is connected to the output terminal of the second trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal of the third trigger is clk3; The input terminal of the fourth trigger is connected to the output terminal of the third trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal of the fourth trigger is clk4; and so on, the previous stage The output is used as the input of the next stage, and the signals clk1~clk10 are sequentially obtained; the clkc signal generation circuit finally generates the internal working clock signal clkc by connecting the signal clk10, the valid signal and the CLK signal through an OR gate.

A typical TSPC flip-flop circuit consists of a first-stage inverter, a second-stage inverter, a third-stage inverter and a reset structure; the first-stage inverter includes two PMOS transistors M2 and M3, an NMOS Tube M1; the gate of M3 tube is connected to the gate of M1 tube to form an inverter and is used as the input terminal of data, and the gate of M2 tube is connected to the clock signal CLK as a gate for controlling data transfer from the first stage to the second stage ; The second-stage inverter includes two NMOS transistors M4 and M5, and one PMOS transistor M6; the M6 transistor is connected to the M4 transistor to access the CLK signal, and the output node X of the first-stage inverter is connected to the gate of the M5 transistor , and as the input of the second-stage inverter; the third-stage inverter includes two NMOS transistors M7 and M8, and one PMOS transistor M9; the gate of the M8 transistor is connected to the CLK signal for controlling the second-stage inverter For transmission with the third-stage inverter, the gates of the M9 transistor and the M7 transistor are connected to the Y node, and connected to the output end of the second-stage inverter.

The reset structure includes a first-stage reset circuit, the first-stage reset circuit is composed of two PMOS transistors M12 and M13, and an NMOS transistor M11, and the M11 transistor and the M12 transistor form an inverter; on the rising edge of the reset signal RES When it arrives, the M13 transistor is turned on, and the node X is pulled up to the VDD level, thereby eliminating the wrong signal caused by the uncertainty of the node X.

The reset structure also includes a second-level reset circuit, the second-level reset circuit is composed of an NMOS transistor M10, the drain of the M10 transistor is connected to the Y node, and the gate is connected to the RES signal. When the rising edge of the signal RES arrives, the M10 transistor is turned on, and the Y node is pulled to the ground level, thereby eliminating the wrong output signal due to the uncertainty of the node Y.

The valid signal generating circuit is generated by the differential signal output by the comparison result of the comparator through an OR gate circuit, and the valid signal generating circuit further includes a signal input transistor composed of M1 and M2 transistors, a PMOS transistor M3, an NMOS transistor M4, The PMOS transistor M5, wherein the signal C1 connected to the gate of the M1 transistor and the signal C2 connected to the gate of the M2 transistor are the differential signals output by the comparison of the comparator, and the drains of the M1 and M2 transistors are connected together with the source of the PMOS transistor M3 Connected as the gate input terminals of the PMOS transistor M5 and the NMOS transistor M4, the source of the M5 transistor is connected with the drain of the M4 transistor to form an output terminal of the circuit, and the valid signal is output.

The clkc signal generating circuit includes NMOS transistors M1-M3, PMOS transistors M4, M6 and NMOS transistor M5, and the NMOS transistors M1-M3 are signal input transistors; wherein the gate of the NMOS transistor M1 is connected to the signal clk10, and the gate of the NMOS transistor M2 is The gate is connected to the signal valid, the gate of the NMOS transistor M3 is connected to the signal CLK; the drains of the NMOS transistors M1-M3 are connected together with the source of the PMOS transistor M4 as the gate input of the PMOS transistor M6 and the NMOS transistor M5 terminal, the source of the PMOS transistor M6 is connected to the drain of the NMOS transistor M5 to form the output end of the circuit, and finally outputs the clkc signal.

The main working principle of this application: when CLK=0, the input inverter samples the D input of the inverter on node X. The second dynamic inverter is in the precharge state, and node Y is charged to VDD by M6. The third inverter is maintained because both M8 and M9 are off. Therefore, during the low phase of the clock, the input of the last (static) inverter maintains its original value, so the output Q is in a stable state. On the rising edge of the clock, dynamic inverters M4-M6 are evaluated. If X is high at the rising edge, then node Y discharges. The third inverter M7-M9 is turned on during the high level phase of the clock, and the value on the Y node is transferred to the output Q. During the positive phase of the clock, if the D input flips high, node X flips low. So the input must remain stable until the value at node X is transferred to Y before the rising edge of the clock. The uncertainty of points X and Y will affect the data conversion of the ADC in the next cycle, so this application adds a reset circuit at points X and Y respectively. The reset circuit consists of four MOS tubes M10-M13. The M10 tube is the reset tube of the Y node, which pulls the node to the ground potential when the rising edge of the reset signal RES arrives. M11-M13 are the reset transistors of the X node, which pull the node to the VDD point when the rising edge of the reset signal RES arrives.

Compared with the prior art, the beneficial effect of the present invention is: to provide an asynchronous clock signal generation circuit based on a true single-phase clock control circuit, to overcome the shortcoming of the existing ADC synchronous control circuit with long conversion time, and to further improve the circuit The conversion speed is high, and because the TSPC flip-flop with reset function eliminates the wrong output signal due to the uncertainty of nodes X and Y, it improves the reliability of the asynchronous clock signal generation circuit.

Description of drawings

Fig. 1 is TSPC circuit structure of the present invention;

Fig. 2 is internal clock circuit of the present invention;

Fig. 3 is the asynchronous sequence that circuit of the present invention produces;

Fig. 4 is the clkc signal generation gate circuit of the present invention;

Fig. 5 is a valid signal generating circuit;

detailed description

The drawings are for illustrative purposes only, and should not be construed as limitations on this patent; in order to better illustrate this embodiment, some parts in the drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product;

For those skilled in the art, it is understandable that some well-known structures and descriptions thereof may be omitted in the drawings. The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

As shown in Figure 1, it is a typical TSPC flip-flop circuit. Including the first-stage inverter, the second-stage inverter, the third-stage inverter and the reset structure, the specific structure is as follows:

The first-stage inverter includes two PMOS transistors M2 and M3, and one NMOS transistor M1; wherein the gate of the M3 transistor is connected to the gate of the M1 transistor to form an inverter and serves as an input terminal for data, and the gate of the M2 transistor is connected to the gate of the M1 transistor. The clock signal CLK is connected as a gate to control the transfer of data from the first stage to the second stage.

The second-stage inverter includes two NMOS transistors M4 and M5, and one PMOS transistor M6; the M6 transistor is connected to the M4 transistor to access the CLK signal, and the output of the first-stage inverter is connected to the gate of the M5 transistor as the second input to the stage inverter. The inverter of this stage is a dynamic inverter and is in a pre-charged state, and the node Y is charged to VDD by M6. Whether the M5 tube is turned on or not is related to the gate state of the tube.

The primary reset circuit is composed of two PMOS transistors M12 and M13 and one NMOS transistor M11. The M11 tube and the M12 tube form an inverter, and when the rising edge of the reset signal RES arrives, the M13 tube is turned on, and the node X is pulled up to the VDD level, thereby eliminating the erroneous signal due to the uncertainty of the node X.

The third-stage inverter includes two NMOS transistors M7 and M8, and one PMOS transistor M9; the gate of the M8 transistor is connected to the CLK signal for controlling the transmission between the second-stage inverter and the third-stage inverter. The gates of the M9 tube and the M7 tube are connected to the output end of the second-stage inverter.

The second stage reset circuit is composed of an NMOS transistor M10, the drain of the M10 transistor is connected to the Y node, and the gate is connected to the RES signal. When the rising edge of the signal RES arrives, the M10 transistor is turned on, and the Y node is pulled to the ground level, thereby eliminating the wrong output signal due to the uncertainty of the node Y.

The input inverter samples the D input of the inverter on node X when CLK=0. The second dynamic inverter is in the precharge state, and node Y is charged to VDD by M6. The third inverter is maintained because both M8 and M9 are off. Therefore, during the low phase of the clock, the input of the last (static) inverter maintains its original value, so the output Q is in a stable state. On the rising edge of the clock, dynamic inverters M4-M6 are evaluated. If X is high at the rising edge, then node Y discharges. The third inverter M7-M9 is turned on during the high level phase of the clock, and the value on the Y node is transferred to the output Q. During the positive phase of the clock, if the D input flips high, node X flips low. So the input must remain stable until the value at node X is transferred to Y before the rising edge of the clock. The uncertainty of points X and Y will affect the data conversion of the ADC in the next cycle, so this application adds a reset circuit at points X and Y respectively. The reset circuit consists of four mos tubes M10-M13. The M10 tube is the reset tube of the Y node, which pulls the node to the ground potential when the rising edge of the reset signal RES arrives. M11-M13 are the reset transistors of the X node, which pull the node to the VDD point when the rising edge of the reset signal RES arrives.

Figure 2 shows the asynchronous clock circuit inside the ADC. The circuit consists of ten flip-flops. The internal circuit structure of the flip-flops is shown in Figure 1. The input terminal of the first trigger of the circuit is connected to the VDD signal, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal is clk1. The input terminal of the second flip-flop is connected to the output terminal of the first flip-flop, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal is clk2. The input terminal of the third trigger is connected to the output terminal of the second trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal is clk3. The input terminal of the fourth trigger is connected to the output terminal of the third trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal is clk4. By analogy, the output of the previous stage is used as the input of the latter stage, and the signals clk1 ~ clk10 are obtained in turn. The signal clk10 is connected with the signal valid and the signal CLK through an OR gate to generate an internal working clock signal clkc. Signal clk1 ~ clk10 and clkc signal timing shown in Figure 3.

clkc signal generation circuit is shown in Figure 4. NMOS tubes M1-M3 are signal input tubes. The gate of the M1 tube is connected to the signal clk10, the gate of the M2 tube is connected to the signal valid, and the gate of the M3 tube is connected to the signal CLK. The drains of the M1-M3 transistors are connected together with the source of the PMOS transistor M4 as the gate input ends of the PMOS transistor M6 and the NMOS transistor M5. The source of the M6 tube is connected to the drain of the M5 tube to form the output end of the circuit, and the clkc signal is output.

The Valid signal is generated by the differential signal output by the comparison result of the comparator through an OR gate circuit. As shown in Figure 5, tubes M1 and M2 are signal input tubes. The signal C1 connected to the gate of the M1 tube and the signal C2 connected to the gate of the M2 tube are differential signals output by the comparator. The drains of the transistors M1 and M2 are connected together to the source of the PMOS transistor M3 as the gate input ends of the PMOS transistor M5 and the NMOS transistor M4. The source of the M5 tube is connected to the drain of the M4 tube to form an output terminal of the circuit, and a valid signal is output.

Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. All modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (10)

1. The asynchronous clock signal generation circuit based on the TSPC circuit is characterized in that: the asynchronous clock signal generation circuit is composed of an internal asynchronous clock circuit, a valid signal generation circuit and a clkc signal generation circuit; The internal asynchronous clock circuit is composed of ten TSPC flip-flop circuits, wherein the input terminal of the first flip-flop of the internal asynchronous clock circuit is connected to the VDD signal, the trigger signal is connected to the valid signal output by the valid signal generating circuit, and the reset terminal Connect to the CLK signal, the output signal of the first trigger is clk1; the input terminal of the second trigger is connected to the output terminal of the first trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, the second The output signal of the trigger is clk2; the input terminal of the third trigger is connected to the output terminal of the second trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal of the third trigger is clk3; The input terminal of the fourth trigger is connected to the output terminal of the third trigger, the trigger signal is connected to the valid signal, the reset terminal is connected to the CLK signal, and the output signal of the fourth trigger is clk4; and so on, the previous stage The output is used as the input of the next stage, and the signals clk1~clk10 are obtained in sequence; The clkc signal generating circuit finally generates an internal working clock signal clkc by connecting the signal clk10, the valid signal and the CLK signal through an OR gate. 2. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 1, is characterized in that: described TSPC flip-flop circuit is made up of first stage inverter, second stage inverter, the 3rd pole inverter and reset structure. 3. the asynchronous clock signal generating circuit based on TSPC circuit according to claim 2, is characterized in that: described first stage inverter comprises two PMOS transistors M2 and M3, an NMOS transistor M1; Wherein M3 transistor gate It is connected with the gate of the M1 tube to form an inverter and is used as the input terminal of the data, and the gate of the M2 tube is connected to the clock signal CLK as a gate for controlling the transfer of data from the first stage to the second stage. 4. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 2, is characterized in that: described second stage inverter comprises two NMOS tubes M4 and M5, a PMOS tube M6; M6 tube and M4 tube connected to the CLK signal, the output node X of the first-stage inverter is connected to the gate of the M5 transistor, and serves as the input of the second-stage inverter. 5. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 2, is characterized in that: described 3rd pole inverter comprises two NMOS tubes M7 and M8, a PMOS tube M9; M8 tube gate is connected The CLK signal is used to control the transfer between the second-stage inverter and the third-stage inverter. The gates of the M9 transistor and the M7 transistor are connected to the Y node and connected to the output terminal of the second-stage inverter . 6. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 2, is characterized in that: described reset structure comprises first stage reset circuit, and described first stage reset circuit is made of two PMOS transistors M12 and M13, An NMOS tube M11 is formed, and the M11 tube and the M12 tube form an inverter. 7. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 6, is characterized in that: described reset structure also comprises a second stage reset circuit, and described second stage reset circuit is made up of an NMOS tube M10, The drain of the M10 tube is connected to the Y node, and the gate is connected to the RES signal. 8. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 1, is characterized in that: described valid signal generation circuit is produced by an OR gate circuit by the output differential signal of comparator comparison result. 9. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 8, is characterized in that: described valid signal generation circuit further comprises the signal input tube that is made of M1 and M2 tube, PMOS tube M3, NMOS tube M4, The PMOS transistor M5, wherein the signal C1 connected to the gate of the M1 transistor and the signal C2 connected to the gate of the M2 transistor are the differential signals output by the comparison of the comparator, and the drains of the M1 and M2 transistors are connected together with the source of the PMOS transistor M3 Connected as the gate input terminals of the PMOS transistor M5 and the NMOS transistor M4, the source of the M5 transistor is connected with the drain of the M4 transistor to form an output terminal of the circuit, and the valid signal is output. 10. the asynchronous clock signal generation circuit based on TSPC circuit according to claim 1, is characterized in that: described clkc signal generation circuit comprises NMOS tube M1～M3, PMOS tube M4, M6 and NMOS tube M5, and described NMOS tube M1-M3 are signal input tubes; the gate of NMOS tube M1 is connected to signal clk10, the gate of NMOS tube M2 is connected to the signal valid, the gate of NMOS tube M3 is connected to signal CLK; the drains of NMOS tubes M1-M3 are connected to Together with the source of the PMOS transistor M4 connected as the gate input end of the PMOS transistor M6 and NMOS transistor M5, the source of the PMOS transistor M6 is connected with the drain of the NMOS transistor M5 to form the output end of the circuit, and finally output the clkc signal.