CN106569961B - Cache module based on memory access continuity and memory access method thereof - Google Patents
Cache module based on memory access continuity and memory access method thereof Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application discloses a cache module based on access address continuity and an access method thereof, wherein the cache module comprises: the method comprises the steps of dividing a plurality of blocks of caches with continuity as a principle, wherein the caches comprise Dcaches for caching discontinuous access data and Ccaches for caching continuous access data; the address judging and data returning unit is used for executing access behavior monitoring and address continuity judging, outputting the result to the operations of the Dcache and the Ccache and executing the data returning operation; and the interface conversion unit is used for executing the conversion from the system bus to the flash memory interface and the operations of issuing and invalidating the prefetch command of the cache. According to the application, the data required by the CPU is put in the cache in advance mainly through the continuity rule of memory access, so that the memory access speed is accelerated, and the performance of the SOC is improved.
Description
[ field of technology ]
The application relates to the technical field of integrated circuit system on a chip (SOC) architecture design, in particular to a cache module based on access address continuity and an access method thereof.
[ background Art ]
Storage walls are a significant challenge in the development of computers, which restricts the improvement of computer performance. Memory access speed is an important indicator for evaluating computer performance in SOC systems.
To address the problem of memory walls, a series of techniques have been developed, such as using a hierarchical memory system, and employing techniques such as prefetching, inference, instruction scheduling, thread scheduling, and the like. The goals of these techniques are: by utilizing the speed advantage of the cache, the CPU directly reads and writes the data in the cache, and the access to the low-speed and low-level memory is avoided to the greatest extent. However, the premise of the direct reading and writing of the cache by the CPU is that the target data must be backed up in the cache. Hierarchical memory designs are almost always employed in existing high performance computer systems.
In the performance test benchmark (test tool), stream is mainly used to test the memory performance of the CPU.
According to various factors such as hit rate, implementation complexity and speed, the replacement strategies of the cache include a random method, a first-in first-out method, a least recently used method and the like. These replacement strategies are applied in different scenarios with different emphasis.
The Cache (Cache) replacement strategy utilizes the locality rule of the program, and reduces the probability of direct access of the CPU to the low-speed memory. However, the program memory access has strong regularity. For example, from the point of view of program instructions, the instructions generated after compiling have strong continuity, large blocks of data are always continuously distributed in a storage space when being taken as an object, and the memory access becomes organically circulated due to the circulating structure.
[ application ]
The application aims to provide a cache module for accelerating access and a memory access method thereof from the perspective of continuity and regularity of CPU memory access, and effectively improves the memory access performance of the CPU. The application is realized by the following technical scheme:
the utility model provides a cache module based on access address continuity sets up on SOC system bus to flash memory's route, its characterized in that, cache module includes:
the method comprises the steps of dividing a plurality of blocks of caches with continuity as a principle, wherein the caches comprise Dcaches for caching discontinuous access data and Ccaches for caching continuous access data;
the address judging and data returning unit is used for executing access behavior monitoring and address continuity judging, outputting the result to the operations of the Dcache and the Ccache and executing the data returning operation;
and the interface conversion unit is used for executing the conversion from the system bus to the flash memory interface and the operations of issuing and invalidating the prefetch command of the cache.
As a specific technical solution, the ccche includes: the cache line structure, the data prefetching module and the cache line replacing circuit; the cache line structure comprises two parts of contents, namely a starting item and a prefetching item, wherein the starting item is the first few data of each continuous data, and the prefetching item is a temporary storage space of a continuous data prefetching part; the data prefetching module is used for prefetching the subsequent continuous addresses, and prefetched data are stored in the prefetching item; the cache line replacement circuit is used for replacing the content in the prefetched item or replacing the whole cache line.
As a specific technical solution, the address continuity includes: address self-increasing, address self-subtracting, and shifted addresses change regularly.
The memory access method of the cache module based on memory access continuity is characterized by comprising the following steps:
(1) When the access behavior is generated, the cache hit comparison is performed in the Dcache and the Ccache at the same time, if the cache hit occurs, the step (2A) is entered, otherwise, the step (2B) is entered;
(2A) Comparing the current address with the last address, judging whether the current address is continuous, outputting the result to the Dcache and the Ccache, and entering a step (2A 1) if the current address is continuous, otherwise entering a step (2A 2);
(2A1) Judging whether the data in the Ccache is valid or not, if so, returning the data by the Ccache and prefetching the data with the subsequent continuous addresses, otherwise, waiting for the return of the data by the flash memory; in the prefetching process, if a discontinuous request is received, interrupting the current prefetching;
(2A2) Returning data by the Dcache, and judging whether the Ccache disables unfilled cache lines or not;
(2B) Judging whether the addresses are continuous, if so, entering the step (2B 1), and if not, entering the step (2B 2);
(2B1) The Ccache decides whether to write the continuous access memory into the cache line according to the current replacement strategy;
(2B2) Judging whether the replacing strategy of the Dcache is met, if so, returning data from the flash memory and filling the data into the Dcache, otherwise, returning the data from the flash memory;
(3) And (3) returning the result obtained in the step (2) to a system bus.
As a specific technical scheme, under the condition of interrupting the current prefetching, the initial item of the ccche is not filled, and the replacement strategy of the ccche determines whether to disable the current cache line when the initial item is not filled.
As a specific technical solution, the current replacement policy of the ccche includes: when the prefetched item of the cache line is not filled, whether the cache line is replaced by the Ccache or not; when the Ccache is full, how to replace a new cache line; how to look at subsets in the continuous data.
The application has the beneficial effects that: compared with a slow memory, the cache structure can effectively accelerate the memory access speed; whatever CPU architecture, this cache architecture can be conveniently applied to various SOCs; for most programs, the access memory contains a large number of repeated continuous or regular accesses, and the acceleration effect of the application on the continuous access memory is stronger; all continuous data are not required to be stored in the cache, and only the first few continuous data are required to be stored, so that the size of the cache is reduced, and the circuit cost is reduced.
[ description of the drawings ]
Fig. 1 is a block diagram of a bus system and a memory of an SOC according to an embodiment of the present application.
FIG. 2 is a cache line structure diagram of a Ccache in a cache module according to an embodiment of the present application.
FIG. 3 is a memory access flow chart under the cache module structure provided by the embodiment of the application.
[ detailed description ] of the application
In order to make the technical scheme and beneficial effects described in the application more clear, the following detailed description is given with reference to the accompanying drawings and the specific embodiments:
as shown in FIG. 1, a system of SOC bus system includes CPU, DMA, system bus, flash memory and cache module, the cache module is set up on the route from CPU to flash memory, the cache module includes a Dcache, a Ccache, address judging and data returning unit and interface converting unit. The Dcache is used for caching discontinuous access data, the Ccache is used for caching continuous data, and the continuity in the Ccache is a specific identifiable sequence, such as address self-increasing, self-subtracting, shifting and the like.
It is assumed that in the above-described circuit, the access time of the flash memory is 3 clock cycles, and it is impossible to streamline. As shown in FIG. 2, the number of initial entries in each cache line of the Ccache is 3, and the number of prefetch entries is 3.
As shown in FIG. 3, when the memory access behavior is generated, the address judging and data returning unit compares the current address with the last address, judges whether the current address is continuous or not, and outputs the result to the Dcache and the Ccache. If the current address is sent to the Dcache and the Ccache, hit data is returned if the current address hits in the Dcache, and if the current address hits in the Ccache, hit data is returned, and the Ccache performs prefetching at the same time of the hit of the Ccache, namely, the 3 rd continuous address prefetching is performed.
Otherwise, under the condition that all caches do not hit, if the caches are discontinuous, the Dcache replaces the cache line according to the current replacement strategy, and the access result is needed to be taken out from the flash memory. If so, the Ccache decides whether to write the continuous access into the cache line according to the current replacement strategy. At the same time as the Ccache hits, the Ccache will prefetch. During the prefetching process, if a discontinuous request is received, the current prefetching is interrupted.
Under the condition of interrupt prefetching, the initial item of the Ccache is not filled, and the replacement strategy of the Ccache determines whether the current cache line is disabled when the initial item is not filled. Each cache item has a corresponding enabling mark, and the cache items which are not filled or disabled have corresponding marks. These flags control the hit and prefetch of the Ccache.
The current replacement strategy of the Ccache comprises the following steps: when the prefetched item of the cache line is not filled, whether the cache line is replaced by the Ccache or not; when the Ccache is full, how to replace a new cache line can adopt common strategies such as LRU, FIFO, random and the like; how to look at the subsets in the continuous data, if the subsets contain the same initial items, the subsets can not be used as new continuous data, because the prefetching mechanism of the Ccache ensures that the access performance of the subsets is not affected.
According to the application, the data required by the CPU is put in the cache in advance mainly through the continuity rule of memory access, so that the memory access speed is accelerated, and the performance of the SOC is improved.
The above embodiments are only for fully disclosing the present application, but not limiting the present application, and all the equivalent technical features that can be obtained without creative work according to the innovative gist of the present application are replaced and increased or reduced, which shall fall within the scope of the present disclosure.
Claims (6)
1. The utility model provides a cache module based on access address continuity sets up on SOC system bus to flash memory's route, its characterized in that, cache module includes:
the method comprises the steps of dividing a plurality of blocks of caches with continuity as a principle, wherein the caches comprise Dcaches for caching discontinuous access data and Ccaches for caching continuous access data;
the address judging and data returning unit is used for executing access behavior monitoring and address continuity judging, outputting the result to the operations of the Dcache and the Ccache and executing the data returning operation; the address judging and data returning unit compares the current address with the last address, judges whether the current address is continuous and outputs the result to the Dcache and the Ccache, if the Dcache hits, hit data is returned, if the Dcache hits, the Ccache returns hit data, and when the Ccache hits, the Ccache can prefetch the data of the subsequent continuous address;
and the interface conversion unit is used for executing the conversion from the system bus to the flash memory interface and the operations of issuing and invalidating the prefetch command of the cache.
2. The memory address continuity based cache module of claim 1, wherein the ccche comprises: the cache line structure, the data prefetching module and the cache line replacing circuit; the cache line structure comprises two parts of contents, namely a starting item and a prefetching item, wherein the starting item is the first few data of each continuous data, and the prefetching item is a temporary storage space of a continuous data prefetching part; the data prefetching module is used for prefetching the subsequent continuous addresses, and prefetched data are stored in the prefetching item; the cache line replacement circuit is used for replacing the content in the prefetched item or replacing the whole cache line.
3. The cache module based on address continuity of claim 1, wherein the address continuity comprises: address self-increasing, address self-subtracting, and shifted addresses change regularly.
4. A memory access method of the cache module based on memory access continuity as recited in claim 3, comprising:
(1) When the access behavior is generated, the cache performs hit comparison in the Dcache and the Ccache at the same time, if the cache hits, the step (2A) is entered, and if not, the step (2B) is entered;
(2A) Comparing the current address with the last address, judging whether the current address is continuous, outputting the result to the Dcache and the Ccache, and entering a step (2A 1) if the current address is continuous, otherwise entering a step (2A 2);
(2A1) Judging whether the data in the Ccache is valid or not, if so, returning the data by the Ccache and prefetching the data with the subsequent continuous addresses, otherwise, waiting for the return of the data by the flash memory; in the prefetching process, if a discontinuous request is received, interrupting the current prefetching;
(2A2) Returning data by the Dcache, and judging whether the Ccache disables unfilled cache lines or not;
(2B) Judging whether the addresses are continuous, if so, entering the step (2B 1), and if not, entering the step (2B 2);
(2B1) The Ccache decides whether to write the continuous access memory into the cache line according to the current replacement strategy;
(2B2) Judging whether the replacing strategy of the Dcache is met, if so, returning data from the flash memory and filling the data into the Dcache, otherwise, returning the data from the flash memory;
(3) And (3) returning the result obtained in the step (2) to a system bus.
5. The memory access method according to claim 4, wherein under the condition of interrupting the current prefetch, a starting item of the Ccache is not filled, and a replacement policy of the Ccache determines whether to disable the current cache line when the starting item is not filled.
6. The memory access method according to claim 4 or 5, wherein the current replacement policy of the cca comprises: when the prefetched item of the cache line is not filled, whether the cache line is replaced by the Ccache or not; when the Ccache is full, how to replace a new cache line; how to look at subsets in the continuous data.
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| CN112256599B (en) * | 2019-07-22 | 2024-11-15 | 华为技术有限公司 | A data pre-fetching method, device and storage device |
| WO2021184141A1 (en) * | 2020-03-15 | 2021-09-23 | Micron Technology, Inc. | Pre-load techniques for improved sequential read |
| CN117971501B (en) * | 2024-03-28 | 2024-07-09 | 北京壁仞科技开发有限公司 | Data access method, device, storage medium and program product |
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| JPH08137754A (en) * | 1994-11-10 | 1996-05-31 | Fuji Xerox Co Ltd | Disk cache device |
| CN1652091A (en) * | 2004-02-07 | 2005-08-10 | 华为技术有限公司 | Data preacquring method for use in data storage system |
| US7069388B1 (en) * | 2003-07-10 | 2006-06-27 | Analog Devices, Inc. | Cache memory data replacement strategy |
| CN101266576A (en) * | 2008-05-15 | 2008-09-17 | 中国人民解放军国防科学技术大学 | A Data Flow Oriented Cache Management Method |
| CN105094686A (en) * | 2014-05-09 | 2015-11-25 | 华为技术有限公司 | Data caching method, cache and computer system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2008225914A (en) * | 2007-03-13 | 2008-09-25 | Fujitsu Ltd | Prefetch control device, storage system, and prefetch control method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08137754A (en) * | 1994-11-10 | 1996-05-31 | Fuji Xerox Co Ltd | Disk cache device |
| US7069388B1 (en) * | 2003-07-10 | 2006-06-27 | Analog Devices, Inc. | Cache memory data replacement strategy |
| CN1652091A (en) * | 2004-02-07 | 2005-08-10 | 华为技术有限公司 | Data preacquring method for use in data storage system |
| CN101266576A (en) * | 2008-05-15 | 2008-09-17 | 中国人民解放军国防科学技术大学 | A Data Flow Oriented Cache Management Method |
| CN105094686A (en) * | 2014-05-09 | 2015-11-25 | 华为技术有限公司 | Data caching method, cache and computer system |
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