CN106559604B - A realization method of dual video processor synchronous imaging - Google Patents

Abstract

The invention belongs to space remote sensor electronic system technology fields, are related to a kind of method of two video processor synchronous imagings.The present invention had both solved requirement of the image co-registration to video processor while imaging, which realizes two equipment synchronous workings by mutually sending out master clock and line synchronising signal between two equipment.Solve traditional design again sends synchronous imaging signal to two video processors by an other signal processor, thus the method that two video processors of control work at the same time.The present invention reduces a stand-alone devices, to reduce the scale and cost of system.

Description

A kind of implementation method of double video processor synchronous imagings

Technical field

The invention belongs to space remote sensor technical fields, are related to a kind of realization side of dual stage video processor synchronous imaging Method.

Background technique

With the rapid development of space remote sensor electronic technology, weight and stand-alone device quantity to remote sensor systems It is required that be increasingly stringenter, meanwhile, the requirement that the image co-registration of later period different spectral coverage works to space remote sensor electronic system is also got over Come higher.Space remote sensor generallys use to realize that two video processors can be imaged simultaneously by other one at present Signal processor sends synchronous imaging signal to two video processors, so that two video processors of control work at the same time, reaches To the purpose of imaging simultaneously.The drawbacks of design, is so that Space Vehicle System is not concise enough, sets so that system increases one It is standby, to increase scale and cost of system etc..

Summary of the invention

The purpose of the present invention is to solve the synchronizations that image when remote sensing image fusion is stringent, provide a kind of dual stage video The implementation method of processor synchronous imaging, by mutually mutually sending out master clock signal between two video processors, to reach two The purpose that platform video processor is imaged simultaneously.

The technology of the present invention solution: a kind of implementation method of two video processor synchronous imagings, two video processing Device uses master clock and line synchronising signal automatic synchronization interface, realizes the automatic synchronization imaging of two video processors；Two views Frequency processor possesses the clock source of oneself respectively, and master clock signal is sent to counterpart device respectively after power-up, automatic by master clock Synchronous Principle selection uses master clock signal.

In order to increase the anti-interference between reliability and video processor, instructed using each video processor internal switch The on-off of controller parallel connection relay controls whether the clock source of video processor generates.

The master clock and line synchronising signal automatic synchronization interface realize that process is as follows:

Multiple selector is used inside (1) two video processor, is set for selecting using local clock source or other side Standby clock source；

(2) if video processor interior design watchdog reset signal there is clock selecting mistake can be to circuit It is resetted；

Using difference shielded cable between (3) two video processors, reduce the noise on cable.

The master clock automatic synchronization principle is accomplished by

(1) equipment being first powered on preferentially detects the master clock signal of other side's transmission during electrification reset；

(2) other side's master clock signal is selected if other side's interface has master clock signal, if other side's interface is not main Clock signal, the then master clock signal for selecting oneself to generate；

(3) whether other side's interface master clock signal is effectively only powering on initial state inspection once, if other side is invalid, when defaulting Progress other side's master clock is also had continuous effect property inspection if other side effectively goes out using outside other side's master clock using local master clock by clock It surveys, is interrupted once generating master clock due to counterpart device power-off, video processor can restore oneself after resetting automatically Local master clock signal.

The advantages of the present invention over the prior art are that:

(1) present invention solves the requirement of two video processors while imaging, efficiently solves image co-registration to simultaneously The strict demand of imaging；

(2) design realizes two merely by master clock and line synchronising signal is mutually sent out between two video processors Equipment synchronous working, does not depend on external equipment completely；

(3) the design reduces a stand-alone device, reduces the scale and cost of system.

Detailed description of the invention

Video processor master clock automatic synchronization interface circuit schematic illustration in Fig. 1 present invention；

Line synchronising signal and video processor timing relationship schematic diagram in Fig. 2 present invention.

Specific embodiment

As shown in Figure 1, a kind of implementation method of dual stage video processor synchronous imaging of the present invention is implemented as follows:

Two video processors are defined as video A and video B, are required according to different operating modes, at two videos Reason device can also be worked asynchronously simultaneously with time-sharing work.Operating mode is divided into double vision frequency synchronous imaging and single video is individually imaged. Referred to as double vision frequency image formation state is imaged in video A and video B simultaneously.Independent video A imaging or individually video B imaging are referred to as single Video imaging state.

The definition of 1 master clock state of table

In order to realize that the automatic synchronization imaging function of two video processors, two video processors devise master well Clock and line synchronising signal automatic synchronization interface.

Two video processors possess the clock source of oneself respectively, and master clock signal is sent to counterpart device respectively after power-up, That is the master clock that the master clock and counterpart device that every video processor has oneself to generate at the beginning of power-up generate can choose It uses, selection abides by master clock automatic synchronization principle using which master clock signal.

Master clock automatic synchronization principle is as follows:

(1) equipment being first powered on preferentially detects the master clock signal of other side's transmission during electrification reset；

(2) other side's master clock signal is selected if other side's interface has master clock signal, if other side's interface is not main Clock signal, the then master clock signal for selecting oneself to generate；

(3) whether other side's interface master clock signal is effectively only powering on initial state inspection once, if other side is invalid, when defaulting Clock is using local master clock, if other side, which effectively in addition to using other side's master clock, will also carry out other side's master clock, continuous effect property inspection It surveys, is interrupted once generating master clock due to counterpart device power-off etc., video processor can restore oneself after resetting automatically Local master clock signal.

According to above-mentioned automatic synchronization principle, the master clock interface circuit figure of design is as shown in Figure 1, two video processors exist Identical design is used on master clock circuit interface, is all to be selected using multiple selector the master clock used, both may be used To select local clock, the clock that counterpart device also can be used works.In addition local house dog electricity is devised on circuit Road can issue reset signal, reset multidiameter option switch when breaking down when master clock signal is in selection, default Use local clock signal.The connection of two equipment is using difference shielded cable, for reducing the noise pair on cable The influence of signal.

Line synchronising signal is selected according to the selection state of master clock, if i.e. master clock counterpart device, then using pair The line synchronising signal that method, apparatus is sent is counted using the local clock of oneself and is produced if master clock uses local clock Raw line synchronising signal.

Fig. 2 gives sequential relationship when two video processors work at the same time, can be with 2 with 3 video processor A periods A video processor B is for a row cycle synchronisation is primary.That is video processor video processor A is imaged at 3 width and video It is identical to manage the time used in device video processor B 2 width of imaging.Using the failing edge of line synchronising signal, according to the work master generated Clock signal, which voluntarily counts, generates oneself row periodic signal, then capable synchronization and video processor row period schematic diagram be as indicated with 2. If using video processor A master clock when synchronous imaging, line synchronising signal is passed through certainly by video processor A internal clocking Row, which counts, to be generated.If using video processor B master clock when synchronous imaging, line synchronising signal is by video processor B Portion's clock is generated by voluntarily counting.

Claims (3)

1. a kind of implementation method of two video processor synchronous imagings, it is characterised in that: when two video processors use main Clock and line synchronising signal automatic synchronization interface realize the automatic synchronization imaging of two video processors；Two video processors point Do not possess the clock source of oneself, master clock signal is sent to counterpart device respectively after power-up, selects by master clock automatic synchronization principle It selects and uses master clock signal；

Wherein, the master clock automatic synchronization principle is accomplished by

(1) equipment being first powered on preferentially detects the master clock signal of other side's transmission during electrification reset；

(2) other side's master clock signal is selected if other side's interface has master clock signal, if other side's interface does not have master clock letter Number, then the master clock signal for selecting oneself to generate；

(3) whether other side's interface master clock signal is effectively only powering on initial state inspection once, if other side is invalid, default clock makes With local master clock, detected if other side effectively in addition to using other side's master clock, will also carry out other side's master clock continuity, once by It generates master clock in counterpart device power-off reason to interrupt, video processor can restore the local master clock of oneself automatically after resetting Signal.

2. a kind of implementation method of two video processor synchronous imagings according to claim 1, it is characterised in that: in order to Increase the anti-interference between reliability and video processor, using each video processor internal switch instruction control unit parallel connection after The on-off of electric appliance controls whether the clock source of video processor generates.

3. a kind of implementation method of two video processor synchronous imagings according to claim 1, it is characterised in that:

Multiple selector is used inside (1) two video processor, for select to use local clock source or counterpart device Clock source；

(2) if video processor interior design watchdog reset signal resets circuit there is clock selecting mistake；

Using difference shielded cable between (3) two video processors, reduce the noise on cable.