CN106558499B - Formation method of MOS transistor - Google Patents

Abstract

A kind of forming method of MOS transistor, comprising: provide semiconductor substrate, the semiconductor substrate surface has gate structure, has stress material layer in the semiconductor substrate of the gate structure two sides；The first coating is formed in the stress material layer surface, the thickness of the central area of first coating is higher than the thickness of fringe region；First coating is etched, to reduce the thickness of the first coating central area；Several layers coating is formed on first coating after etching, previous coating is performed etching before one layer of coating of every formation, until the overall thickness of the fringe region of first coating and the coating is less than the overall thickness of central area and the overall thickness of fringe region is greater than 6nm, the overall thickness of central area is less than 40nm.The forming method of the MOS transistor improves the performance of MOS transistor.

Description

Formation method of MOS transistor

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a MOS transistor.

Background technique

MOS transistors are one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and source and drain regions located in the semiconductor substrate on both sides of the gate structure. The working principle of the MOS transistor is: by applying a voltage to the gate, the current through the channel at the bottom of the gate structure is adjusted to generate a switching signal.

Generally, the material of the source and drain regions is a material with stress. In order to prevent the subsequent formation of the metal silicide layer directly on the surface of the source and drain regions and the dislocation between the contact surface with the surface of the source and drain regions, it is necessary to form a layer on the surface of the source and drain regions. overlay.

However, the performance of MOS transistors formed by the prior art is poor.

Contents of the invention

The problem solved by the present invention is to avoid the thinner total thickness of the first covering layer and the edge region of the covering layer formed on the surface of the stress material layer when the total thickness of the first covering layer and the central region of the covering layer is kept within a certain range, Improve the protection of the stress material layer, thereby improving the performance of the MOS transistor.

In order to solve the above problems, the present invention provides a method for forming a MOS transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a gate structure, and there are stress material layers in the semiconductor substrate on both sides of the gate structure ; forming a first covering layer on the surface of the stress material layer, the thickness of the central region of the first covering layer is higher than the thickness of the edge region; etching the first covering layer to reduce the central region of the first covering layer thickness; several layers of covering layers are formed on the first covering layer after etching, and before each layer of covering layer is formed, the preceding covering layer is etched until the first covering layer and the covering The total thickness of the edge regions of the layer is less than the total thickness of the central region and the total thickness of the edge regions is greater than 6 nm, and the total thickness of the central region is less than 40 nm.

Optionally, the process of etching the covering layer is a wet etching process.

Optionally, the parameters of the wet etching process are: the etching solution used is a tetramethylammonium hydroxide solution, the concentration of tetramethylammonium hydroxide is 1% to 30% by mass, and the etching temperature is 20 degrees Celsius ~50 degrees Celsius.

Optionally, the parameters of the wet etching process are as follows: the etching solution used is KOH solution, the concentration of KOH is 0.1%-40% by mass, and the etching temperature is 20°C-50°C.

Optionally, the material of the covering layer is silicon.

Optionally, the process of forming each cladding layer is a selective epitaxial growth process.

Optionally, the parameters of the selective epitaxial growth process are: the gas used is one of SiH ₄ and H ₂ Cl ₂ Si or a combination thereof, the total flow rate of the gas is 30 sccm-300 sccm, and the temperature is 550 degrees Celsius ~750 degrees Celsius, the chamber pressure is 1torr~50mtorr.

Optionally, the number of layers of the covering layer is 1 to 4 layers.

Optionally, when the MOS transistor is a P-type MOS transistor, the stress material layer is made of silicon germanium.

Optionally, when the MOS transistor is an N-type MOS transistor, the stress material layer is made of carbon silicon.

Compared with the prior art, the technical solution of the present invention has the following advantages:

Since the first covering layer is etched to reduce the thickness of the central region of the first covering layer, and then several covering layers are formed on the etched first covering layer, before each layer of covering layer is formed, the previous covering layer Layers are etched until the total thickness of the edge regions of the first cover layer and the cover layer is less than the total thickness of the central region and the total thickness of the edge regions is greater than 6 nm, and the total thickness of the central region is less than 40 nm. The total thickness of the first covering layer and the central region of the covering layer is kept within a certain range while increasing the total thickness of the first covering layer and the edge region of the covering layer. The total thickness of the first covering layer and the central area of the covering layer is kept within a certain range, so that the thickness of the first covering layer and the central area of the covering layer will not be too thick, and the metal silicide layer and stress material layer formed subsequently will not be increased. At the same time, due to the increase of the total thickness of the edge region of the first covering layer and the covering layer, the protective effect of the first covering layer and the covering layer on the stress material layer is enhanced, and the surface of the stress material layer is in the subsequent etching It will not be exposed in the process, and the stress material layer will not be damaged to reduce the stress of the stress material layer; while avoiding the need to keep the total thickness of the first covering layer and the central area of the covering layer within a certain range, the first covering The phenomenon that the total thickness of the edge region of the layer and the cover layer is too thin and the protective effect of the stress material layer is reduced, thereby improving the performance of the MOS transistor.

Further, the number of layers of the several covering layers is 1 to 4 layers, and as the number of layers of the covering layers increases, the difference between the total thickness of the edge regions of the first covering layer and the covering layers and the total thickness of the central region further decreases. Under the condition that the total thickness of the central region of the first covering layer and the covering layer remains within a certain range, the total thickness of the first covering layer and the edge region of the covering layer is further increased; at the same time, the number of layers of the covering layer will not be too large Many, reducing the manufacturing process steps and saving the manufacturing cost.

Description of drawings

1 to 4 are schematic diagrams of the formation process of MOS transistors in the prior art;

5 to 9 are schematic diagrams of the formation process of the MOS transistor in the first embodiment of the present invention;

10 and 11 are schematic diagrams of the formation process of the MOS transistor in the second embodiment of the present invention;

12 and 13 are schematic views of the formation process of the MOS transistor in the third embodiment of the present invention.

Detailed ways

As mentioned in the background, the performance of MOS transistors formed in the prior art is poor.

1 to 4 are schematic diagrams of the formation process of MOS transistors in the prior art.

Referring to FIG. 1 , a semiconductor substrate 100 is provided, the surface of the semiconductor substrate 100 has a gate structure 110 , and trenches 120 are formed in the semiconductor substrate 100 on both sides of the gate structure 110 .

The crystal orientation of the semiconductor substrate 100 is (100).

Sidewalls 111 are formed on both sides of the gate structure 110 .

Referring to FIG. 2 , a stress material layer 121 is formed within the trench 120 (see FIG. 1 ).

The stress material layer 121 is made of silicon germanium.

Referring to FIG. 3 , a covering layer 130 is formed on the surface of the stress material layer 121 .

The covering layer 130 is made of silicon.

The function of the covering layer 130 is to prevent the subsequently formed metal silicide layer from being directly formed on the surface of the stress material layer 121 and to avoid dislocation between the contact surface of the stress material layer 121 and the metal silicide layer.

Research has found that the reasons for the poor performance of the MOS transistors formed by the above method are:

In the process of forming the covering layer, the growth rate of silicon on the (100) crystal plane is much greater than that on the (111) crystal plane, so that the total thickness of the edge region of the covering layer is much smaller than that of the covering layer. The total thickness of the central region, and in order to prevent the resistance between the subsequently formed metal silicide layer and the stress material layer from being too large, it is necessary to keep the total thickness of the central region of the covering layer within a certain range, if the covering The total thickness of the central region of the layer is kept within a certain range, so that the total thickness of the peripheral region of the covering layer cannot increase with the increase of the total thickness of the central region of the covering layer, and the total thickness of the peripheral region of the covering layer is relatively thin. In the subsequent etching process, it is easy to cause etching damage to the edge region of the covering layer, exposing a part of the surface of the stress material layer (refer to FIG. 4 ), thereby causing damage to the stress material layer and reducing the stress material layer. stress, thereby degrading the performance of the MOS transistor.

On this basis, the present invention provides a method for forming a MOS transistor. After forming a first covering layer on the surface of the stress material layer and etching the first covering layer, several covering layers are formed on the surface of the first covering layer. Before forming a cover layer, the previous cover layer is etched, so that under the premise that the total thickness of the first cover layer and the central area of the cover layer is within a certain range, the first cover layer and the cover layer The total thickness of the edge region is increased, so that the protective effect of the first covering layer and the covering layer on the stress material layer is increased.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

first embodiment

5 to 9 are schematic views of the forming process of the MOS transistor in the first embodiment of the present invention.

Referring to FIG. 5 , a semiconductor substrate 200 is provided, the surface of the semiconductor substrate 200 has a gate structure 210 , and trenches 230 are formed in the semiconductor substrate 200 on both sides of the gate structure 210 .

The semiconductor substrate 200 provides a process platform for subsequent formation of MOS transistors.

The semiconductor substrate 200 can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 200 can also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide; the semiconductor substrate 200 can also be other For semiconductor materials, we will not give examples one by one here. In this embodiment, the material of the semiconductor substrate 200 is silicon.

In this embodiment, the crystal orientation of the semiconductor substrate 200 is (100). It should be noted that, in other embodiments, the crystal orientation of the semiconductor substrate 200 may be (101), (001), (010) or (110).

The gate structure 210 includes a gate dielectric layer 211 on the surface of the semiconductor substrate 200 and a gate electrode layer 212 on the surface of the gate dielectric layer 211 .

In this embodiment, the material of the gate dielectric layer 211 is silicon oxide, and the material of the gate electrode layer 212 is polysilicon. In other embodiments, the material of the gate dielectric layer 211 is a high-K dielectric material (K greater than 3.9), such as HfO ₂ , La ₂ O ₃ , HfSiON, HfAlO ₂ , SiO ₂ , ZrO ₂ , Al ₂ O ₃ , HfO ₂ , HfSiO ₄ , La ₂ O ₃ , HfSiON or HfAlO ₂ , the material of the gate electrode layer 212 is metal.

The method for forming the gate structure 210 is: using a deposition process to form a gate dielectric material layer (not shown) and a gate electrode material layer (not shown) covering the gate dielectric material layer on the surface of the semiconductor substrate 200; A patterned mask layer (not shown) is formed on the surface of the material layer, and the patterned mask layer defines the position of the gate structure 210; using the patterned mask layer as a mask, the gate structure 210 is etched. The dielectric material layer and the gate electrode material layer until the surface of the semiconductor substrate 200 is exposed to form a gate structure 210 .

In this embodiment, sidewalls 220 are formed on the sidewall surfaces of both sides of the gate structure 210 . The functions of the sidewalls 220 are: to define the distance between the subsequently formed source and drain regions and the gate structure 210 ; and to protect the gate structure 210 . The material of the sidewall 220 is silicon nitride or silicon oxynitride.

The method for forming the sidewall 220 is: using a deposition process to form a sidewall material layer covering the semiconductor substrate 200 and the gate structure 210; using an anisotropic dry etching process to etch the sidewall material layer until the semiconductor substrate is exposed. The surface of the bottom 200 forms side walls 220 .

In this embodiment, taking the MOS transistor as a P-type MOS transistor as an example, the cross-sectional shape of the trench 230 is sigma-shaped, and the sigma-shaped trench 230 is beneficial to the stress material layer 231 filled in the trench 230. The stress is released into the channel.

The method for forming the trench 230 is: forming a mask material layer covering the gate structure 210, the sidewall 220 and the semiconductor substrate 200; patterning the mask material layer to form a patterned mask layer, the The patterned mask layer defines the position of the trench 230; using the patterned mask layer as a mask, the semiconductor substrate 200 is etched by a dry etching process to form sidewalls and grooves in the semiconductor substrate 200. An opening (not shown) with a vertical bottom; the opening is wet-etched until a sigma-shaped trench 230 is formed in the semiconductor substrate 200 .

The material of the patterned mask layer is silicon nitride or silicon oxynitride. After the trench 230 is formed, the patterned mask layer is not removed, and the stress material layer, the first covering layer and the first covering layer are subsequently formed. In the process of several covering layers on the surface of a covering layer, the patterned mask layer is used to cover the top surface of the semiconductor substrate 200 and the surface of the gate structure 210, preventing the subsequent stress material layer, the first covering layer and the Several capping layers of the capping layer surface are grown on the top surface of the semiconductor substrate 200 and the surface of the gate structure 210 .

In other embodiments, the cross-sectional shape of the groove 230 may be bowl-shaped or square.

Referring to FIG. 6 , a stress material layer 231 is formed in the trench 230 (see FIG. 5 ).

When the MOS transistor is a P-type MOS transistor, the stress material layer 231 is made of silicon germanium. When the MOS transistor is an N-type MOS transistor, the stress material layer 231 is made of carbon silicon. In this embodiment, the MOS transistor is a P-type MOS transistor, and the material of the stress material layer 231 is silicon germanium.

The stress material layer 231 is grown in the trench 230 by an epitaxial growth process.

In this embodiment, the stress material layer 231 is a single-layer structure; in other embodiments, the stress material layer 231 is a laminated structure, specifically, the stress material layer 231 includes a first stress material layer (not shown shown) and a second stress material layer (not shown) located on the surface of the first stress material layer. For PMOS transistors, the atomic percentage concentration of germanium in the second stress material layer is greater than the atomic percentage concentration of germanium in the first stress material layer; for NMOS transistors, the atomic number of carbon in the second stress material layer The percent concentration is greater than the atomic percent concentration of carbon in the first stress material layer.

Referring to FIG. 7 , a first covering layer 240 is formed on the surface of the stress material layer 231 .

The material of the first covering layer 240 is silicon or silicon germanium, which is used to prevent the subsequently formed metal silicide layer from being directly formed on the surface of the stress material layer 231 to cause dislocation of the contact surface between the stress material layer 231 and the metal silicide layer.

When the material of the first covering layer 240 is silicon germanium, the atomic percentage of germanium in the first covering layer 240 is greater than 0% and less than 10%. In this embodiment, the material of the first covering layer 240 is silicon.

The method of forming the first covering layer 240 is a deposition process, such as plasma chemical vapor deposition process, atomic layer deposition process or selective epitaxial growth process.

In this embodiment, the method for forming the first cladding layer 240 is a selective epitaxial growth process, and the specific process parameters are: the gas used is one of SiH ₄ and H ₂ Cl ₂ Si or a combination thereof, and the The total gas flow is 30sccm-300sccm, the temperature is 550-750 degrees Celsius, and the chamber pressure is 1torr-50mtorr.

The first covering layer 240 has an edge area and a central area. The edge area of the first covering layer 240 refers to the area close to the top of the sidewall of the trench 230. The central area of the first covering layer 240 refers to all but the first covering layer 240. The part of the edge area of the first covering layer 240 , the central area of the first covering layer 240 is thicker than the edge area of the first covering layer 240 . It should be noted that the definition of the central area and the edge area is applicable to each covering layer formed subsequently, and will not be described in detail.

In the process of forming the first cladding layer 240, the growth rate of silicon on the (100) crystal plane is much greater than that on the (111) crystal plane, so that the thickness of the edge region of the first cladding layer 240 is much smaller than the The thickness of the central area of the first covering layer 240, if the subsequent etching process, especially the dry etching process, is directly performed on the surface of the first covering layer 240, it is easy to cause etching damage to the edge area of the first covering layer 240, Part of the surface of the stress material layer 231 is exposed, thereby causing damage to the stress material layer 231 and reducing the stress in the stress material layer 231 .

The thickness of the central region of the first covering layer 240 is 15nm-30nm.

Referring to FIG. 8 , the first capping layer 240 is etched to reduce the thickness of the central region of the first capping layer 240 .

The process of etching the first covering layer 240 is a wet etching process. The solution of the wet etching process can be an organic alkaline solution or an inorganic alkaline solution. The etching rate of the central area of the first covering layer 240 is Greater than the etching rate of the edge region of the first cladding layer 240 .

When the solution of the wet etching process is an organic alkaline solution, the organic alkaline solution may be a tetramethylammonium hydroxide (Tetramethylammonium Hydroxide, TMAH) solution; the solution of the wet etching process is an inorganic alkaline solution When , the inorganic alkaline solution is KOH, NaOH or NH ₄ OH solution.

In this embodiment, the etching solution used for etching the first covering layer 240 is tetramethylammonium hydroxide solution; in another embodiment, the etching solution used for etching the first covering layer 240 is KOH solution.

If the concentration of the etching solution is too low, the rate of etching the first covering layer 240 is too small, which reduces the process efficiency; It will also increase the etching degree of the edge region of the first covering layer 240, and the thickness of the edge region after the etching of the first covering layer 240 is too thin. Therefore, when the etching solution is tetramethylammonium hydroxide solution, tetramethyl ammonium hydroxide solution is selected. The mass percentage concentration of ammonium hydroxide is 1%-30%. When the etching solution is KOH solution, the mass percentage concentration of KOH is selected to be 0.1%-40%.

If the etching temperature of the first covering layer 240 is too high, the etching degree of the central region of the first covering layer 240 will also increase the etching degree of the edge region of the first covering layer 240, and the first covering layer 240 will be etched. If the thickness of the rear edge region is too thin, if the etching temperature of the first covering layer 240 is too low, the etching rate of the first covering layer 240 will be reduced, and the etching efficiency will be reduced. Therefore, when the etching solution is tetramethyl When the ammonium hydroxide solution is used, the etching temperature is selected to be 20°C to 50°C, and when the etching solution is KOH solution, the etching temperature is selected to be 20°C to 50°C.

In this embodiment, the first covering layer 240 has crystal planes (110), (100) and (111), and the tetramethylammonium hydroxide solution is on the crystal planes (110), (100) and (111) A cap layer 240 has an etch rate ratio of 66:33:1. In other embodiments, the ratio of the etching rate of the tetramethylammonium hydroxide solution to the first capping layer 240 on (110), (100) and (111) crystal planes can be selected from other values.

The first covering layer 240 is etched by a wet etching process, and the etching rate along the silicon crystal planes (100) and (110) is faster than the etching rate along the silicon crystal plane (111), therefore, the The thickness of the central area of the first covering layer 240 has a smaller variation in the thickness of the edge area of the first covering layer 240 , so that the thickness difference between the central area and the edge area of the first covering layer 240 is reduced.

The thickness of the central area of the first covering layer 240 after etching is 10 nm˜20 nm.

Referring to FIG. 9 , a second covering layer 241 is formed on the surface of the etched first covering layer 240 .

After forming the second covering layer 241, the total thickness of the edge regions of the first covering layer 240 and the second covering layer 241 is greater than the first thickness and the total thickness of the central regions of the first covering layer 240 and the second covering layer 241 is smaller than the second covering layer 240 and the second covering layer 241. thickness.

The first thickness is 6 nm, and the second thickness is 40 nm.

The function of the second covering layer 241 is to prevent the subsequent formation of the metal silicide layer directly on the surface of the stress material layer 231 and cause dislocation of the contact surface between the stress material layer 231 and the metal silicide layer; The total thickness of the edge regions of the layer 240 and the second cover layer 241 .

The material of the second covering layer 241 is silicon or silicon germanium. When the material of the second covering layer 241 is silicon germanium, the atomic percentage of germanium in the second covering layer 241 is greater than 0% and less than 10%. In this embodiment, the material of the second covering layer 241 is silicon.

The thickness of the central region of the second covering layer 241 is 10nm˜20nm.

The method of forming the second covering layer 241 is a deposition process, such as plasma chemical vapor deposition process, atomic layer deposition process or selective epitaxial growth process.

In this embodiment, the method for forming the second covering layer 241 is a selective epitaxial growth process, and the specific process parameters are: the gas used is one of SiH ₄ and H ₂ Cl ₂ Si or a combination thereof, the The total gas flow is 30sccm-300sccm, the temperature is 550-750 degrees Celsius, and the chamber pressure is 1torr-50mtorr.

It should be noted that if the total thickness of the central regions of the first covering layer 240 and the second covering layer 241 is too thin, the protective effect on the stress material layer 231 will be weakened. In the subsequent etching process, especially the dry etching process, It is easy to expose the surface of the stress material layer 231, thereby causing etching damage to the stress material layer 231; if the total thickness of the central area of the first covering layer 240 and the second covering layer 241 is too thick, the metal silicide layer formed subsequently Therefore, the total thickness of the central regions of the first covering layer 240 and the second covering layer 241 needs to be kept within a certain range. In this embodiment, the total thickness of the central regions of the first covering layer 240 and the second covering layer 241 is 20 nm˜40 nm.

Since the first covering layer 240 is first etched to reduce the thickness of the central region of the first covering layer 240, then the second covering layer 241 is formed on the surface of the first covering layer 240 after etching, so that the first covering layer 240 and the second covering layer 240 Under the premise that the total thickness of the central region of the two covering layers 241 remains within a certain range, the total thickness of the edge regions of the first covering layer 240 and the second covering layer 241 increases, and the first covering layer 240 and the second covering layer 241 respond to stress The protective effect of the material layer 231 is enhanced in the edge region. In the subsequent etching process, the surface of the stress material layer 231 will not be exposed.

After the second covering layer 241 is formed, the stress material layer 231 is implanted with ions using the sidewall 220 and the gate structure 210 as a mask to form source and drain regions. For PMOS transistors, the dopant ions are P-type ions, such as B or In; for NMOS transistors, the dopant ions are N-type ions, such as P (phosphorus) or As. Then a metal silicide layer (not shown) is formed on the surface of the second covering layer 241 .

In this embodiment, a covering layer is formed on the first covering layer 240 .

second embodiment

10 to 11 are schematic views of the formation process of the MOS transistor in the second embodiment of the present invention.

The difference between the second embodiment and the first embodiment is that: on the basis of the first embodiment, the second covering layer is etched to reduce the thickness of the central area of the second covering layer, and then the etched second The surface of the covering layer forms a third covering layer. The thicknesses of the layers of the first covering layer and the second covering layer in the second embodiment are different from those of the layers of the first covering layer and the second covering layer in the first embodiment. The same parts in the second embodiment and the first embodiment will not be described in detail.

Referring to FIG. 10 , which is a schematic view based on FIG. 9 , the second covering layer 241 is etched to reduce the thickness of the central region of the second covering layer 241 .

In this embodiment, the thickness of the central region before the etching of the first covering layer 240 is 15nm-30nm, the thickness of the central region after the etching of the first covering layer 240 is 8nm-15nm, and the thickness of the central region before the etching of the second covering layer 241 is The thickness is 15nm-30nm, and the thickness of the central region after the second covering layer 241 is etched is 8nm-15nm.

The process of etching the second covering layer 241 is a wet etching process. The solution of the wet etching process may be an organic alkaline solution or an inorganic alkaline solution. The etching rate of the central area of the second covering layer 241 is greater than that of the The etching rate of the edge region of the second covering layer 241.

When the solution of the wet etching process is an organic alkaline solution, the organic alkaline solution may be a tetramethylammonium hydroxide (Tetramethylammonium Hydroxide, TMAH) solution; the solution of the wet etching process is an inorganic alkaline solution When , the inorganic alkaline solution is KOH, NaOH or NH ₄ OH solution.

In this embodiment, the etching solution used for etching the second covering layer 241 is tetramethylammonium hydroxide solution; in another embodiment, the etching solution used for etching the second covering layer 241 is KOH solution.

If the concentration of the etching solution is too low, the rate of etching the second covering layer 241 is too small, which reduces the process efficiency; if the concentration of the etching solution is too high, the etching degree of the second covering layer 241 central region increases It will also increase the etching degree of the edge region of the second covering layer 241, and the thickness of the edge region after the second covering layer 241 is etched is too thin. Therefore, when the etching solution is a tetramethylammonium hydroxide solution, select tetramethylammonium hydroxide solution. The mass percentage concentration of ammonium hydroxide is 1%-30%. When the etching solution is a KOH solution, the KOH mass percent concentration is selected to be 0.1%˜40%.

If the etching temperature of the second covering layer 241 is too high, the etching degree of the central region of the second covering layer 241 will also increase the etching degree of the edge region of the second covering layer 241, and the second covering layer 241 will be etched. If the thickness of the rear edge region is too thin, if the etching temperature of the second covering layer 241 is too low, the etching rate of the second covering layer 241 will be reduced and the etching efficiency will be reduced. Therefore, when the etching solution is tetramethyl When the ammonium hydroxide solution is used, the etching temperature is selected to be 20°C to 50°C, and when the etching solution is KOH solution, the etching temperature is selected to be 20°C to 50°C.

The second cladding layer 241 has crystal planes (110), (100) and (111), and the tetramethylammonium hydroxide solution is to (110), (100) and (111) crystal planes of the second cladding layer 241. The etch rate ratio is 66:33:1. In other embodiments, the ratio of the etching rate of the tetramethylammonium hydroxide solution to the first capping layer 240 on (110), (100) and (111) crystal planes can be selected from other values.

The second cover layer 241 is etched by a wet etching process, and the etching rate along the silicon crystal planes (100) and (110) is faster than that along the silicon crystal plane (111), therefore, the The thickness of the central area of the second covering layer 241 has a small variation in the thickness of the edge area of the second covering layer 241 .

Referring to FIG. 11 , a third covering layer 242 is formed on the surface of the etched second covering layer 241 .

After forming the third covering layer 242, the total thickness of the edge regions of the first covering layer 240, the second covering layer 241 and the third covering layer 243 is greater than the first thickness, and the first covering layer 240, the second covering layer The total thickness of the central region of the layer 241 and the third covering layer 243 is smaller than the second thickness.

The first thickness is 6 nm, and the second thickness is 40 nm.

The function of the third covering layer 242 is to prevent the subsequent formation of the metal silicide layer directly on the surface of the stress material layer 231 and cause dislocation of the contact surface between the stress material layer 231 and the metal silicide layer; The total thickness of the edge regions of the layer 240 , the second cover layer 241 and the third cover layer 242 .

The material of the third covering layer 242 is silicon, and the thickness of the central area of the third covering layer 242 is 4nm˜10nm.

The total thickness of the central regions of the first covering layer 240 , the second covering layer 241 and the third covering layer 242 is 20 nm˜40 nm.

The method for forming the third covering layer 242 is a deposition process, such as a plasma chemical vapor deposition process, an atomic layer deposition process or a selective epitaxial growth process.

In this embodiment, the method for forming the third covering layer 242 is a selective epitaxial growth process, and the specific process parameters are: the gas used is one of SiH ₄ and H ₂ Cl ₂ Si or a combination thereof, the The total gas flow is 30sccm-300sccm, the temperature is 550-750 degrees Celsius, and the chamber pressure is 1torr-50mtorr.

Since the etching reduces the thickness of the central area of the second covering layer 241, then the third covering layer 242 is formed on the surface of the etched second covering layer 241, so that the first covering layer 240, the second covering layer 241 and the third covering layer 240 Under the premise that the total thickness of the central area of the covering layer 242 maintains a certain range, the total thickness of the edge regions of the first covering layer 240, the second covering layer 241 and the third covering layer 242 is further increased, and the first covering layer 240, the second covering layer The protective effect of the layer 241 and the third covering layer 242 on the edge region of the stress material layer 231 is further enhanced.

After the third covering layer 242 is formed, the stress material layer 231 is implanted with ions using the sidewall 220 and the gate structure 210 as a mask to form source and drain regions. Then a metal silicide layer (not shown) is formed on the surface of the third covering layer 242 .

In this embodiment, two covering layers are formed on the first covering layer 240 , namely the second covering layer 241 and the third covering layer 242 .

third embodiment

12 and 13 are schematic views of the formation process of the MOS transistor in the third embodiment of the present invention.

The difference between this embodiment and the second embodiment is: on the basis of the second embodiment, the third covering layer is etched to reduce the thickness of the central area of the third covering layer, and then the third covering layer after etching The surface of the layer forms a fourth covering layer. The thicknesses of the first covering layer, the second covering layer and the third covering layer in the third embodiment are different from those of the first covering layer, the second covering layer and the third covering layer in the second embodiment. The same parts in this embodiment and the second embodiment will not be described in detail again.

Referring to FIG. 12 , which is a schematic diagram based on FIG. 11 , the third covering layer 242 is etched to reduce the thickness of the central area of the third covering layer 242 .

In this embodiment, the thickness of the central region before the etching of the first covering layer 241 is 10nm-20nm, the thickness of the central region after the etching of the first covering layer 241 is 5nm-10nm, and the thickness of the central region before the etching of the second covering layer 241 is The thickness is 10nm-20nm, the thickness of the central area after the second covering layer 241 is etched is 5nm-10nm, the thickness of the central area before the third covering layer 242 is etched is 10nm-20nm, the central area after the third covering layer 242 is etched The thickness is 5nm ~ 10nm.

The process of etching the third covering layer 242 is a wet etching process. The solution of the wet etching process may be an organic alkaline solution or an inorganic alkaline solution. The etching rate of the central area of the third covering layer 242 is greater than that of the The etch rate of the edge region of the third cladding layer 242 .

When the solution of the wet etching process is an organic alkaline solution, the organic alkaline solution may be a tetramethylammonium hydroxide (Tetramethylammonium Hydroxide, TMAH) solution; the solution of the wet etching process is an inorganic alkaline solution When , the inorganic alkaline solution is KOH, NaOH or NH ₄ OH solution.

In this embodiment, the etching solution used to etch the third covering layer 242 is a tetramethylammonium hydroxide solution; in another embodiment, the etching solution used to etch the third covering layer 242 is a KOH solution.

If the concentration of the etching solution is too low, the rate of etching the third covering layer 242 is too small, which reduces the process efficiency; It will also increase the etching degree of the edge region of the third covering layer 242, and the thickness of the edge region after the third covering layer 242 is etched is too thin. Therefore, when the etching solution is a tetramethylammonium hydroxide solution, select tetramethyl ammonium hydroxide solution. The mass percentage concentration of ammonium hydroxide is 1%-30%. When the etching solution is KOH solution, the mass percentage concentration of KOH is selected to be 0.1%-40%.

If the etching temperature of the third covering layer 242 is too high, the etching degree of the central region of the third covering layer 242 will also increase the etching degree of the edge region of the third covering layer 242, and the third covering layer 242 will be etched. If the thickness of the rear edge region is too thin, if the etching temperature of the third covering layer 242 is too low, the etching rate of the third covering layer 242 will be reduced and the etching efficiency will be reduced. Therefore, when the etching solution is tetramethyl When the ammonium hydroxide solution is used, the etching temperature is selected to be 20°C to 50°C, and when the etching solution is KOH solution, the etching temperature is selected to be 20°C to 50°C.

The third covering layer 242 has crystal planes (110), (100) and (111), and the tetramethylammonium hydroxide solution has a third covering layer on (110), (100) and (111) crystal planes. 242 has an etch rate ratio of 66:33:1. In other embodiments, the ratio of the etching rate of the tetramethylammonium hydroxide solution to the first capping layer 240 on (110), (100) and (111) crystal planes can be selected from other values.

The third covering layer 242 is etched by a wet etching process, and the etching rate along the silicon crystal planes (100) and (110) is faster than the etching rate along the silicon crystal plane (111), therefore, the The thickness of the central area of the third covering layer 242 has a smaller thickness variation than that of the edge area of the third covering layer 242 .

Referring to FIG. 13 , a fourth covering layer 243 is formed on the surface of the etched third covering layer 242 .

After forming the fourth covering layer 243, the total thickness of the central areas of the first covering layer 240, the second covering layer 241, the third covering layer 242 and the fourth covering layer 243 is 20nm-40nm. The total thickness of the second covering layer 241 , the third covering layer 242 and the fourth covering layer 243 is greater than the first thickness in the edge region and smaller than the second thickness in the central region.

The first thickness is 6 nm, and the second thickness is 40 nm.

The function of the fourth covering layer 243 is to prevent the subsequent formation of the metal silicide layer directly on the surface of the stress material layer 231 and cause dislocation of the contact surface between the stress material layer 231 and the metal silicide layer; The total thickness of the edge regions of the layer 240 , the second cover layer 241 , the third cover layer 242 and the fourth cover layer 243 .

The material of the fourth covering layer 243 is silicon, and the thickness of the central area of the fourth covering layer 243 is 5 nm˜10 nm.

The method for forming the fourth covering layer 243 is a deposition process, such as plasma chemical vapor deposition process, atomic layer deposition process or selective epitaxial growth process.

In this embodiment, the method for forming the fourth cladding layer 243 is a selective epitaxial growth process, and the specific process parameters are: the gas used is one of SiH ₄ and H ₂ Cl ₂ Si or a combination thereof, and the The total gas flow is 30sccm-300sccm, the temperature is 550-750 degrees Celsius, and the chamber pressure is 1torr-50mtorr.

Since the thickness of the central area of the third covering layer 242 is reduced by etching, the fourth covering layer 243 is formed on the surface of the third covering layer 242 after etching, so that the first covering layer 240, the second covering layer 241, the third covering layer Under the premise that the total thickness of the central area of the covering layer 242 and the fourth covering layer 243 maintains a certain range, the total thickness of the edge regions of the first covering layer 240, the second covering layer 241, the third covering layer 242 and the fourth covering layer 243 With further increase, the protective effect of the first covering layer 240 , the second covering layer 241 , the third covering layer 242 and the fourth covering layer 243 on the edge region of the stress material layer 231 is further enhanced.

After the fourth covering layer 243 is formed, the stress material layer 231 is implanted with ions using the sidewall 220 and the gate structure 210 as a mask to form source and drain regions. Then a metal silicide layer (not shown) is formed on the surface of the fourth covering layer 243 .

In this embodiment, three covering layers are formed on the first covering layer 240 , namely the second covering layer 241 , the third covering layer 242 and the fourth covering layer 243 .

It should be noted that several layers of covering layers can be formed on the surface of the first covering layer, and the previous layer of covering layer is etched before each layer of covering layer is formed, and the etching rate of the central area of the previous layer of covering layer is greater than The etching rate of the edge area of the previous layer of covering layer is until the total thickness of the first covering layer and the edge area of the covering layer is greater than the first thickness and the thickness of the first covering layer and the central area of the covering layer is smaller than the second thickness.

The edge area of the covering layer refers to the area close to the top of the sidewall of the trench, the central area of the covering layer refers to the part of the covering layer except the edge area, and the central area of the covering layer is larger than the edge area of the covering layer thick.

As the number of layers of the covering layer formed on the first covering layer increases, under the premise that the total thickness of the first covering layer and the central area of the covering layer maintains a certain range, the total thickness of the first covering layer and the edge area of the covering layer Further increase, and the difference between the total thickness of the first covering layer and the edge area of the covering layer and the total thickness of the central area decreases, and the protective effect of the first covering layer and the covering layer on the edge area of the stress material layer is further improved enhanced.

In an actual process, considering the factors of manufacturing cost and manufacturing process steps, the number of layers of the several covering layers is 1-4 layers.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. a kind of forming method of MOS transistor characterized by comprising

Semiconductor substrate is provided, the semiconductor substrate surface has gate structure, and the semiconductor of the gate structure two sides serves as a contrast There is stress material layer in bottom；

The first coating is formed in the stress material layer surface, the thickness of the central area of first coating is higher than edge The thickness in region；

First coating is etched, to reduce the thickness of the first coating central area, the first coating center after etching Domain with a thickness of 10nm~20nm；

Several layers coating is formed on first coating after etching, to previous before one layer of coating of every formation Coating performs etching, until the overall thickness of the fringe region of first coating and the coating is less than central area Overall thickness and the overall thickness of fringe region are greater than 6nm, and the overall thickness of central area is less than 40nm.

2. the forming method of MOS transistor according to claim 1, which is characterized in that the technique for etching the coating For wet-etching technique.

3. the forming method of MOS transistor according to claim 2, which is characterized in that the parameter of the wet-etching technique are as follows: For the etching solution used for tetramethyl ammonium hydroxide solution, the mass percent concentration of tetramethylammonium hydroxide is 1%~30%, Etching temperature is 20 degrees Celsius~50 degrees Celsius.

4. the forming method of MOS transistor according to claim 2, which is characterized in that the parameter of the wet-etching technique are as follows: For the etching solution used for KOH solution, the mass percent concentration of KOH is 0.1%~40%, etching temperature is 20 degrees Celsius~ 50 degrees Celsius.

5. the forming method of MOS transistor according to claim 1, which is characterized in that the material of the coating is silicon.

6. the forming method of MOS transistor according to claim 1, which is characterized in that form the work of each layer of coating Skill is selective epitaxial growth process.

7. the forming method of MOS transistor according to claim 6, which is characterized in that the selective epitaxial growth work The parameter of skill are as follows: the gas used is SiH₄And H₂Cl₂One of Si or combinations thereof, the total flow of the gas are 30sccm ~300sccm, temperature are 550 degrees Celsius~750 degrees Celsius, and chamber pressure is 1torr~50mtorr.

8. the forming method of MOS transistor according to claim 1, which is characterized in that the number of plies of the coating arrives for 1 4 layers.

9. the forming method of MOS transistor according to claim 1, which is characterized in that when the MOS transistor is p-type When MOS transistor, the material of the stress material layer is germanium silicon.

10. the forming method of MOS transistor according to claim 1, which is characterized in that when the MOS transistor is N-type When MOS transistor, the material of the stress material layer is carbon silicon.