CN106558083A - A kind of accelerated method in webp compression algorithms infra-frame prediction stage, apparatus and system - Google Patents

Abstract

The invention discloses an acceleration method, device and system for the intra-frame prediction stage of a webp compression algorithm, which are used in a data center server, including obtaining a picture in the webp format on the CPU side, dividing the picture into macroblocks of a preset size and positioning them Information; select the macroblock to be predicted as the current block, judge whether there is an encoded macroblock in the preset position around the current block according to the position information of the current block, and if so, send the current block and the encoded macroblock to the calculation Chip; the computing chip performs several preset prediction calculations according to the current block and the encoded macroblock, and obtains the prediction results and distortion rates of each prediction calculation, and sends them to the CPU; select the prediction calculation corresponding to the minimum distortion rate The result is used as the encoding of the current block; continue to select the next current block until all the macroblocks in the picture are encoded. The invention distinguishes logical judgment and vector calculation, which are respectively processed by different chips, and the speed of intra-frame prediction is fast.

Description

A method, device and system for accelerating the intra-frame prediction stage of a webp compression algorithm

technical field

The present invention relates to the technical field of picture intra-frame prediction, in particular to an acceleration method, device and system for the intra-frame prediction stage of a webp compression algorithm.

Background technique

In the era of Internet +, according to incomplete statistics, picture data accounts for about 60% of the total Internet traffic, and the transmission of massive picture data increases network delay. The WebP image format is an image compression format that uses a complex compression algorithm in exchange for a higher compression rate.

In the entire WebP compression process, intra-frame prediction is an important stage. The purpose of intra-frame prediction is to encode each macroblock obtained after the picture is divided. In this process, complex logic judgments and a large number of vector calculation operations are required due to the processing of multiple prediction modes, while the traditional CPU cannot well realize high-speed parallel calculation, and the processing speed is slow.

Therefore, how to provide a method, device and system for intra-frame prediction of pictures in webp format with fast processing speed is a problem that those skilled in the art need to solve at present.

Contents of the invention

The purpose of the present invention is to provide an acceleration method, device and system for the intra-frame prediction stage of a webp compression algorithm, which distinguishes operations such as logic judgment from vector calculation operations, which are respectively performed by a CPU and a computing chip, and the two chips are divided into tasks. Intra prediction is fast.

In order to solve the above-mentioned technical problems, the present invention provides a method for accelerating the intra-frame prediction stage of a webp compression algorithm, which is used for a data center server, including:

Step s101: Obtain a picture in webp format on the CPU side, divide the picture into macroblocks of a preset size and record the position information of each macroblock;

Step s102: Select the current macroblock to be predicted as the current block, judge whether there is an encoded macroblock in the preset position around the current block on the picture according to the position information of the current block, and if so, store the The current block and the coded macro block are sent to the calculation chip; the calculation chip performs several preset prediction calculations according to the current block and the coded macro block, and obtains the prediction calculation of each The prediction result and the distortion rate are sent to the CPU;

Step s103: Select the prediction result corresponding to the prediction calculation with the smallest distortion rate as the encoding of the current block, and repeat step s102 until all the macroblocks in the picture are encoded.

Preferably, the surrounding preset positions are specifically the left side, upper side and upper left side of the current block.

Preferably, the preset several predictive calculations specifically include:

One or a combination of horizontal prediction, vertical prediction, DC prediction and motion prediction.

In order to solve the above-mentioned technical problems, the present invention also provides an acceleration device for the intra-frame prediction stage of a webp compression algorithm, which is used for a data center server, including:

The picture acquisition module is used to obtain the picture of webp format at the CPU side, divides the picture into macroblocks of preset size and records the position information of each macroblock;

The selection module is used to select the current macroblock to be predicted as the current block, and judge whether there is an encoded macroblock in the preset position around the current block on the picture according to the position information of the current block, if there is , sending the current block and the coded macro block to the computing chip; the computing chip performs several preset prediction calculations according to the current block and the coded macro block, and obtains each of the The prediction result and the distortion rate of the prediction calculation are sent to the CPU;

The coding module is used to select the prediction result corresponding to the prediction calculation with the smallest distortion rate as the coding of the current block; and trigger the selection module to select the next macroblock to be predicted until all the macroblocks in the picture All coded.

In order to solve the above technical problems, the present invention also provides an acceleration system for the intra-frame prediction stage of the webp compression algorithm, which is used in a data center server, including a CPU and a computing chip, and the CPU includes the above picture intra-frame prediction device.

Preferably, the computing chip is specifically an FPGA.

The present invention provides an acceleration method, device and system for the intra-frame prediction stage of the webp compression algorithm, which divides the macroblocks in the CPU, and performs a logic judgment operation on whether there are coded macroblocks in the preset positions around the current block, and then Predictive calculations for the current block and encoded macroblocks are performed by the computing chip. That is to say, the present invention distinguishes operations such as logic judgment from vector calculation operations, which are performed by CPU and computing chip respectively. Compared with CPU, computing chip is more suitable for computing operations, while CPU is only used to process operations such as logical judgment. The division of work by a chip increases the speed of intra-frame prediction.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the prior art and the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present invention. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is the flow chart of the process of the acceleration method of a kind of webp compression algorithm intra prediction stage that the present invention provides;

Fig. 2 is a schematic diagram of the current block and surrounding coded macroblocks in a specific embodiment provided by the present invention;

FIG. 3 is a schematic structural diagram of an acceleration system in the intra prediction stage of a webp compression algorithm provided by the present invention.

detailed description

The core of the present invention is to provide an acceleration method and device for the intra-frame prediction stage of a webp compression algorithm, which distinguishes operations such as logic judgment from vector calculation operations, which are performed by the CPU and the computing chip respectively, and the two chips are divided into tasks. Intraprediction is fast.

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The present invention provides an acceleration method for the intra-frame prediction stage of a webp compression algorithm, which is used in a data center server, as shown in Figure 1, which is a process of an acceleration method for the intra-frame prediction stage of a webp compression algorithm provided by the present invention A flowchart of the method; the method includes:

Step s101: Obtain a picture in webp format on the CPU side, divide the picture into macroblocks of a preset size and record the position information of each macroblock;

It can be understood that the picture adopts the YUV color coding method, and each macroblock is composed of one luma block and two chrominance blocks. Since the sampling rate of Y (brightness component) and UV (chrominance component) are different, the Y , UV is divided into blocks of different sizes, wherein the size of the Y luma block is 16*16, and the size of the UV chrominance block is 8*8; of course, the present invention does not limit the specific size of each macro block.

Step s102: Select the current macroblock to be predicted as the current block, judge whether there is an encoded macroblock in the preset position around the current block on the picture according to the position information of the current block, and if so, combine the current block and the encoded macroblock The block is sent to the calculation chip; the calculation chip performs several preset prediction calculations according to the current block and the encoded macro block, and obtains the prediction result and distortion rate of each prediction calculation, and sends it to the CPU;

Wherein, the location information here is specifically coordinates, for example, may be xy coordinates. In addition, it is also necessary to calculate the start address of the current block according to the coordinates of the current block and the row and column widths of the current block, which is used for sending the macroblock.

Preferably, the surrounding preset positions are specifically the left side, upper side and upper left side of the current block. The surrounding preset positions depend on the prediction calculation method, which is not limited in the present invention.

In addition, after sending the current block and the encoded macroblock to the computing chip, the CPU will send a start control command to the computing chip for setting relevant parameters and controlling the computing chip to perform predictive calculations. Of course, the parameter setting here depends on the specific situation.

Further, when the prediction is completed, the computing chip will send an end flag to the CPU, and the CPU will generate a read instruction after receiving the end flag, and read the prediction results and distortion rates of various prediction calculations.

Step s103: Select the prediction result corresponding to the prediction calculation with the smallest distortion rate as the encoding of the current block, and repeat step s102 until all the macroblocks in the picture are encoded.

Among them, several preset forecasting calculations specifically include:

One or a combination of horizontal prediction, vertical prediction, DC prediction and motion prediction.

For easy understanding, a 4*4 macroblock is taken as an example. Referring to FIG. 2 , FIG. 2 is a schematic diagram of a current block and surrounding coded macroblocks in a specific embodiment of the present invention.

Among them, the relational formula of each prediction calculation is as follows:

Horizontal prediction: X _ij =L _i ; that is, during horizontal prediction, the prediction result of each pixel in the current block is equal to the coding of the programmed macroblock in the same row on the left.

Vertical prediction: X _ij =A _j ; that is, during vertical prediction, the prediction result of each pixel in the current block is equal to the coding of the programmed macroblock in the same column above it.

DC prediction: X _ij = (L _i +A _j /2

Motion prediction: X _ij =L _i +A _j -C

Where i, j are both ∈ (0, 1, 2, 3), X _ij represents the prediction result of each pixel of the current macroblock.

The present invention provides an acceleration method for the intra-frame prediction stage of the webp compression algorithm, which divides the macroblocks in the CPU, and performs a logical judgment operation on whether there are encoded macroblocks in the preset positions around the current block, and then performs the current block and The prediction calculation of the coded macroblock is performed by the calculation chip. That is to say, the present invention distinguishes operations such as logic judgment from vector calculation operations, which are performed by CPU and computing chip respectively. Compared with CPU, computing chip is more suitable for computing operations, while CPU is only used to process operations such as logical judgment. The division of work by a chip increases the speed of intra-frame prediction.

The present invention also provides an acceleration device for the intra-frame prediction stage of a webp compression algorithm, which is used for a data center server, and the device includes:

Picture acquisition module 11, is used for obtaining the picture of webp format at CPU end, divides picture into the macroblock of preset size and records the positional information of each macroblock;

The selection module 12 is used to select the current macroblock to be predicted as the current block, judge whether there is an encoded macroblock in the preset position around the current block on the picture according to the position information of the current block, and if so, convert the current block and The coded macroblock is sent to the computing chip 2; the computing chip 2 performs several preset prediction calculations according to the current block and the coded macroblock, and obtains the prediction result and distortion rate of each prediction calculation, and sends it to the CPU1 ;

The encoding module 13 is used to select the prediction result corresponding to the prediction calculation with the smallest distortion rate as the encoding of the current block; and trigger the selection module 12 to select the next macroblock to be predicted until all the macroblocks in the picture are encoded.

The present invention provides an acceleration device for the intra-frame prediction stage of the webp compression algorithm, which divides the macroblocks in the CPU, and performs a logical judgment operation on whether there are coded macroblocks in the preset positions around the current block, and then performs the current block and The prediction calculation of the coded macroblock is performed by the calculation chip. That is to say, the present invention distinguishes operations such as logic judgment from vector calculation operations, which are performed by CPU and computing chip respectively. Compared with CPU, computing chip is more suitable for computing operations, while CPU is only used to process operations such as logical judgment. The division of work by a chip increases the speed of intra-frame prediction.

The present invention also provides an acceleration system for the intra-frame prediction stage of a webp compression algorithm, which is used for a data center server, as shown in FIG. 3 . FIG. 3 is an acceleration system for the intra-frame prediction stage of a webp compression algorithm provided by the present invention Schematic. The system includes a CPU1 and a computing chip 2, and the CPU1 includes the above picture intra prediction device.

Wherein, the computing chip 2 here is specifically an FPGA. It can be understood that FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) has a fast calculation speed and is suitable for running processing involving a large number of vector operations.

In addition, the present invention needs to set a cache in the FPGA, which can be set on the DDR memory (Double Data Rate, double data rate synchronous dynamic random access memory) of the FPGA. Of course, the present invention does not limit the location of the cache. The cache is used for encoding the current block sent by the CPU1 and the programmed macroblocks at the preset positions around it, and obtaining the prediction result and distortion rate after the prediction is completed.

In addition, the present invention can use the OpenCL high-level language to generate corresponding algorithm descriptions, and further generate a host-side program running on the CPU1 and a Kernel-side program oriented to the FPGA platform. Then, use the GCC compiler to compile the host-side program to generate an executable program file that can be executed on CPU1; use the Altera SDK for OpenCL (AOC) high-level synthesis tool to compile and synthesize the Kernel program file to generate an executable program file that can be executed on the FPGA. AOCX file to run. Finally, the PCI-E interface is used to connect CPU1 and FPGA for data communication; the DDR3 memory on the FPGA development board is used as a data cache. Of course, the above is a preferred embodiment, and how to generate the program depends on the actual situation.

It should be noted that in this specification, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations Any such actual relationship or order exists between. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. a method for accelerating the intra-frame prediction stage of a webp compression algorithm, used for data center servers, characterized in that, comprising: Step s101: Obtain a picture in webp format on the CPU side, divide the picture into macroblocks of a preset size and record the position information of each macroblock; Step s102: Select the current macroblock to be predicted as the current block, judge whether there is an encoded macroblock in the preset position around the current block on the picture according to the position information of the current block, and if so, store the The current block and the coded macro block are sent to the calculation chip; the calculation chip performs several preset prediction calculations according to the current block and the coded macro block, and obtains the prediction calculation of each Prediction results and distortion rates are sent to the CPU; Step s103: Select the prediction result corresponding to the prediction calculation with the smallest distortion rate as the encoding of the current block, and repeat step s102 until all the macroblocks in the picture are encoded. 2 . The method according to claim 1 , wherein the preset surrounding positions are specifically the left side, upper side and upper left side of the current block. 3 . 3. The method according to claim 1, characterized in that, the preset several predictive calculations specifically include: One or a combination of horizontal prediction, vertical prediction, DC prediction and motion prediction. 4. An acceleration device for the intra-frame prediction stage of a webp compression algorithm, used for a data center server, is characterized in that, comprising: The picture acquisition module is used to obtain the picture of webp format at the CPU side, divides the picture into macroblocks of preset size and records the position information of each macroblock; The selection module is used to select the current macroblock to be predicted as the current block, and judge whether there is an encoded macroblock in the preset position around the current block on the picture according to the position information of the current block, if there is , sending the current block and the coded macro block to the computing chip; the computing chip performs several preset prediction calculations according to the current block and the coded macro block, and obtains each of the The prediction result and the distortion rate of the prediction calculation are sent to the CPU; The coding module is used to select the prediction result corresponding to the prediction calculation with the smallest distortion rate as the coding of the current block; and trigger the selection module to select the next macroblock to be predicted until all the macroblocks in the picture All coded. 5. An acceleration system for the intra-frame prediction stage of a webp compression algorithm, which is used in a data center server, is characterized in that it includes a CPU and a computing chip, and the picture intra-frame prediction device as claimed in claim 4 is included in the CPU. 6. The system according to claim 4, wherein the computing chip is specifically an FPGA.