CN106549058A - Semiconductor device manufacturing method - Google Patents

Abstract

The present invention provides a FinFET manufacturing method, by forming a silicon/germanium silicon stack and removing one of the materials to form a nanowire, since the silicon/germanium silicon stack is included in the fin, the nanowire does not need to use additional The pad is supported, which reduces the difficulty of the process, and, due to the difference in material properties between silicon and germanium, one of the materials can be removed by a wet etching process with a high selectivity ratio, without using a dry etching process, further The process is simplified; and the invented method is compatible with the conventional FinFET process, and the FinFET nanowire device can be easily and effectively obtained.

Description

Semiconductor device manufacturing method

technical field

The present invention relates to the field of semiconductor device manufacturing methods, in particular to a method for manufacturing FinFET semiconductor devices.

Background technique

In the past 30 years, semiconductor devices have been proportionally reduced in accordance with Moore's law, the feature size of semiconductor integrated circuits has been continuously reduced, and the integration level has been continuously improved. As the technology node enters the deep sub-micron field, such as within 100nm or even within 45nm, the traditional field effect transistor (FET), that is, planar FET, begins to encounter the limitations of various basic physical laws, making its prospect of scaling down challenged . Many new structure FETs have been developed to meet the actual needs, among which FinFET is a new structure device with great potential for scaling down.

FinFET, Fin Field Effect Transistor, is a multi-gate semiconductor device. Due to its unique structure, FinFET has become a promising device in the field of deep submicron integrated circuits. As the name implies, FinFET includes a Fin perpendicular to the bulk silicon substrate, and Fin is called fin or fin-shaped semiconductor pillar, and different FinFETs are separated by STI structure. Unlike conventional planar FETs, the channel region of the FinFET is located within the Fin. The gate insulating layer and the gate surround Fin on the side and top surface, thereby forming a gate on at least two sides, that is, a gate on both sides of Fin; at the same time, by controlling the thickness of Fin, FinFET has excellent characteristics : Better short channel effect suppression ability, better sub-threshold slope, lower off-state current, eliminating floating body effect, lower operating voltage, and more conducive to scaling down.

Although FinFET has the above-mentioned advantages, there are still situations where the current is small and the gate control is weak. In order to solve the above problems, nanowires are considered to be a better solution. However, the conventional etching method for forming nanowires is relatively complicated and not very compatible with conventional FinFET processes; at the same time, nanowires need pads for support. This leads to a more complicated process and increases the production cost

Therefore, it is necessary to provide a new FinFET manufacturing method to form nanowires in a more convenient and effective way.

Contents of the invention

The invention proposes a FinFET manufacturing method, which adopts silicon/germanium-silicon stacking and high selectivity etching process to easily and effectively manufacture the FinFET device with nanowire structure.

The invention provides a method for manufacturing a semiconductor device, which is used to manufacture a FinFET device, comprising the following steps:

For manufacturing a FinFET device, it is characterized in that comprising the following steps:

providing a substrate, and forming an impurity layer on a surface of the substrate;

forming a silicon/germanium-silicon stack in which silicon layers and germanium-silicon layers are alternately stacked on the impurity layer;

Fins are formed by patterning;

forming STIs on both sides of the fin;

Form dummy gate oxide layer, dummy gate stack, gate sidewall;

Forming source and drain extension regions and source and drain regions;

Depositing a dielectric layer comprehensively to cover the dummy gate stack;

planarizing to expose the upper surface of the dummy gate stack, and removing the dummy gate stack and the dummy gate oxide layer;

removing the silicon or silicon germanium material in the silicon/germanium silicon stack;

A gate insulating layer and a gate are formed.

According to one aspect of the present invention, the impurity layer is a layer formed by implantation or epitaxial in-situ doping on the substrate, which has an impurity opposite to the doping type of the source and drain regions of the semiconductor device to be fabricated; A barrier layer for preventing impurity diffusion is formed between the impurity layer and the substrate; the barrier layer is an element with an atomic number smaller than silicon, preferably carbon.

According to one aspect of the invention, the top of the STI is higher than the bottom of the silicon/germanium stack.

According to one aspect of the present invention, when removing the silicon or silicon germanium material in the silicon/germanium silicon stack, the silicon or germanium silicon material is removed by a process with a high etching selectivity; the silicon/germanium silicon stack is removed When silicon is contained in the silicon, dry etching or wet etching is used; when wet etching is used, an organic solvent having a hydroxyl group is selected, preferably TMAH.

The advantage of the present invention is that by forming a silicon/germanium-silicon stack and removing one of the materials to form a nanowire, since the silicon/germanium-silicon stack is contained in the fin, the nanowire does not need to be supported by an additional pad , which reduces the difficulty of the process, and, due to the difference in material properties between silicon and germanium, one of the materials can be removed by a wet etching process with a high selectivity ratio, without using a dry etching process, which further simplifies the process; Moreover, the invented method is compatible with the conventional FinFET process, and the FinFET nanowire device can be obtained simply and effectively.

Description of drawings

1-10 are schematic flow charts of the semiconductor manufacturing method provided by the present invention.

detailed description

Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

The invention provides a method for manufacturing a semiconductor device, and in particular, relates to a method for manufacturing a FinFET device. Hereinafter, referring to the accompanying drawings, the semiconductor device manufacturing method provided by the present invention will be described in detail.

First, referring to FIG. 1 , a substrate 1 is provided, and an impurity layer 2 is formed on the surface of the substrate 1 . The substrate 1 can be reasonably selected according to the needs of device applications, including but not limited to bulk silicon substrates, SOI substrates, germanium substrates, silicon germanium (SiGe) substrates, compound semiconductor materials, such as gallium nitride (GaN), arsenic Gallium (GaAs), Indium Phosphide (InP), etc. In consideration of compatibility with conventional semiconductor processes and cost, the substrate 1 in this embodiment preferably adopts a bulk silicon substrate.

The impurity layer 2 is a layer formed by implantation or epitaxial in-situ doping on the substrate 1 , which has an impurity opposite to the doping type of the source and drain regions of the semiconductor device to be fabricated. In addition, optionally, between the impurity layer 2 and the substrate 1, a barrier layer (not shown) for preventing diffusion of impurities is formed. The barrier layer can prevent the diffusion of impurity elements in the impurity layer 2 and the diffusion of dopant elements in the substrate 1 , and can be formed by implantation or epitaxy on the substrate 1 . The blocking layer includes an element with an atomic number smaller than silicon, and carbon element is preferably used to produce a blocking effect.

Next, referring to FIG. 2 , on the impurity layer 2 , a silicon/germanium-silicon stack 3 in which silicon layers and germanium-silicon layers are alternately stacked is formed. The silicon/germanium-silicon stack 3 is preferably formed by an epitaxial process, and its bottom layer is silicon or germanium. In the illustrated embodiment of the present invention, a germanium-silicon layer is used as the bottom layer; in an optional embodiment, silicon can be used. layer is the bottom layer. The silicon/germanium-silicon stack 3 is used to form nanowires in subsequent processes, the thickness of each layer of silicon and germanium-silicon layer is 2-50nm, preferably 5-15nm, and the number of stacks is usually more than 3 layers, preferably 5 layers, that is, silicon germanium/silicon/silicon germanium/silicon/silicon germanium from bottom to top.

Referring to FIG. 3 , which is a side view, fins are formed by patterning. Preferably, the fin includes a silicon/germanium silicon stack 3 , an impurity layer 2 and a protruding portion 4 of the substrate 1 .

Next, referring to FIG. 4 , which is a side view, STI structures 5 are formed on both sides of the fin. Wherein, the STI structure 5 is formed on the substrate 1 using materials such as SiO ₂ and SiON, and specific processes include but are not limited to PECVD, HDP-CVD, RTO (rapid thermal oxidation) and the like. Preferably, the top of the STI structure 5 is higher than the bottom of the silicon/germanium silicon stack 3 to achieve isolation between nanowire devices.

After the STI structure 5 is formed, referring to FIG. 5 , a dummy gate oxide layer 6 , a dummy gate stack 7 and a gate spacer 8 are formed. The lines of the dummy gate oxide layer 6 , the dummy gate stack 7 , and the gate sidewall 8 straddle the fins, usually perpendicular to the lines of the fins. The dummy gate oxide layer 6 is, for example, SiO ₂ , and the material of the dummy gate stack 7 is polysilicon or amorphous silicon. In one embodiment of the present invention, amorphous silicon is used. The specific method for forming the gate spacer 8 includes: depositing gate spacer material on the entire surface, and performing etching back, wherein the gate spacer material includes but not limited to Si ₃ N ₄ .

Next, referring to FIG. 6 , a source-drain extension region and a source-drain region 9 are formed. The specific process includes removing part of the silicon/germanium-silicon stack 3 material, forming source and drain grooves, and then filling the source and drain extension regions and the source and drain regions 9, for example, by using epitaxy and other processes. The source-drain extension region and the source-drain region 9 may also use silicide or stress material.

Referring to FIG. 7 , a dielectric layer 10 is deposited all over to cover the dummy gate stack 7 , the gate spacer 8 and so on. The material of the dielectric layer 10 is SiO ₂ or the like.

Next, referring to FIG. 8 , a planarization process is used to expose the upper surface of the dummy gate stack 7 , and then the dummy gate stack 7 and the dummy gate oxide layer 6 are removed to form a gate groove 11 . The gate recess 11 also exposes the top and side surfaces of the fin including the silicon/germanium silicon stack 3 .

Referring to FIG. 9 , one of the silicon or silicon germanium materials in the silicon/silicon germanium stack 3 is removed through the exposed gate groove 11 . Preferably, silicon or silicon germanium is removed by using a high selectivity etching process, such as dry or wet etching. The more selective use of wet etching rather than dry etching processes further simplifies the process. In the preferred embodiment of the present invention, the silicon material is removed. When wet etching is used, an organic solvent with hydroxyl groups, preferably TMAH, is selected. In this case, silicon germanium is retained as the nanowire, that is, the channel region of the device. The silicon germanium channel region will have better device performance; in an alternative embodiment, the silicon germanium can be selectively removed while the silicon material remains. FIG. 9 is a schematic diagram after the silicon material is removed, wherein oblique hatching indicates the space formed after the silicon material is removed.

Next, referring to FIG. 10 , a gate insulating layer and a gate 12 are formed. The gate insulating layer and the gate 12 are HKMG, wherein the gate insulating layer adopts a high-K gate insulating layer material, one or more layers selected from one or a combination of the following materials: Al ₂ O ₃ , HfO ₂ , a hafnium-based high-K dielectric material including at least one of HfSiO _x , HfSiON, HfAlO _x , HfTaO _x , HfLaO _x , HfAlSiO _x , and HfLaSiO _x , including ZrO ₂ , La ₂ O ₃ , LaAlO ₃ , TiO ₂ , or A rare earth-based high-K dielectric material containing at least one of Y ₂ O ₃ . The material of the gate is metal, alloy or metal compound, such as TiN, TaN, W and so on. The gate insulating layer and the gate 12 surround the remaining silicon germanium or silicon nanowires in the silicon/silicon germanium stack 3 to form a device. FIG. 10 is a schematic diagram surrounding silicon germanium nanowires, where the square hatching represents the gate insulating layer and the gate 12 .

In the above, the semiconductor device manufacturing method of the present invention has been described. In the method of the present invention, nanowires are formed by forming a silicon/germanium-silicon stack and removing one of the materials. Since the silicon/germanium-silicon stack is contained in the fins, the nanowire does not need to use an additional pad for processing. support, which reduces the difficulty of the process, and, due to the difference in material properties between silicon and germanium, one of the materials can be removed by a wet etching process with a high selectivity ratio, without using a dry etching process, which further simplifies the process ; and the invented method is compatible with the conventional FinFET process, and can easily and effectively obtain the FinFET nanowire device.

Although the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures and/or process flows without departing from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (7)

1. a kind of method, semi-conductor device manufacturing method, for manufacturing FinFET, its feature exists In comprising the steps：

Substrate is provided, and impurity layer is formed on the surface of the substrate；

Alternately laminated silicon/germanium silicon the lamination of silicon layer and germanium silicon layer is formed on the impurity layer；

By patterned process, fin is formed；

STI is formed in the fin both sides；

Form dummy gate oxide layer, dummy gate electrode storehouse, grid curb wall；

Form source drain extension area and source-drain area；

Comprehensive metallization medium layer, covers the dummy gate electrode storehouse；

Planarization process exposes the dummy gate electrode storehouse upper surface, and removes the illusory grid Pole storehouse and the dummy gate oxide layer；

Remove the silicon or germanium silicon material in the silicon/germanium silicon lamination；

Form gate insulator and grid.

2. method according to claim 1, it is characterised in that the impurity layer is in institute The layer that injection or extension doping in situ are formed on substrate is stated, which has partly is led with to make The contrary impurity of body device source-drain area doping type.

3. method according to claim 2, it is characterised in that in the impurity layer and institute State between substrate, formation prevents the barrier layer that impurity spreads.

4. method according to claim 3, it is characterised in that the barrier layer is atom Element of the ordinal number less than silicon, preferably carbon.

5. method according to claim 1, it is characterised in that the top of the STI is high In the bottom of the silicon/germanium silicon lamination.

6. method according to claim 1, it is characterised in that removing the silicon/germanium silicon During silicon or germanium silicon material in lamination, silicon or germanium silicon are removed using the technique of high etching selection ratio Material.

7. method according to claim 6, it is characterised in that remove the silicon/germanium silicon and fold Layer in silicon when, using dry etching or wet etching；During using wet etching, tool is selected There are the organic solvent of hydroxyl, preferably TMAH.