CN106533404B - A Triangular Carrier Slope Randomly Distributed Pulse Width Modulation Circuit - Google Patents

Abstract

The invention discloses a triangular carrier slope random distribution pulse width modulation circuit, comprising a system clock module, a counter module, a Rom module and a random triangular carrier processing module; the system clock module is used for a system clock signal; the counter module is used for according to the real-time system clock Signal output count; the Rom module is used to take the count as an address, take out the stored random data Δ _i , and transmit the random data Δ _i to the random triangular carrier processing module; the random triangular carrier processing module is used to The data _Δi generates a random triangular carrier and outputs it to the modulation main circuit. The invention can reduce the electromagnetic interference inside the power system, reduce the mechanical vibration and noise from the source without changing the topology of the main circuit of pulse width modulation, so as to effectively solve the electromagnetic interference problem inside the power system and the vibration noise problem outside the system It provides a new way; vibration reduction and noise reduction do not depend on additional equipment, which reduces the cost of filtering and vibration reduction, and saves system resources.

Description

A Triangular Carrier Slope Randomly Distributed Pulse Width Modulation Circuit

technical field

The invention belongs to the technical field of power electronics, and specifically relates to a pulse width modulation circuit with a random distribution of the slope of a triangular carrier wave.

Background technique

In power electronics technology, pulse width modulation technology with a fixed carrier frequency has been widely used. This technology is based on the equivalent principle of volt-second balance. The duty cycle is determined by controlling the on-off of the switching device to modulate different waveforms. However, the output voltage has harmonics with large amplitudes at the carrier frequency and its multiplier. The hazards of the system are very extensive: for the system, these harmonics are the main source of electromagnetic interference, which reduces the electromagnetic compatibility quality of the system, and even affects the normal operation of other devices and equipment in the system; , harmonics will cause undesired loss, produce mechanical vibration and air noise; in the field of target recognition, the use of harmonic spectrum as target features can be used to track and identify ships, so the existence of harmonics will also affect ships Stealth performance of the boat.

With the rapid development of power electronics technology, a large number of literatures have proposed different solutions to the above problems of fixed carrier frequency PWM technology: researchers may start from the modulation method itself and improve the PWM technology; or Starting from the outside of the system, passively add filtering and vibration reduction equipment to reduce the influence of harmonics, and achieve the purpose of reducing electromagnetic interference and eliminating noise. The shortcomings of these methods are also very obvious. For example, the specific harmonic elimination method: when the topology of the power converter is different, the corresponding PWM control laws are different. At this time, the nonlinear equation for harmonic elimination is It has to be recalculated - this method is only an optimization scheme for specific main circuit topology applications, and has no universal value, and the calculation of the nonlinear equation of the specific harmonic elimination method is also very complicated. Large data sheets; additional filtering and vibration damping equipment usually takes up space and adds weight to the equipment. For many military equipment with limited space and load, this is undoubtedly not an ideal solution.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the problem that the output voltage of the pulse width modulation with a fixed carrier frequency has large amplitude harmonics at the carrier frequency and its frequency multiplication, and proposes a triangular carrier slope random distribution pulse width modulation circuit to achieve The purpose of dispersing harmonic energy is achieved; at the same time, the harmonic distortion rate THD of the output voltage remains unchanged.

In order to achieve the above-mentioned purpose, a kind of triangle carrier slope random distribution pulse width modulation circuit designed by the present invention is special in that it comprises a system clock module, a counter module, a Rom module and a random triangle carrier processing module;

The system clock module is used for a system clock signal;

The counter module is used to output counting according to the real-time system clock signal;

The Rom module is configured to take the count as an address, take out the stored random data Δ _i , and transmit the random data Δ _i to the random triangular carrier processing module;

The random triangular carrier processing module is used for generating a random triangular carrier according to the random data Δ _i and outputting the random triangular carrier to the modulation main circuit.

Further, the pulse width modulation circuit is implemented based on FPGA. The random data Δ _i is stored in the FPGA, which solves the problem of excessive computational burden caused by real-time generation of random carrier sequences in existing research; at the same time, this measure can also ensure the real-time performance of random triangular carrier pulse width modulation.

Further, the random data Δ _i is determined by the random triangular carrier cycle T _i and the output main frequency f of the system clock module. As a result, the range of the random triangular carrier period T _i can be controlled in advance to avoid excessive loss due to an excessively high random carrier frequency range and excessive mechanical vibration due to an excessively low switching frequency.

Further, the random triangular carrier processing module judges and outputs a high pulse or a low pulse according to the value of the random data Δ _i . This process can be realized only by FPGA, which avoids the disadvantage that the combination of FPGA and DSP is required to perform random pulse width modulation in the existing research.

The principle of the present invention is as follows: First, from the perspective of frequency domain harmonic distribution, the principle of energy dispersion in frequency domain of output voltage of random carrier pulse width modulation technology is theoretically deduced. The main circuit topology of the single-phase full-bridge inverter is shown in Figure 1. Taking sinusoidal pulse width modulation as an example, it modulates the sinusoidal signal through a fixed frequency carrier. Wherein, U _C is a carrier signal with a fixed frequency, and U _S is a sine wave modulation signal; when the first switch S ₁ and the fourth switch S ₄ are turned on, the output voltage U _AB is +U/2, when the second switch S ₂ and the third switch S ₃ are turned on, the output voltage U _AB is -U/2; and when the first switch S ₁ and the second switch S ₂ are turned on or the third switch S ₃ and the fourth switch S ₄ are turned on When , the output voltage U _AB is 0; by changing the width ratio of +U/2 and -U/2, the expected sinusoidal pulse width modulation output voltage can be obtained as shown in (a).

Secondly, when the average symmetrical rule is used for sampling, the partial magnification of the sine pulse width modulation of the fixed carrier frequency is shown in (b), and the partial magnification when the symmetrical rule is used for sampling is shown in (c); U is the DC terminal in Figure 1. Input voltage; pulse width W is the sinusoidal modulation signal _{U S =} acosω _{0 t} (ω ₀ is the fundamental angular frequency, a is determined by the value of the modulation depth), and the corresponding pulse is symmetrical with the sampling point as the center, we can get:

Wherein UA is the voltage at point _A in Figure 1, and θ1, θ2, θ3, and θ4 are the angle values of π/2, π, 3/2π, and 2π at four different moments in θ=ωs _t , respectively;

right Expanding the Fourier series, we can get the following formula:

a _n and b _n are the coefficients after Fourier series expansion, respectively, where a ₀ =acosω ₀ t (a is the modulation depth, ω ₀ is the fundamental angular frequency, and n is a natural number); it can be seen that when ω ₀ is fixed When , the value of the first term acosω ₀ t in the right side of Equation (1) is also determined, that is, the first term is the DC part, and the second term changes with the change of the carrier frequency, which is the harmonic component; The Harmonic component H of the second term is analyzed by the Er function, and we can get:

Among them, J _k is the Bessel function of the first kind (when l=1, 3,..., n=2, 4,...; when l=0, 2,..., n=1, 3,...; k= 1, 2, …).

According to the reduction result of (2), it can be known that the output harmonic amplitude A of the sinusoidal pulse width modulation with a fixed carrier frequency is:

A=(4U/nπ)×J _k (anπ/2) (3)

At the same time, the harmonic distortion (THD) of the output voltage can be obtained as:

For the single-phase main circuit, when the IGBT module 3 is turned on, the first switch S ₁ and the fourth switch S ₄ or the second switch S ₂ and the third switch S ₃ must be turned on at the same time, that is, there are A and The potential of B is opposite, therefore, the output voltage U _AB =U _A -U _B =U, the amplitude of the fundamental wave and the harmonic wave will be twice of the calculation results in equations (1) and (2). When the modulating signal is a sinusoidal signal and the carrier signal is a carrier wave, the above formula deduces the harmonics of the single-phase PWM output voltage, and it can be known that:

(1) For the fundamental wave part ω ₀ , its amplitude is aU;

(2) For the harmonic part nω _s +kω ₀ , its amplitude is (4U/nπ)×J _k (anπ/2);

(3) The amplitude of the fundamental wave is only related to the modulation depth a;

(4) The THD of the output voltage is only related to the modulation depth.

Based on the above analysis, it can be seen that in the right side of equation (1), the second term is the harmonic component. Since the Fourier transform of cos(nω _s t) is a unit impulse function:

The unit impulse function and the fixed part in equation (1) are convolved in the frequency domain. According to the characteristics of the unit impulse function in the frequency domain, it can be known that the convolution of any function in the frequency domain and the unit impulse function is the function in the frequency domain. 's move. That is to say, for each n value of the pulse width modulation technique with a fixed carrier frequency, the calculation of the distribution of the harmonic components in the second term of equation (1) in the frequency domain can be regarded as the carrier frequency and its multiple frequencies. For (4/nπ)sin[(nπ/2)sin(ω ₀ t)+(nπ/2)] Fourier transform amplitude shift; in the frequency domain, for all harmonic calculations of n values, it is equivalent to Different harmonics of the same carrier are distributed at the carrier and its multiple frequencies. For different orders n, the spectral amplitudes of the harmonics will also be superimposed at the carrier and its multiple frequencies.

With the same topology, as long as the triangular carrier of the input part of the modulation main circuit is replaced with a random triangular carrier signal, an expression similar to formula (2) can be obtained. By introducing the randomly distributed triangular carrier frequency, the formula can be obtained:

Among them, the mean value of the random triangular carrier frequency is f _av , and the angle change caused by the random triangular carrier frequency is composed of the 2πnf _av part caused by the frequency mean and the real-time angle difference part φ(t). At this time, the schematic diagram of the triangular carrier slope pulse width modulation technique is as shown. Randomly changing the slope of the triangular carrier, then the random distribution of the triangular carrier slope PWM is equivalent to adding several randomly distributed carrier frequencies within a certain period of time.

Therefore, the main circuit topology analysis of the single-phase full-bridge inverter combined with equation (7) can deduce the corresponding formula for the random distribution pulse width modulation of the triangular carrier slope, and similarly, the harmonic characteristics of the random distribution pulse width modulation of the triangular carrier slope can be obtained. :

(1) The fundamental wave component does not contain random carrier frequency, does not change with the carrier wave, and the fundamental wave frequency domain amplitude does not change;

(2) Randomly changing the average value of the carrier carrier frequency is equal to the carrier frequency of the fixed carrier frequency PWM; if the carrier frequency changes randomly, the spacing between spectrum lines will be reduced, and this reduction is caused by the change in the number of carrier frequencies. , not caused by an increase in the value of a single carrier frequency or a change in the switching frequency;

(3) What the carrier slope random distribution PWM does is not to reduce the total decibels of the noise, but to move the original harmonics with larger amplitudes to achieve the purpose of dispersing the harmonic energy; at the same time, the harmonics The wave distortion rate THD remains unchanged.

In this design, the random carrier frequency of the random distribution pulse width modulation circuit of the triangular carrier slope is generated by the random carrier processing module through a predetermined random number, which is equivalent to adding several randomly distributed carrier frequencies within a certain period of time, so that the original focus on the carrier and The harmonic amplitude at the frequency doubling is suppressed, and it is basically consistent with the harmonic distortion rate THD of the output voltage during the fixed carrier pulse width modulation, which greatly improves the power quality.

The advantage of the present invention is that it can reduce the electromagnetic interference inside the power system, reduce the mechanical vibration and noise from the source without changing the topology of the main circuit of the pulse width modulation, so as to effectively solve the electromagnetic interference problem inside the power system and the outside of the system. It provides a new way to solve the problem of vibration and noise; vibration reduction and noise reduction do not depend on additional equipment, which reduces the cost of filtering and vibration reduction, and saves system resources.

Description of drawings

Figure 1 is the main circuit topology diagram of the single-phase full-bridge inverter;

Figure 2a is a waveform diagram of a sinusoidal pulse width modulation output voltage;

Figure 2b is a waveform diagram of a sinusoidal pulse width modulation voltage with a fixed carrier frequency;

Figure 2c is a waveform diagram of a sinusoidal pulse width modulation voltage with a fixed carrier frequency;

Fig. 3 is the waveform diagram of triangular carrier slope pulse width modulation voltage;

4 is a structural block diagram of a triangular carrier slope random distribution pulse width modulation circuit according to the present invention;

Fig. 5 is a flow chart of processing by a random triangular carrier processing module in Fig. 1;

Fig. 6 is the output pulse of random triangular carrier processing module in Fig. 1;

Fig. 7 is a triangular carrier slope random distribution pulse width modulation output voltage waveform spectrum and spectrum distribution diagram;

FIG. 8 is a pulse width modulation output voltage waveform and spectrum distribution diagram of a fixed carrier frequency.

In the figure: system clock module 1-1, counter module 1-2, Rom module 1-3 and random triangular carrier processing module 1-4, adjust main circuit 2, IGBT module 3.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in FIG. 4 , a triangular carrier slope random distribution pulse width modulation circuit of the present invention is implemented by FPGA and includes a system clock module 1-1, a counter module 1-2, a Rom module 1-3 and a random triangular carrier processing module 1 -4. The system clock module 1-1 outputs the main frequency f (for example, at 50MHz, the minimum system count time is 0.02 microseconds). 1-1 is connected, the counter module 1-2 receives the system clock signal sent by the system clock module 1-1 to count, and outputs the count to the Rom module 1-3, and the Rom module 1-3 takes the count as the address and takes it out from the Rom Stored random data, and send the random data to the random carrier processing modules 1-4.

According to needs, generate random numbers and store them in Rom modules 1-3, and the random numbers are generated by random carrier frequency fi (corresponding random carrier cycle is T _{i )} average value f _av (n is random The number of carriers, f _i is the ith carrier frequency) should be equal to the frequency f _c of the pulse width modulation of the fixed carrier frequency to ensure equal switching times in the same time, that is, the switching loss remains unchanged (for example, the fundamental frequency is When the PWM is 50Hz and the fixed carrier frequency is 5KHz, 100 random carriers are generated within 0.02 seconds, and the average frequency of these 100 random carriers must be 5KHz).

The method for realizing the random distribution pulse width modulation of the slope of the triangular carrier by the present invention is the process of modulating the random triangular carrier by the carrier of the fixed frequency. The method for generating the random triangular carrier comprises the following steps:

1) Set the average value of random triangular carrier frequency f _av , and the number of random triangular carriers n, then the random triangular carrier frequency is f _i , i=1～n, and the corresponding random triangular carrier cycle is T _i , i=1～n , i cycle automatically from 1 to n during the random distribution of the triangular carrier slope during PWM;

2) Calculate all random data Δ _i , Δ _i =T _i /(1/f), and find the minimum random data Δ _min and the maximum random data Δ _max , where f is the output frequency;

3) When i is an odd number, set the initial value of the odd-numbered judgment condition Δc to _Δmin , and go to step 4). When i is an even number, set the initial value of the even-numbered judgment condition _{Δc '} to be _Δmax , and go to step 5. );

4) Set Δ _c =Δ _min +Δ _i , and compare whether Δ _c is greater than Δ _max , if yes, output a high pulse and return to step 1), otherwise loop this step;

5) Set Δ _c' =Δ _max -Δ _i , and compare whether Δ _c' is less than Δ _min , if yes, output a high pulse and return to step 1), otherwise loop this step.

In the random carrier processing module 1-4, the random triangular carrier frequency f _i is generated according to the random triangular carrier period T _i stored in the Rom module 1-3 and output to the modulation main circuit 2 . The processing flow chart of a single random carrier is shown in Figure 5. After converting T _i into random data Δ _i , accumulation or subtraction is performed according to the digital i output from the counting module 1-3, and the odd-numbered judgment condition _Δc and the even-numbered judgment condition Δc _' are determined according to the selected random data Δi _. Random data _Δmin and maximum random data _Δmax ( _Δmax and _Δmin are respectively the maximum and minimum values when counting); the duration of the output high/low pulse is determined by the odd-numbered judgment condition _Δc and the even-numbered judgment condition Δ _c' is determined by comparing with _Δmax or _Δmin . According to the principle of volt-second balance, it can be known that the generated high pulse is equivalent to the triangular carrier whose slope varies randomly in Fig. 3 .

For example, when the number of random carriers is _n =100 within 0.02 seconds, the average value of the random carrier frequency f _av = 5KHz, the period Ti of the random carrier ranges from 0 to 0.02 seconds (the limit is not acceptable), and the FPGA main frequency f = 50MHz, _Δmax is 24990000, _Δmin is 5000.

Assuming that the value of the _fifth random carrier cycle T5 is 0.00002296 seconds, Δ _i is 1148 after quantization, and i is an odd number at this time, the initial value of Δ _c is set to Δ _{min (} 5000), and Δ _c is accumulated, Comparing with Δ _max (24990000) every time of accumulation, when Δ _c is less than Δ _max , output low pulse; on the contrary, when the accumulated number Δ _c is greater than Δ _max , stop accumulation and output high pulse.

Assuming that the value of the sixth random carrier cycle _T6 is _0.00002296 seconds, Δ _i is ₁₁₄₈ after quantization, and i is an even number at this time. Comparing with _Δmin (5000) every time of accumulation, when _Δc is greater than _Δmin , a low pulse is output; on the contrary, when the accumulative number _Δc is less than _Δmin , the accumulation is stopped and a high pulse is output.

Take the average value of the random carrier frequency f _av = 5KHz, when the number of random carriers n = 100 within 0.02 seconds, the FPGA main frequency f = 50MHz; the system clock 1-1 continuously sends the count with a period of 50MHz, and transmits it to the counter module 1 -2. The Rom module 1-3 and the random carrier processing module 1-4 that store random numbers, the Rom module 1-3 takes out the stored random carrier cycle T _i according to the count and passes it to the random carrier processing module 1-4, and the random carrier process Modules 1-4 finally output pulses to modulation master module 2, as shown in Figure 6.

The modulation signal is set as a sine wave with a frequency of 50Hz, the DC voltage source U=300V, the resistance and inductance loads are 1Ω and 2mH respectively, the modulation depth a is set to 0.8, the fundamental frequency _f0 is set to 50Hz, and the carrier frequency is set to the fundamental 200 times the wave frequency, the PWM sub-module of the triangular carrier slope random distribution pulse width modulation is equivalent to adding 100 random distribution carrier frequencies with an average value of 10KHz in a repeating time (the repetition time is equal to the fixed carrier frequency pulse width modulation technology). The fixed carrier cycle in the As shown in Figure 8.

It can be seen that in one cycle analyzed by FFT, the triangular carrier slope is randomly distributed and the amplitude at the fundamental frequency of the PWM is the same as that of the fixed carrier PWM, while the original focus is on the harmonics at the carrier and its multipliers. The amplitude has been suppressed, and some harmonic spectrum values also appear at the frequency points where there is no harmonic amplitude in the fixed carrier PWM output voltage spectrum; at the same time, it can be seen that the THD of the output voltage is 146.05%, which is different from the The THD of the carrier pulse width modulation is basically the same; the maximum single harmonic amplitude is only 17.62, which is 84.82% lower than that of the fixed carrier pulse width modulation. Distribute over a wider range without changing the THD value. The triangular carrier slope random distribution pulse width modulation technology greatly improves the power quality.

In addition to the above-mentioned examples, the present invention can also have other implementation forms, and all solutions formed by equivalent replacement or equivalent transformation fall within the protection scope of the patent requirements.

Contents not described in detail in this specification belong to the prior art known to those skilled in the art.

Claims (2)

1. a triangular carrier slope random distribution pulse width modulation circuit, is characterized in that: comprise system clock module (1-1), counter module (1-2), Rom module (1-3) and random triangular carrier processing module ( 1-4); The system clock module (1-1) is used for a system clock signal; The counter module (1-2) is used to output counting according to the real-time system clock signal; The Rom module (1-3) is used to take the count as an address, take out the stored random data Δ _i , and transmit the random data Δ _i to the random triangular carrier processing module (1-4); the random data Δ i The data Δ _i is determined by the random triangular carrier cycle T _i and the output main frequency f of the system clock module (1-1); The random triangular carrier processing module (1-4) is configured to generate a random triangular carrier according to the random data Δ _i and output it to the modulation main circuit (2); the pulse width modulation circuit (1) is implemented based on FPGA. 2. a kind of triangular carrier slope random distribution pulse width modulation circuit according to claim 1, is characterized in that: described random triangular carrier processing module (1-4) judges and outputs high pulse according to the value of described random data Δ _i or low pulse.