CN106531809B - A deep trench power MOS device structure and its preparation method - Google Patents

Abstract

The present invention relates to the field of semiconductor manufacturing technology, in particular to a deep trench power MOS device structure and its preparation method. After the bulk ion implantation and annealing processes are completed, an overlay P-type ion implantation process is added to N-type The upper part of the guard ring and the upper part of the P-type lightly doped epitaxial layer between adjacent N-type guard rings forms a P-type lightly doped region to resist N-type ion pollution in the process, so that the isolation of the device periphery is not directly large The leakage path can maintain normal operation, thereby improving the performance of the device.

Description

A deep trench power MOS device structure and its preparation method

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a deep trench power MOS device structure and a preparation method thereof.

Background technique

With the continuous development of semiconductor technology, power MOS transistor devices have high input impedance, low loss, fast switching speed, no secondary breakdown, wide safe working area, good dynamic performance, and easy coupling with the front electrode to achieve high current, With the advantages of high conversion efficiency, gradually replacing bipolar devices has become the mainstream of power device development today.

At present, during the fabrication process of conventional deep trench power MOS devices, there will be free N-type ions in the clean room. The sources of N-type ions include the machines of each unit process, the blanks used in the production cycle, abnormal handling during machine maintenance, the factory environment, and the feeding of raw materials; N-type free ions will be produced during the process. Causes electrical drift of the device. Especially for P-type MOS tubes, after the body region (body) ion implantation and annealing process are completed, a certain concentration of free N-type ions will form a large A weak N-type interface will easily lead to the failure of the peripheral isolation structure in the terminal area of the MOS device, which will lead to relatively large leakage current and relatively low withstand voltage of the device, which is not expected by those skilled in the art.

Contents of the invention

In view of the above existing problems, the present invention discloses a deep trench power MOS device structure, including:

a P-type heavily doped substrate, and the P-type heavily doped substrate is divided into a cell region and a terminal region above the P-type heavily doped substrate;

a P-type lightly doped epitaxial layer disposed on the P-type heavily doped substrate;

N-type doped layer disposed on the P-type lightly doped epitaxial layer of the cell region;

a P-type source region layer disposed on the N-type doped layer;

A plurality of trenches in the cell region, which sequentially penetrate through the P-type source region layer and the N-type doped layer, and are arranged in the P-type lightly doped epitaxial layer;

A plurality of trenches in the termination region are arranged in the P-type lightly doped epitaxial layer of the termination region;

Several N-type guard rings are arranged in the P-type lightly doped epitaxial layer of the terminal region, and the upper part of the P-type lightly doped epitaxial layer between adjacent N-type guard rings is formed with P-type lightly doped Area.

The above-mentioned deep trench power MOS device structure, wherein the deep trench power MOS device structure further includes:

an insulating dielectric layer, disposed on the bottoms and sidewall surfaces of the plurality of cell region trenches and the plurality of terminal region trenches, and the upper surface of the P-type source region layer, the N-type guard ring Both the exposed upper surface and the exposed upper surface of the P-type lightly doped region are covered;

The polysilicon layer is arranged in the plurality of cell region trenches and the plurality of terminal region trenches, and the upper surface of the polysilicon layer is lower than the upper surface of the P-type source region layer.

In the above deep trench power MOS device structure, the height difference between the upper surface of the polysilicon layer and the upper surface of the P-type source region layer is 10-50 angstroms.

In the above deep trench power MOS device structure, the insulating dielectric layer is an oxide layer.

In the above-mentioned deep trench power MOS device structure, N-type body region contact regions are formed in the N-type doped layers between the trenches of adjacent cell regions.

In the above-mentioned deep trench power MOS device structure, wherein the deep trench power MOS device structure further includes several cell area contact holes located in the cell area and several terminal area contact holes located in the terminal area:

The plurality of cell region contact holes penetrate through the insulating dielectric layer located on the P-type source region layer and are disposed in the N-type body region contact region, and the plurality of terminal region contact holes penetrate through the terminal region The insulating dielectric layer above the trench in the region is set in the polysilicon layer in the trench in the terminal region.

The above-mentioned deep trench power MOS device structure, wherein the deep trench power MOS device structure further includes:

metal, filling the plurality of cell area contact holes and the plurality of terminal area contact holes.

The invention also discloses a method for preparing a deep trench power MOS device structure, comprising the following steps:

A semiconductor structure comprising a cell region and a terminal region is provided, the semiconductor structure comprising a P-type heavily doped substrate and a P-type lightly doped epitaxial layer on the P-type heavily doped substrate;

Performing a trench etching process on the semiconductor structure to form a plurality of cell region trenches in the P-type lightly doped epitaxial layer of the cell region, and forming a plurality of cell region trenches in the P-type lightly doped epitaxial layer of the terminal region forming a plurality of termination region trenches;

forming several N-type guard rings in the P-type lightly doped epitaxial layer in the terminal region;

forming a polysilicon layer in the plurality of trenches in the cell region and the trench in the terminal region;

Performing a body region implantation process to form an N-type body region doped region on the upper part of the P-type lightly doped epitaxial layer in the cell region;

Performing a P-type ion implantation process on the semiconductor structure to form a first P-type lightly doped region on the upper part of the N-type body doped region, and a P-type lightly doped region between adjacent N-type guard rings The upper part of the hetero-epitaxial layer forms a second P-type lightly doped region;

The subsequent preparation process of the deep trench power MOS device structure is continued.

The method for preparing the above-mentioned deep trench power MOS device structure, wherein the trench etching process includes:

forming a hard mask with a groove pattern on the P-type lightly doped epitaxial layer;

Etching the P-type lightly doped epitaxial layer by using the hard mask as a mask to form the trenches in the cell region and the trenches in the terminal region.

In the above-mentioned method for manufacturing a deep trench power MOS device structure, the hard mask is a stacked structure formed of oxide, nitride and oxide.

The above-mentioned method for preparing a deep trench power MOS device structure, wherein the step of forming a polysilicon layer in the trenches in the plurality of cell regions and the trenches in the termination region includes:

Prepare a gate dielectric layer to cover the bottoms and sidewall surfaces of the trenches in the plurality of cell regions and the trenches in the termination region, and cover the upper surface of the P-type lightly doped epitaxial layer;

Depositing a polysilicon layer to fill the trenches in the plurality of cell regions and the trenches in the terminal region, and cover the exposed upper surface of the gate dielectric layer;

Etching back the polysilicon layer, so that the upper surface of the polysilicon layer is lower than the upper surface of the P-type lightly doped epitaxial layer;

In the method for preparing a deep trench power MOS device structure above, the height difference between the upper surface of the polysilicon layer and the upper surface of the P-type lightly doped epitaxial layer is 10-50 angstroms.

The method for preparing the above-mentioned deep trench power MOS device structure, wherein the subsequent preparation process of the power MOS device includes the following steps:

A P-type source region is formed on the upper part of the N-type body region doped region between adjacent cell region trenches, and the P-type source region covers the first P-type lightly doped region;

forming an insulating dielectric layer on the semiconductor structure;

In order from top to bottom, etch the insulating dielectric layer, the P-type source region to the N-type body region doped region to form a contact hole in the cell region, and etch the terminal region The insulating dielectric layer above the trench stops in the polysilicon layer in the trench of the termination region to form a contact hole in the termination region.

A hole implantation process is performed on the N-type body doped region through the contact hole in the cell region, and a hole implantation process is performed on the polysilicon layer in the trench of the termination region through the contact hole in the termination region, so that the forming an N-type body region contact region around the bottom of the cell region contact hole and the terminal region contact hole;

Metal is deposited in the contact hole to form the power MOS device.

The above invention has the following advantages or beneficial effects:

The invention discloses a deep trench power MOS device structure and a preparation method thereof. After the body region ion implantation and annealing process are completed, a blanket P-type ion implantation process is added to the upper part of the N-type guard ring. and the upper part of the P-type lightly doped epitaxial layer between the adjacent N-type guard rings to form a P-type lightly doped region to resist N-type ion contamination in the process, so that the isolation of the device periphery is not possible because there is no direct large leakage path To maintain normal work, thereby improving the performance of the device.

Description of drawings

The invention and its characteristics, configurations and advantages will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. Like numbers designate like parts throughout the drawings. The drawings may not be drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

Fig. 1 is the schematic diagram of deep trench power MOS device structure in the embodiment of the present invention;

Fig. 2 is a flow chart of a method for a deep trench power MOS device structure in an embodiment of the present invention;

3 to 17 are schematic flow charts of the manufacturing method of the deep trench power MOS device structure in the embodiment of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Embodiment one:

As shown in Figure 1, this embodiment relates to a deep trench power MOS device structure disclosed by the present invention. Specifically, the deep trench power MOS device structure includes a P-type heavily doped upper part divided into a cell region and a terminal region. A heterogeneous substrate 100, a P-type lightly doped epitaxial layer 101 (such as a P-silicon layer) disposed on the P-type heavily doped substrate 100, disposed on the P-type lightly doped epitaxial layer 101 of the cell region The N-type doped layer 102, the P-type source region layer 103 disposed on the N-type doped layer 102, sequentially penetrate the P-type source region layer 103 and the N-type doped layer 102, and are disposed in the P Several trenches 104 in the cell region in the lightly doped epitaxial layer 101, several trenches 105 in the termination region in the lightly doped P-type epitaxial layer 101 disposed in the A number of N-type guard rings 106 in the layer 101, and a P-type lightly doped region 107 is formed on the upper part of the P-type lightly doped epitaxial layer 101 between adjacent N-type guard rings 106; further, the above-mentioned P-type heavily doped The substrate 100 includes a P-type heavily doped substrate (such as a P++ silicon wafer) 101 with a first doping concentration as a drain region and a P-type heavily doped substrate 1001 above the first doping concentration. A P-type heavily doped substrate (such as an epitaxial P+ silicon layer) 1002 with a second doping concentration, and the first doping concentration is greater than the second doping concentration.

In a preferred embodiment of the present invention, the above-mentioned deep trench power MOS device structure further includes a polysilicon layer 109 disposed in several trenches 104 in the cell area and several trenches 105 in the terminal area, and a polysilicon layer 109 disposed in the trenches 104 in the cell area and between the polysilicon layer 109 and between several termination region trenches 105 and the polysilicon layer 109 to isolate the polysilicon layer 109 from the inner wall surface of the cell region trench 104, the polysilicon layer 109 and the termination region trench 105 inner wall surface, and The upper surface of the P-type source region layer 103, the upper surface of the N-type guard ring 106, the upper surface of the polysilicon layer 109, and the exposed upper surface of the P-type lightly doped region 107 are all covered by the insulating dielectric layer 108, and the above-mentioned polysilicon layer 109 The upper surface of the upper surface of the P-type source region layer 103 is lower than the upper surface of the P-type source region layer 103, and the height difference between the upper surface of the polysilicon layer 109 and the upper surface of the P-type source region layer 103 is 10 to 50 angstroms (for example, 10 angstroms, 20 angstroms , 25 angstroms or 50 angstroms, etc.); further, the insulating dielectric layer 108 is an oxide layer.

In a preferred embodiment of the present invention, N-type body region contact regions 110 are formed in the N-type doped layer 102 between the trenches 104 of adjacent cell regions.

In a preferred embodiment of the present invention, the above-mentioned deep trench power MOS device structure further includes several cell area contact holes 111 located in the cell area and several terminal area contact holes 112 located in the terminal area: several cell area contact holes 111 is disposed in the N-type body region contact region 110 through the insulating dielectric layer 108 located on the P-type source region layer 103, and a plurality of termination region contact holes 112 are disposed in the insulating dielectric layer 108 disposed on the termination region trench 105. In the polysilicon layer 109 within the trench 105 in the termination region.

In a preferred embodiment of the present invention, the above-mentioned deep trench power MOS device structure further includes a metal layer 113 that fills the above-mentioned several cell region contact holes 111 and several terminal region contact holes 112 and covers the upper surface of the insulating dielectric layer 108 .

Embodiment two:

As shown in FIG. 2, this embodiment relates to a method for preparing a deep trench power MOS device structure. Specifically, the method includes the following steps:

Step S1, providing a semiconductor structure with a cell region and a terminal region, the semiconductor structure includes a P-type heavily doped substrate 200 and a P-type lightly doped epitaxial layer 201 on the P-type heavily doped substrate 200 ( Such as P-silicon layer); preferably, the P-type heavily doped substrate 200 includes a P-type heavily doped substrate 200 (N++ silicon layer) with a first doping concentration and the A P-type heavily doped substrate 2002 (N+ silicon layer) with a second doping concentration on the P-type heavily doped substrate 2001, and the first doping concentration is greater than the second doping concentration, as shown in FIG. 3 Structure.

Specifically, the formation method of the semiconductor structure includes: epitaxial P+ silicon layer and P- silicon layer above the P++ silicon wafer as the drain region, and wherein the P-type dopant ions can be boron (B), boron fluoride (BF2 ) in one or a combination.

Step S2, performing a trench etching process on the semiconductor structure to form a number of trenches 2031 in the cell region in the P-type lightly doped epitaxial layer 201 in the cell region, and in the P-type lightly doped epitaxial layer 201 in the terminal region A plurality of terminal area trenches 2032 are formed, such as the structures shown in FIGS. 4-5 .

In the embodiment of the present invention, the step S2 specifically includes the following steps:

Step S21, sequentially depositing an oxide layer (OX), a nitride layer (SIN) and an oxide layer (OX) on the above-mentioned semiconductor structure (also called (P-type lightly doped epitaxial layer 201) to form a hard The mask 202 , that is, the hard mask 202 is a stacked structure formed of oxide, nitride and oxide.

In step S22 , photolithography and etching are performed on the hard mask 202 to form the hard mask 202 with a groove pattern, such as the structure shown in FIG. 4 .

In step S23, the P-type lightly doped epitaxial layer 201 is etched using the hard mask 202 as a mask to form several cell region trenches 2031 in the P-type lightly doped epitaxial layer 201 in the cell region and the terminal Several terminal region trenches 2032 in the P-type lightly doped epitaxial layer 201 of the region, the structure shown in FIG. 5 .

Step S3, forming a plurality of N-type guard rings 204 in the P-type lightly doped epitaxial layer 201 in the terminal region; since the process of forming the plurality of N-type guard rings 204 is well known to those skilled in the art, it will not be repeated here. The structure shown in Figure 6.

Step S4 , forming a polysilicon layer 207 ′ in several cell region trenches 2031 and terminal region trenches 2032 , as shown in FIGS. 7-10 .

In the embodiment of the present invention, the step S4 specifically includes the following steps:

Step S41 , after removing the hard mask 202 , prepare a sacrificial oxide layer 205 covering the bottoms and sidewall surfaces of the plurality of cell region trenches 2031 and terminal region trenches 2032 , as shown in FIG. 7 .

Step S42, and after removing the sacrificial oxide layer 202, prepare a gate dielectric layer 206 covering the bottoms and sidewall surfaces of the trenches 2031 in the cell region and the trenches 2032 in the terminal region, and lightly doped with P-type The upper surface of the epitaxial layer 201 is covered. Preferably, the material of the gate dielectric layer 206 is oxide, as shown in FIG. 8 .

In step S43 , polysilicon 207 is deposited to fill the plurality 2031 and the termination region trench 2032 , and cover the exposed upper surface of the gate dielectric layer 206 , as shown in FIG. 9 .

Step S44, etching back the polysilicon 207, so that the upper surface of the formed polysilicon layer 207' is lower than the upper surface of the P-type lightly doped epitaxial layer 201; The height difference between the upper surfaces of the layers 201 is 10-50 angstroms (for example, 10 angstroms, 20 angstroms, 25 angstroms or 50 angstroms, etc.), as shown in the structure shown in FIG. 10 .

Step S5, performing a body region implantation process to form an N-type body region doped region 208 on the top of the P-type lightly doped epitaxial layer 201 in the cell region. Specifically, the ion implanted in the above body region implantation process can be phosphorus (P ), the body region implantation process includes the steps of body region photolithography, doping implantation and high temperature annealing. At this time, after the body region (body) ion implantation and annealing processes are completed, a very thin N-type interface 209 (N-- region) will be formed on the device surface of the terminal region, as shown in FIG. 11 .

Step S6, perform a P-type ion implantation process (blanket IMP) on the semiconductor structure completed in step S5 to form a first P-type lightly doped region 2101 on the upper part of the N-type body doped region 208, and form a first P-type lightly doped region 2101 in the adjacent N-type guard ring The upper part of the P-type lightly doped epitaxial layer 201 between 204 forms a second P-type lightly doped region 2102; the structure shown in FIG. 12 .

Step S7, continuing the subsequent manufacturing process of the deep trench power MOS device structure, such as the structures shown in FIGS. 13-17 .

In a preferred embodiment of the present invention, continuing the preparation process of subsequent power MOS devices includes the following steps:

Step S71, perform source region photolithography and P+ ion implantation (using XP mask), implanted ions can be one or a combination of B, BF, BF ₂ P, and then perform an annealing process to form trenches in adjacent cell regions The upper part of the N-type body region doped region 208 between 2031 forms a P-type source region (P+ type source region) 211, and the P-type source region 211 covers the first P-type lightly doped region 2101, that is, the original first P A part or all of the P-type source region 211 is formed by ion implantation into the P-type lightly doped region 2101 , as shown in FIG. 13 .

In step S72, an insulating dielectric layer 212 is formed on the semiconductor structure formed in step S71, the insulating dielectric layer 212 is filled with the cell region trench 2031 and the terminal region trench 2032, and covers the upper surface of the gate dielectric layer 206, as The structure shown in Figure 14.

Step S73, sequentially etch the insulating dielectric layer 212, the P-type source region 211 to the N-type body region doped region 208 in sequence from top to bottom to form the contact hole 2131 in the cell region, and etch the groove located in the terminal region The insulating dielectric layer 212 above the trench 2032 stops in the polysilicon layer 207 ′ in the termination region trench 2032 to form a termination region contact hole 2132 , as shown in FIG. 15 .

In step S74, a hole implantation process is performed on the N-type body doped region 208 through the cell region contact hole 2131, and a hole implantation process is performed on the polysilicon layer 207' in the termination region trench 2032 through the termination region contact hole 2132, so as to An N-type body region contact region 214 is formed around the bottom of the cell region contact hole 2131 and the terminal region contact hole 2132, that is, N++ ion implantation is performed in the body region contact region and other regions that do not require source region implantation, so that these regions are transformed into N-type , the implanted ions may be P, and high-temperature annealing is performed after ion implantation to form an N-type body region contact region, as shown in FIG. 16 .

Step S75, continue to deposit the metal 215 in the contact hole 2131 of the cell region and the contact hole 2132 of the terminal region, and perform photolithography and etching on the metal 215 to form a metal electrical contact, wherein the cell region is the entire piece of source-body contact metal Electrically isolated by the insulating dielectric layer 212 on the surface of the deep trench, the structure shown in Figure 17

It is not difficult to find that this embodiment is a method embodiment corresponding to the above embodiment of the deep trench power MOS device structure, and this embodiment can be implemented in cooperation with the above embodiment of the deep trench power MOS device structure. The relevant technical details mentioned in the above embodiments of the deep trench power MOS device structure are still valid in this embodiment, and will not be repeated here in order to reduce repetition. Correspondingly, the relevant technical details mentioned in this implementation manner can also be applied to the above embodiments of the deep trench power MOS device structure.

Those skilled in the art should understand that those skilled in the art can implement variations by combining the existing technology and the foregoing embodiments, and details are not described here. Such variations do not affect the essence of the present invention, and will not be repeated here.

The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and the devices and structures that are not described in detail should be understood to be implemented in a common manner in the art; Within the scope of the technical solution of the invention, many possible changes and modifications can be made to the technical solution of the present invention by using the methods and technical content disclosed above, or be modified into equivalent embodiments with equivalent changes, which does not affect the essence of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (13)

1. a preparation method of deep trench power MOS device structure, is characterized in that, comprises the steps: A semiconductor structure comprising a cell region and a terminal region is provided, the semiconductor structure comprising a P-type heavily doped substrate and a P-type lightly doped epitaxial layer on the P-type heavily doped substrate; Performing a trench etching process on the semiconductor structure to form a plurality of cell region trenches in the P-type lightly doped epitaxial layer of the cell region, and forming a plurality of cell region trenches in the P-type lightly doped epitaxial layer of the terminal region forming a plurality of termination region trenches; forming several N-type guard rings in the P-type lightly doped epitaxial layer in the terminal region; forming a polysilicon layer in the plurality of trenches in the cell region and the trench in the terminal region; Performing a body region implantation process to form an N-type body region doped region on the upper part of the P-type lightly doped epitaxial layer in the cell region; Perform a P-type ion implantation process on the semiconductor structure to form a first P-type lightly doped region on the upper part of the N-type body region doped region, and form a first P-type lightly doped region on the upper part of the N-type guard ring and adjacent to the N-type The upper part of the P-type lightly doped epitaxial layer between the guard rings forms a second P-type lightly doped region; The subsequent preparation process of the deep trench power MOS device structure is continued. 2. the preparation method of deep trench power MOS device structure as claimed in claim 1 is characterized in that, described trench etching process comprises: forming a hard mask with a groove pattern on the P-type lightly doped epitaxial layer; Etching the P-type lightly doped epitaxial layer by using the hard mask as a mask to form the trenches in the cell region and the trenches in the terminal region. 3 . The method for manufacturing a deep trench power MOS device structure according to claim 2 , wherein the hard mask is a stacked structure formed of oxide, nitride and oxide. 4 . 4. The preparation method of deep trench power MOS device structure as claimed in claim 2, is characterized in that, the described step of forming polysilicon layer in described several cell area trenches and terminal area trenches comprises: Prepare a gate dielectric layer to cover the bottoms and sidewall surfaces of the trenches in the plurality of cell regions and the trenches in the termination region, and cover the upper surface of the P-type lightly doped epitaxial layer; Depositing a polysilicon layer to fill the trenches in the plurality of cell regions and the trenches in the terminal region, and cover the exposed upper surface of the gate dielectric layer; The polysilicon layer is etched back so that the upper surface of the polysilicon layer is lower than the upper surface of the P-type lightly doped epitaxial layer. 5. the preparation method of deep trench power MOS device structure as claimed in claim 4 is characterized in that, the height difference between the upper surface of described polysilicon layer and the upper surface of described P-type lightly doped epitaxial layer is 10 to 50 Angstroms. 6. The preparation method of deep trench power MOS device structure as claimed in claim 2, is characterized in that, the preparation process of described continuation follow-up power MOS device comprises the steps: A P-type source region is formed on the upper part of the N-type body region doped region between adjacent cell region trenches, and the P-type source region covers the first P-type lightly doped region; forming an insulating dielectric layer on the semiconductor structure; In order from top to bottom, etch the insulating dielectric layer, the P-type source region to the N-type body region doped region to form a contact hole in the cell region, and etch the terminal region The insulating dielectric layer above the trench stops into the polysilicon layer in the trench of the termination region to form a contact hole in the termination region; A hole implantation process is performed on the N-type body doped region through the contact hole in the cell region, and a hole implantation process is performed on the polysilicon layer in the trench of the termination region through the contact hole in the termination region, so that the forming an N-type body region contact region around the bottom of the cell region contact hole and the terminal region contact hole; Metal is deposited in the contact hole to form the power MOS device. 7. A deep trench power MOS device structure, characterized in that it is formed by the preparation method according to any one of claims 1-6, and includes: a P-type heavily doped substrate, and the P-type heavily doped substrate is divided into a cell region and a terminal region above the P-type heavily doped substrate; a P-type lightly doped epitaxial layer disposed on the P-type heavily doped substrate; N-type doped layer disposed on the P-type lightly doped epitaxial layer of the cell region; a P-type source region layer disposed on the N-type doped layer; A plurality of trenches in the cell region, which sequentially penetrate through the P-type source region layer and the N-type doped layer, and are arranged in the P-type lightly doped epitaxial layer; a plurality of trenches in the termination region, arranged in the P-type lightly doped epitaxial layer of the termination region; Several N-type guard rings are arranged in the P-type lightly doped epitaxial layer of the terminal region, and the upper part of the N-type guard ring and the P-type lightly doped epitaxial layer between adjacent N-type guard rings A P-type lightly doped region is formed on the upper part. 8. The deep trench power MOS device structure according to claim 7, wherein the deep trench power MOS device structure further comprises: an insulating dielectric layer, disposed on the bottoms and sidewall surfaces of the plurality of cell region trenches and the plurality of terminal region trenches, and the upper surface of the P-type source region layer, the N-type guard ring Both the exposed upper surface and the exposed upper surface of the P-type lightly doped region are covered; The polysilicon layer is arranged in the plurality of cell region trenches and the plurality of terminal region trenches, and the upper surface of the polysilicon layer is lower than the upper surface of the P-type source region layer. 9 . The deep trench power MOS device structure according to claim 8 , wherein the height difference between the upper surface of the polysilicon layer and the upper surface of the P-type source region layer is 10˜50 angstroms. 10. The deep trench power MOS device structure according to claim 8, wherein the insulating dielectric layer is an oxide layer. 11 . The deep trench power MOS device structure according to claim 8 , wherein N-type body region contact regions are formed in the N-type doped layers between adjacent trenches of the cell region. 12 . 12. The deep trench power MOS device structure as claimed in claim 11, characterized in that, the deep trench power MOS device structure also comprises several cell area contact holes located in the cell area and located at the terminal Contact holes in several terminal areas of the area: The plurality of cell region contact holes penetrate through the insulating dielectric layer located on the P-type source region layer and are disposed in the N-type body region contact region, and the plurality of terminal region contact holes penetrate through the terminal region. The insulating dielectric layer above the trench in the region is set in the polysilicon layer in the trench in the terminal region. 13. The deep trench power MOS device structure according to claim 12, wherein the deep trench power MOS device structure further comprises: metal, filling the plurality of cell area contact holes and the plurality of terminal area contact holes.