CN106531745A - Thin film transistor array substrate and liquid crystal panel - Google Patents

Abstract

A thin film transistor array substrate, including multiple groups of thin film transistors and multiple RGB pixel units, one group of thin film transistors corresponds to one RGB pixel unit, each group of thin film transistors includes three thin film transistors respectively located in the first to third rows, three The thin film transistors respectively correspond to the R sub-pixel, G sub-pixel and B sub-pixel in the corresponding RGB pixel unit, and the aspect ratios of the conductive channels of all the thin film transistors in each row are not exactly the same, and are all within the preset ratio range , so that the total leakage current of the row is within the preset current range. Since the leakage current is only related to the width-to-length ratio of the conductive channel of the thin film transistor, the greater the width-to-length ratio W/L, the greater the drain current, and the smaller the width-to-length ratio, the smaller the drain current. Therefore, the present invention avoids burrs in the control signal output by the driving chip, improves the display quality of the liquid crystal panel, avoids noise, and reduces the power consumption of the display module. The invention also provides a liquid crystal panel.

Description

A kind of thin film transistor array substrate and liquid crystal panel

technical field

The invention relates to the field of display technology, in particular to a voltage output control circuit and a liquid crystal display.

Background technique

With the rapid development of the small and medium-sized electronic display industry, people have higher and higher requirements for the resolution and other quality of small and medium-sized LCD liquid crystal displays. The improvement of the display quality is closely related to the transmission rate of the display data and the integrity of the signal. For the current small and medium-sized LCD display screens, all the multiplexers are simultaneously turned on during the time period when the gates are turned on, so as to complete the charging of the RGB sub-pixels. But when all the multiplexers are turned on, it will cause the display module to instantly form a large pumping load on the LCD panel driver chip, which will cause glitches in the control signal output by the driver chip, which will not only affect the display quality, Noise is generated, and power consumption of the display module is also increased.

Contents of the invention

The object of the present invention is to provide a thin film transistor array substrate to improve display quality, avoid noise generation, and reduce power consumption of a display module.

Another object of the present invention is to provide a liquid crystal panel.

In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:

The present invention provides a thin-film transistor array substrate, including multiple sets of thin-film transistors and multiple RGB pixel units, one set of thin-film transistors corresponds to one RGB pixel unit, and each set of thin-film transistors includes three thin-film transistors respectively located in the first to third rows Transistors, the three thin film transistors correspond to the R sub-pixels, G sub-pixels and B sub-pixels in the corresponding RGB pixel units. within the proportional range, so that the total leakage current of this line is within the preset current range.

Wherein, in the first row of thin film transistors, the aspect ratios of the conduction channels of two adjacent thin film transistors are different.

Wherein, the first row of thin film transistors includes 2N thin film transistors, N is a natural number, and the length-to-width ratios of the 2Nth thin film transistors are the same.

Wherein, the aspect ratio of the conductive communication of the 2N-1th thin film transistor is the same, and is different from the aspect ratio of the conductive communication of the 2Nth thin film transistor.

Wherein, in the second row of thin film transistors, the aspect ratios of the conduction channels of two adjacent thin film transistors are different.

Wherein, the second row of thin film transistors includes 2N thin film transistors, N is a natural number, and the aspect ratio of the conductive communication of the 2Nth thin film transistors is the same.

Wherein, the aspect ratios of the conduction communication of the 2N-1th thin film transistors are the same.

Wherein, in the third row of thin film transistors, the aspect ratios of the conduction channels of two adjacent thin film transistors are different.

Wherein, the third row of thin film transistors includes 2N thin film transistors, N is a natural number, and the aspect ratios of the 2Nth thin film transistors are the same.

Wherein, the aspect ratios of the conduction communication of the 2N-1th thin film transistors are the same.

The present invention also provides a liquid crystal panel, including the above thin film transistor array substrate, liquid crystal and color filter substrate.

Embodiments of the present invention have the following advantages or beneficial effects:

The thin film transistor array substrate of the present invention includes multiple groups of thin film transistors and multiple RGB pixel units, one group of thin film transistors corresponds to one RGB pixel unit, and each group of thin film transistors includes three thin film transistors respectively located in the first to third rows, The three thin film transistors correspond to the R sub-pixels, G sub-pixels and B sub-pixels in the corresponding RGB pixel units, and the aspect ratios of the conductive channels of all the thin film transistors in each row are not exactly the same, and are all within the preset ratio range within, so that the total leakage current of the row is within the preset current range. Since the leakage current is only related to the width-to-length ratio of the conductive channel of the thin film transistor, the greater the width-to-length ratio W/L, the greater the drain current, and the smaller the width-to-length ratio, the smaller the drain current. Therefore, in this embodiment, by changing the aspect ratio of the thin film transistors in the corresponding row corresponding to the R sub-pixel, the G sub-pixel and the B sub-pixel, the total leakage current of the row can be adjusted within the preset current range (that is, to reduce the The size of the total leakage current of the row, but still greater than a current threshold), so that the driver chip will no longer form a large pumping load without affecting the display effect, and avoid glitches in the control signal output by the driver chip , thereby improving the display quality of the liquid crystal panel, avoiding noise, and reducing the power consumption of the display module.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a circuit diagram of a thin film transistor array substrate provided by a first solution embodiment of the present invention.

FIG. 2 is a cross-sectional top view of the thin film transistor in FIG. 1 .

FIG. 3 is a top view of the cross-sectional arrangement of the thin film transistor in FIG. 1 .

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In addition, the following descriptions of the various embodiments refer to the attached drawings to illustrate specific embodiments in which the present invention can be implemented. The directional terms mentioned in the present invention, for example, "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., only is to refer to the direction of the attached drawings. Therefore, the direction terms used are for better and more clearly explaining and understanding the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, use a specific orientation construction and operation, therefore, should not be construed as limiting the invention.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Ground connection, or integral connection; can be mechanical connection; can be directly connected, can also be indirectly connected through an intermediary, and can be internal communication between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more. If the term "process" appears in this specification, it not only refers to an independent process, but also includes in this term as long as it can realize the expected function of the process when it cannot be clearly distinguished from other processes. In addition, the numerical range represented by "-" in this specification means the range which includes the numerical value described before and after "-" as a minimum value and a maximum value, respectively. In the drawings, those with similar or identical structures are denoted by the same reference numerals.

Please refer to FIG. 1-FIG. 2 , the embodiment of the first solution of the present invention provides a thin film transistor array substrate 100 . The thin film transistor array substrate 100 includes multiple sets of thin film transistors 10 and multiple RGB pixel units 20, one set of thin film transistors 10 corresponds to one RGB pixel unit 20, and each set of thin film transistors includes three transistors respectively located in the first to third rows. Thin film transistors 11, 12 and 13, the three thin film transistors 11, 12 and 13 respectively correspond to the R sub-pixel, G sub-pixel and B sub-pixel in the corresponding RGB pixel unit, the length of the conductive channel of all the thin film transistors in each row The width ratios W/L are not all the same, and are all within a preset ratio range, so that the total leakage current of the row is within a preset current range.

It should be noted that the TFTs 11 in the first row correspond to all R sub-pixels, the TFTs 12 in the second row correspond to all G sub-pixels, and the TFTs 13 in the third row correspond to all R sub-pixels. Wherein, the total leakage current of each row is the sum of the leakage currents of each thin film transistor in the row. The leakage current of each thin film transistor is Id=0.5*K*W/L*(Vgs-Vth)^2 (wherein K and Vth are constants only related to the material of the thin film transistor), it can be seen that when the Vgs of the thin film transistor At a certain time, the drain current Id is only related to the width-to-length ratio W/L of the conductive channel of the thin film transistor. The larger the width-to-length ratio W/L, the greater the drain current Id, and the smaller the width-to-length ratio W/L Then the drain current Id is smaller. Therefore, in this embodiment, by changing the aspect ratio of the thin film transistors in the corresponding row corresponding to the R sub-pixel, the G sub-pixel and the B sub-pixel, the total leakage current of the row can be adjusted within the preset current range (that is, to reduce the The size of the total leakage current of the row, but still greater than a current threshold), so that the driver chip will no longer form a large pumping load without affecting the display effect, and avoid glitches in the control signal output by the driver chip , thereby improving the display quality of the liquid crystal panel, avoiding noise, and reducing the power consumption of the display module.

Referring to FIG. 3 , in this embodiment, in the first row of thin film transistors 11 , the aspect ratio W/L of the conductive channels of two adjacent thin film transistors 11 is different.

Specifically, the first row of thin film transistors 11 includes 2N thin film transistors, where N is a natural number, and the aspect ratio W/L of the conductive communication of the 2Nth thin film transistors 11 is the same.

It should be noted that, among the thin film transistors 11 in the first row, the aspect ratio W/L of the conduction channels of the thin film transistors 11 at the second, fourth, sixth and other even-numbered positions is the same.

The aspect ratio of the conductive communication of the 2N−1th thin film transistor 11 is the same, and different from the aspect ratio of the conductive communication of the 2Nth thin film transistor 11 .

It should be noted that, among the thin film transistors 11 in the first row, the aspect ratio W/L of the conduction channel of the thin film transistors 11 at the first, third, fifth, etc. odd-numbered positions is the same as that of the thin film transistors at the even-numbered positions. The aspect ratios of the conductive channels of 11 are different. In this way, in the first row of thin film transistors 11, the aspect ratio of the conductive channel of the thin film transistors 11 presents the arrangement state of large, small, large, small and repeats the above states in sequence, or presents small, large, small, large and repeats the above states in sequence. The order of the states. In this embodiment, the aspect ratio of the conductive communication of the 2Nth thin film transistor 11 is greater than the aspect ratio of the conductive communication of the 2N−1th thin film transistor 11 .

In this embodiment, the thin film transistors 12 in the second row are also the same in structure and arrangement as the thin film transistors 11 in the first row. Specifically:

In the second row of thin film transistors 12 , the aspect ratio W/L of the conduction channels of two adjacent thin film transistors 12 is different.

Specifically, the second row of thin film transistors 12 includes 2N thin film transistors, where N is a natural number, and the aspect ratio W/L of the conductive communication of the 2Nth thin film transistors 12 is the same.

It should be noted that, among the thin film transistors 12 in the second row, the aspect ratio W/L of the conduction channels of the thin film transistors 12 at the second, fourth, sixth and other even-numbered positions is the same.

The aspect ratio of the conductive communication of the 2N−1th thin film transistor 12 is the same, and different from the aspect ratio of the conductive communication of the 2Nth thin film transistor 12 .

It should be noted that, among the thin film transistors 12 in the second row, the aspect ratio W/L of the conduction channel of the thin film transistors 12 at the first, third, fifth, etc. odd-numbered positions is the same as that of the thin film transistors at the even-numbered positions. The aspect ratios of the conductive channels of 12 are different. In this way, in the second row of thin film transistors 12, the aspect ratio of the conductive channel of the thin film transistors 12 presents the arrangement state of large, small, large, small and repeats the above states in sequence, or presents small, large, small, large and repeats the above states in sequence. The order of the states.

In this embodiment, the structure and arrangement of the thin film transistors 13 in the third row are the same as those of the thin film transistors 11 and 12 in the first and second rows. Specifically:

In the third row of thin film transistors 13 , the aspect ratios of the conductive channels of two adjacent thin film transistors 13 are different.

It should be noted that, among the thin film transistors 13 in the third row, the aspect ratio W/L of the conductive channels of the thin film transistors 13 at the second, fourth, sixth and other even-numbered positions is the same.

The aspect ratio of the conductive communication of the 2N−1th thin film transistor 13 is the same, and different from the aspect ratio of the conductive communication of the 2Nth thin film transistor 13 .

It should be noted that, among the thin film transistors 13 in the third row, the aspect ratio W/L of the conduction channel of the thin film transistors 13 at the first, third, fifth, etc. odd-numbered positions is the same as that of the thin film transistors at even-numbered positions The aspect ratios of the conductive channels of 13 are different. In this way, in the second row of thin film transistors 13, the aspect ratio of the conductive channel of the thin film transistors 13 presents the arrangement state of large, small, large, small and repeats the above states in sequence, or presents small, large, small, large and repeats the above states in sequence. The order of the states.

In other embodiments, since the thin film transistors in each row are independent of each other, the thin film transistors 11 - 13 in the first to third rows may be different in structure and arrangement. As long as it is satisfied, the aspect ratio W/L of the conduction channel of all thin film transistors in each row is not exactly the same, and they are all within the preset ratio range, so that the total leakage current of the row is within the preset current range. Can.

The embodiment of the second solution of the present invention provides a liquid crystal panel 400 . The liquid crystal panel 400 includes a thin film transistor array substrate, a liquid crystal 410 and a color filter substrate 420 . Wherein, the thin film transistor array substrate is the thin film transistor array substrate 100 provided in the first solution embodiment above. Since the thin film transistor array substrate 100 has been described in detail in the first solution, it will not be repeated here.

In this embodiment, the liquid crystal panel 400 includes the thin film transistor array substrate 100 . The thin film transistor array substrate 100 includes multiple sets of thin film transistors 10 and multiple RGB pixel units 20, one set of thin film transistors 10 corresponds to one RGB pixel unit 20, and each set of thin film transistors includes three transistors respectively located in the first to third rows. Thin film transistors 11, 12 and 13, the three thin film transistors 11, 12 and 13 respectively correspond to the R sub-pixel, G sub-pixel and B sub-pixel in the corresponding RGB pixel unit, the length of the conductive channel of all the thin film transistors in each row The width ratios W/L are not all the same, and are all within a preset ratio range, so that the total leakage current of the row is within a preset current range.

It should be noted that the TFTs 11 in the first row correspond to all R sub-pixels, the TFTs 12 in the second row correspond to all G sub-pixels, and the TFTs 13 in the third row correspond to all R sub-pixels. Wherein, the total leakage current of each row is the sum of the leakage currents of each thin film transistor in the row. The leakage current of each thin film transistor is Id=0.5*K*W/L*(Vgs-Vth)^2 (wherein K and Vth are constants only related to the material of the thin film transistor), it can be seen that when the Vgs of the thin film transistor At a certain time, the drain current Id is only related to the width-to-length ratio W/L of the conductive channel of the thin film transistor. The larger the width-to-length ratio W/L, the greater the drain current Id, and the smaller the width-to-length ratio W/L Then the drain current Id is smaller. Therefore, in this embodiment, by changing the aspect ratio of the thin film transistors in the row corresponding to the R sub-pixel, the G sub-pixel and the B sub-pixel, the total leakage current of the row can be reduced, but it is still greater than a current threshold. In this way, on the premise of not affecting the display effect, the driver chip no longer forms a large pumping load, and avoids glitches in the control signal output by the driver chip, thereby improving the display quality of the LCD panel, avoiding noise, and reducing Indicates the power consumption of the display module.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples" or "some examples" mean specific features described in connection with the embodiment or example, A structure, material or characteristic is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The implementation methods described above do not constitute a limitation to the scope of protection of the technical solution. Any modifications, equivalent replacements and improvements made within the spirit and principles of the above implementation methods shall be included in the protection scope of the technical solution.

Claims (11)

1. a kind of thin-film transistor array base-plate, it is characterised in that：The thin-film transistor array base-plate includes that many cluster films are brilliant Body pipe and multiple rgb pixel units, a cluster film transistor one rgb pixel unit of correspondence, each cluster film transistor include Respectively positioned at three thin film transistor (TFT)s of the first to the third line, three thin film transistor (TFT)s are corresponded in corresponding rgb pixel unit respectively R sub-pixels, G sub-pixel and B sub-pixels, per a line in all of thin film transistor (TFT) conducting channel the incomplete phase of length-width ratio Together, and in the range of preset ratio, so that total leakage current of the row is in the range of predetermined current.

2. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that in the first row thin film transistor (TFT), phase The length-width ratio of the conducting channel of adjacent two thin film transistor (TFT)s is different.

3. thin-film transistor array base-plate as claimed in claim 2, it is characterised in that the first row thin film transistor (TFT) includes 2N Thin film transistor (TFT), N is natural number, and the length-width ratio of the conductive communication of 2N thin film transistor (TFT) is identical.

4. thin-film transistor array base-plate as claimed in claim 3, it is characterised in that the conduction of 2N-1 thin film transistor (TFT) The length-width ratio of communication is identical, and different from the length-width ratio of the conductive communication of 2N thin film transistor (TFT).

5. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that in the second row thin film transistor (TFT), phase The length-width ratio of the conducting channel of adjacent two thin film transistor (TFT)s is different.

6. thin-film transistor array base-plate as claimed in claim 5, it is characterised in that the second row thin film transistor (TFT) includes 2N Thin film transistor (TFT), N is natural number, and the length-width ratio of the conductive communication of 2N thin film transistor (TFT) is identical.

7. thin-film transistor array base-plate as claimed in claim 6, it is characterised in that the conduction of 2N-1 thin film transistor (TFT) The length-width ratio of communication is identical.

8. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that in the third line thin film transistor (TFT), phase The length-width ratio of the conducting channel of adjacent two thin film transistor (TFT)s is different.

9. thin-film transistor array base-plate as claimed in claim 8, it is characterised in that the third line thin film transistor (TFT) includes 2N Thin film transistor (TFT), N is natural number, and the length-width ratio of the conductive communication of 2N thin film transistor (TFT) is identical.

10. thin-film transistor array base-plate as claimed in claim 9, it is characterised in that 2N-1 thin film transistor (TFT) is led The length-width ratio that electricity is linked up is identical.

11. a kind of liquid crystal panels, including the thin-film transistor array base-plate as described in any one of claim 1-10, liquid crystal and coloured silk Ilm substrate.