CN106531684B - A method of forming self-aligned contacts - Google Patents

Abstract

The present invention provides a method for forming a self-aligned contact, comprising: providing a substrate on which a gate stack and spacers on both sides of the gate stack are formed, and the spacers on both sides of the spacer are forming an active/drain region and a metal silicide layer on the bottom; forming a blocking mask layer and a first blocking mask layer outside the sidewall spacer and above the blocking mask layer in sequence two sidewall spacers; forming an interlayer dielectric layer, and performing surface planarization until the gate stack is exposed; removing the second sidewall spacer and the blocking mask layer connected to the second sidewall spacer to expose the The metal silicide layer; filling the groove with metal and planarizing until the gate stack is exposed, can effectively solve the problem that the distance between the gate and the contact cannot be accurately and easily reduced in the prior art.

Description

A method of forming self-aligned contacts

technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a self-aligned contact portion.

Background technique

In the manufacturing process of the integrated circuit, a tungsten plug is usually used as a contact part to realize the electrical connection between the complementary metal oxide semiconductor (CMOS) and the outside.

With the continuous development of integrated circuit technology, the size of the device is continuously reduced, which makes the alignment lithography between different layers more and more difficult. One of the problems caused by gate pitch reduction is the formation of contact-to-gate (CTG) shorts once the contacts are misaligned. This CTG short actually destroys the MOS transistor. As transistor gate pitches have shrunk below 45 nanometers, CTG shorts have become one of the major yield limiting factors. Current methods for reducing CTG shorting include controlled positioning and the use of contacts with smaller critical dimensions. However, as the gate pitch has been reduced, precise positioning requirements have become very difficult. For example, transistors with gate pitches less than or equal to 100 nm require less than 10 nm layer positioning control and critical dimension (CD) control to achieve a manufacturable process window. Therefore, the preparation of the contact portion is very difficult.

In addition, with the research and application of the three-dimensional device structure of fin field effect transistors (Fin-FETs), the gate spacing of transistors has been reduced to less than 22 nanometers, and how to reduce the current delay has become an urgent problem to be solved. A feasible method is to reduce the distance between the gate and the contact by reducing the distance between the gate and the contact, however, the distance between the gate and the contact is reduced by conventional photolithography (Litho) process, reactive ion etching (RIE) process, etc. Distance has become very difficult.

SUMMARY OF THE INVENTION

The present invention provides a method for forming a self-aligned contact portion to solve the problem that the distance between the gate and the contact portion cannot be accurately and easily reduced in the prior art.

The present invention provides a method of forming a self-aligned contact, comprising:

A substrate is provided on which a gate stack and spacers located on both sides of the gate stack are formed, and source/drain regions and a space between the source/drain regions are formed on the substrate on both sides of the spacers a metal silicide layer on the

forming a blocking mask layer and an auxiliary sidewall spacer outside the sidewall spacer and above the blocking mask layer in sequence;

forming an interlayer dielectric layer and performing surface planarization until the gate stack is exposed;

removing the auxiliary spacer and the blocking mask layer connected to the auxiliary spacer to expose the metal silicide layer;

The recesses are filled with metal and planarized until the gate stack is exposed.

Preferably, the gate stack sequentially includes: a dielectric layer on the substrate, a gate electrode layer on the dielectric layer, and a hard mask layer on the gate electrode layer.

Preferably, the method further includes:

removing the gate stack to form a metal gate groove;

forming a metal gate dielectric layer in the metal gate groove;

filling the metal gate groove with metal;

Planarization is performed until the sidewalls are exposed.

Preferably, the filling the groove with metal and performing planarization until the gate stack is exposed comprises:

Fill the groove with filler, and perform planarization until the gate electrode layer is exposed, the selective etching ratio of the filler to the gate electrode layer is ≥50:1, and the ratio of the filler to the gate dielectric layer is greater than or equal to 50:1. Select the etching ratio ≥50:1;

removing the gate stack, and forming a metal gate dielectric layer, and the selective etching ratio of the metal gate dielectric layer to the filler is ≥50:1;

removing the filler;

The grooves are filled with metal and planarized until the sidewalls are exposed.

Preferably, the filler is amorphous carbon.

Preferably, the removing the auxiliary spacer and the blocking mask layer in contact with the auxiliary spacer, and exposing the metal silicide layer comprises:

removing the auxiliary spacer, the gate stack and the blocking mask layer in contact with the auxiliary spacer, exposing the metal silicide layer and the substrate under the gate stack;

A metal gate dielectric layer is formed.

Preferably, the forming the metal gate dielectric layer includes:

depositing a high-k dielectric layer;

The high-k dielectric layer outside the gate stack is removed.

Preferably, fins are further formed on the substrate, the gate stack is located above the fins in a direction perpendicular to the fins, and the source/drain regions are located on the fins on both sides of the spacers and the metal silicide layer over the source/drain regions.

Preferably, the material of the auxiliary spacer includes any one of the following: polysilicon and amorphous silicon.

Preferably, the contact portion includes any one or more of the following layers: an adhesive layer, a metal work function layer, a diffusion barrier layer, and a metal gate electrode layer.

The present invention provides a method for forming a self-aligned contact, the method comprising: providing a gate stack, sidewall spacers on both sides of the gate stack, source/drain regions, and a metal silicide layer over the source/drain regions substrate, and then sequentially form a blocking mask layer and an auxiliary spacer thereon, which serves as a sacrificial layer for forming a contact, and then form an interlayer dielectric layer, and remove the auxiliary spacer and its auxiliary spacer by removing the auxiliary spacer. Adjoining block mask layers to expose the metal silicide, and finally filled with metal and planarized to form self-aligned contacts. Since the auxiliary sidewall outside the sidewall is conformally formed in this process, the position of the auxiliary sidewall is the position of the contact portion, and there is no need to define the position of the contact portion by photolithography; and the thickness of the sidewall can be adjusted precisely by adjusting the thickness of the sidewall. The distance between the contact portion and the gate effectively solves the problem in the prior art that the distance between the gate and the contact portion cannot be accurately and simply reduced.

Further, the method provided by the present invention can also adjust the size of the contact portion by adjusting the thickness of the auxiliary sidewall.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the accompanying drawings required in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only described in the present invention. For some of the embodiments, those of ordinary skill in the art can also obtain other drawings according to these drawings.

FIG. 1 is a flowchart of a method for forming a self-aligned contact according to an embodiment of the present invention;

2A to 2J are schematic cross-sectional structural diagrams of a process of forming a self-aligned contact portion according to Embodiment 1 of the present invention;

3A to 3D are schematic cross-sectional structural diagrams of a process of forming a self-aligned contact portion according to Embodiment 2 of the present invention;

4A to 4H are schematic cross-sectional structural diagrams of a process of forming a self-aligned contact portion according to Embodiment 3 of the present invention;

5A to 5E are schematic cross-sectional structural diagrams of a process of forming a self-aligned contact portion according to Embodiment 4 of the present invention;

6A to 6C are three-dimensional schematic diagrams of a process of forming a self-aligned contact portion according to Embodiment 5 of the present invention.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but not to be construed as a limitation of the present invention.

Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, the present disclosure provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, structures described below in which a first feature is "on" a second feature may include embodiments in which the first and second features are formed in direct contact, or may include additional features formed between the first and second features example, such that the first and second features may not be in direct contact.

In order to better understand the present invention, the process of forming a self-aligned contact in the prior art will be briefly introduced below. Taking a planar device as an example, the main steps include: first, define the active elements of nMOS and pMOS transistors through a double well process Then, isolation between the active regions of the transistor is formed by a shallow trench isolation process; then, a gate stack is formed on the surface of the substrate by a polysilicon gate structure process; Next, a lightly doped drain implant process is used to define the source/drain of the transistor Then, a sidewall spacer is formed around the gate stack, and a source/drain implantation process is performed to form a source/drain region; then, a metal silicide layer is formed on the source and drain regions by a self-alignment process to reduce contact resistance; Then, an interlayer dielectric layer is formed by a spin coating method, a chemical mechanical planarization CMP process, etc.; then, a through hole is formed in the ILD layer by a photolithography process and an etching process to expose the source/drain regions, and a chemical vapor deposition method is used. and CMP process to form tungsten plugs in the vias as contacts. As the size of the device becomes smaller, it has become difficult to define the position of the tungsten plug through the photolithography process; in addition, as the size of the device decreases, how to reduce the distance between the gate and the contact to reduce the current delay also appear more important.

The present invention provides a method for forming a self-aligned contact part, by presetting an auxiliary spacer near the spacer in the ILD layer, the auxiliary spacer is a sacrificial layer used to form the contact part, and then removing the auxiliary spacer To expose the source/drain regions, and to form self-aligned contacts by depositing metal and CMP processes; since there is no need to define the position of the contact by photolithography in this process, and the thickness of the sidewall spacer can be adjusted to precisely adjust the contact and the contact. The distance between the gates can also be adjusted by adjusting the thickness of the auxiliary spacer to adjust the size of the contact portion, thus effectively solving the problem that it is difficult to reduce the distance between the gate and the contact portion in the prior art.

In order to better understand the technical solutions and technical effects of the present invention, a detailed description will be given below with reference to the flowchart and specific embodiments. shown in 6C.

In the present invention, the substrate 100 may be a semiconductor substrate, such as: Si substrate, Ge substrate, SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) Wait. In other embodiments, the substrate 100 may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., may also be a stacked structure, such as Si/SiGe, etc., and may also be other Epitaxial structures, such as SGOI (silicon germanium on insulator), etc.

In the present invention, a device structure has been formed on the substrate 100, and the device structure may include: a gate stack 101, spacers 102 on both sides of the gate stack 101, and source/drain regions 103; in addition, the device structure It may also include: fins 1001 formed on the surface of the substrate 100 for making Fin-FETs.

In the present invention, the gate of the gate stack 101 may be a polysilicon gate or a metal gate 109; correspondingly, the preparation process of the metal gate may be a gate-before process or a gate-last process. Specifically, the gate stack 101 sequentially includes: a gate dielectric layer 1011 on the substrate 100 , a gate electrode layer 1012 on the gate dielectric layer 1011 , and a hard mask layer on the gate electrode layer 1012 1013. The gate dielectric layer 1011 on the substrate 100 can be a dielectric layer such as silicon dioxide; the hard mask layer 1013 can be used as a grinding stop layer for the interlayer dielectric layer 106, for example, the hard mask layer It is a material with a smaller removal rate than the material of the ILD layer 106, such as a silicon nitride film.

When the gate stack 101 is a metal gate, a high-k material may be used in the dielectric layer 1011 above the substrate 100 , wherein, examples of the high-k material include but are not limited to hafnium oxide, silicon hafnium oxide, oxide Lanthanum, Lanthanum Alumina, Zirconium Oxide, Silicon Zirconium Oxide, Tantalum Oxide, Titanium Oxide, Titanium Barium Strontium Oxide, Titanium Barium Oxide, Titanium Strontium Oxide, Yttrium Oxide, Aluminum Oxide, Tantalum Scandium Oxide and Lead Niobate. In some embodiments, the thickness of the metal gate dielectric layer 108 may be between about 1 angstrom and about 50 angstroms. In another embodiment, additional processes, such as an annealing process, may be performed on the metal gate dielectric layer 108 in order to improve the quality of the formed high-k material.

It should be noted that the metal gate 109 may be composed of at least a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the metal gate 109 may be composed of two or more metal layers, wherein at least one of the metal layers is a metal work function layer and at least one of the metal layers is a fill metal layer.

For PMOS transistors, metals that can be used for metal gate 109 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (eg, ruthenium oxide). The P-type metal work function layer will allow the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for metal gate 109 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, among others. Metal carbides. The N-type metal work function layer will allow the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV.

In the present invention, the spacers 102 may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the spacers 102 are well known in the art and typically include deposition and etching process steps. In particular, the sidewall spacers 102 in the present invention not only serve as shielding layers for heavily doped source/drain regions 103 , but also serve as isolation between the gate stack 101 and the contact portion 107 . In order to ensure the isolation effect, the sidewalls 102 may have a laminated structure.

The blocking mask layer 104 is mainly used as an etch stop layer for the auxiliary spacer 105 , that is, the selective etching ratio of the blocking mask layer 104 and the auxiliary spacer 105 is ≥50:1, and the blocking mask layer 104 The material can be silicon oxide, silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN), any other oxide, etc., which satisfy the selective etching ratio requirement.

The auxiliary spacers 105 may be formed using deposition and etching processes similar to the fabrication of the spacers 102 . For example, a conformal layer may be deposited over the block mask layer 104, thereby creating a conformal layer along the block mask layer 104 and the gate stack 101, and then dry etching is performed to form an auxiliary layer Side wall 105. It should be noted that the selective etching ratio of the auxiliary spacer 105 to the sidewall 102 is ≥50:1, and the selective etching ratio of the auxiliary spacer 105 to the ILD layer 106 is ≥50:1. The shape layer can be amorphous silicon, polysilicon, silicon oxide, silicon nitride, amorphous carbon (α-C), silicon oxynitride (SiON), carbon-doped silicon oxynitride (SiOCN) that meet the above-mentioned selective etching ratio requirements. ), any other oxide, any other nitride, or any low-k dielectric material. Next, an anisotropic etching process is used to remove excess conformal layer from other regions except the auxiliary spacers 105 to form the auxiliary spacers 105 . It should be noted that in this process, etching may be continued to remove the exposed blocking mask layer 104 .

The source/drain regions 103 are formed in the substrate adjacent to the spacers 102 . For each MOS transistor, one diffusion region 106 adjacent to the gate stack 101 functions as a source region, and another diffusion region 106 adjacent to the gate stack 101 functions as a drain region. The source/drain regions 103 are formed by methods known in the art, such as ion implantation, epitaxial deposition, and the like.

One or more ILD layers 106 are deposited over the MOS transistors. ILD layer 106 may be formed using dielectric materials such as low-k dielectric materials that are commonly used in integrated circuit structures. Specifically, examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), doped carbon oxides (CDO), silicon nitride, organic polymers such as octafluorocyclobutane or polytetrafluoroethylene, Fluorosilicate glass (FSG) and organosilicates such as silsesquioxane, siloxane or organosilicate glass. The ILD layer 106 layer may include pores or other voids, eg, a loose silicon dioxide layer formed by oblique angle growth, etc., to further reduce its dielectric constant.

In addition, a metal silicide layer 1031 is also formed on the source/drain regions 103 . To form the metal silicide layer 1031, a conventional metal deposition process, such as a sputter deposition process or an atomic layer deposition (ALD) process, may be used to form a conformal metal layer on the source/drain regions 103. Typically, the metal layer may include one or more of nickel, cobalt, tantalum, titanium, tungsten, platinum, palladium, aluminum, yttrium, erbium, ytterbium, or any other metal that is a good candidate for suicide. Subsequently, an annealing process may be performed to cause the metal to react with the silicon on the surface of the source/drain regions 103 and form the metal silicide layer 1031 . Any unreacted metals can be selectively removed using known processes. The metal silicide layer 1031 reduces the contact resistance between the contacts 107 and the source/drain regions 103 to be formed later. Of course, the metal silicide layer 1031 can also be formed only on the surface of the source/drain region 103 under the auxiliary spacer 105. For example, after removing the auxiliary spacer 105 to expose part of the source/drain region 103, the A metal layer for forming the metal silicide layer 1031 is deposited on the surface of the bottom 100, the material of the metal layer is as described above, and then an annealing process can be performed to make the metal react with the silicon on the surface of the source/drain region 103 and form the metal silicide layer 1031, and finally Any unreacted metal may be selectively removed using known processes to form a metal silicide layer 1031 on the surface of the source/drain regions 103 under the auxiliary spacers 105 . It should be noted that with the metal silicide layer 1031 formed by the first method described above, a relatively wide metal silicide layer 1031 can be formed to provide, for example, lower contact resistance to reduce the total contact between the contact portion 107 and the source/drain regions 103 resistance. For the metal silicide layer 1031 formed by the above-mentioned second method, since only less source/drain regions 103 are exposed, relatively less metal silicide layer 1031 is generated during the formation of the metal silicide layer 1031 .

In addition, in order to further prevent the particles of the contact portion 107 from diffusing to the sidewall spacer 102 or to improve the isolation effect between the contact portion 107 and the gate stack 101 , one or more layers of thin films exist on the surface of the contact portion 107 as a diffusion barrier. The diffusion barrier layer can be a high melting point metal such as titanium and platinum, and a substance with a high melting point such as titanium nitride.

Particularly, when the fin 1001 and the gate stack 101 are formed on the substrate 100, the gate stack 101 is located above the fin 1001 in a direction perpendicular to the fin 1001, and the source/drain regions 103 are located on the side On the fins 1001 on both sides of the wall 102 and the metal silicide layer 1031 on the source/drain regions 103 . Then, a blocking mask layer 104 and an auxiliary spacer 105 located outside the spacer 102 and above the blocking mask layer 104 are sequentially formed according to claim 1, and the following steps are used to form the contact portion 107 .

Example 1

In this embodiment, the substrate 100 is a silicon substrate, the gate is a polysilicon gate, the material of the auxiliary spacer 105 is polysilicon, and the final device is a planar device. A method of forming self-aligned contacts 107 includes:

Step S01 , a substrate 100 is provided, on which a gate stack 101 and spacers 102 located on both sides of the gate stack 101 are formed, and active/drain is formed on the substrate 100 on both sides of the spacer 102 region 103 and a metal silicide layer 1031 over the source/drain regions 103, as shown in FIGS. 2A-2B.

In this embodiment, the gate stack 101 includes: a gate dielectric layer 1011 on the substrate 100 , a gate electrode layer 1012 on the gate dielectric layer 1011 , and a hard mask on the gate electrode layer 1012 Layer 1013. The process of forming the gate stack 101 mainly includes: first, defining the active region of the MOSFET (shown in the figure), usually using high-energy, high-dose implantation, about one micron deep into the epitaxial layer. Well implantation determines the threshold operating voltage of the transistor and avoids problems such as latch-up effects; then isolation is formed between the active regions by a shallow trench isolation process (not shown); then, the active region is formed by a polysilicon gate structure process A gate stack 101 is formed on the top; then, a lightly doped drain implantation process is performed to define the source and drain regions of the transistor; then, a sidewall spacer 102 is formed around the gate stack 101, and source/drain is performed using the sidewall spacer 102 as a mask An implantation process is performed to form the source/drain regions 103 ; finally, a metal silicide layer 1031 is formed on the surface of the source/drain regions 103 .

In a specific embodiment, taking the 0.25 μm process as an example, the silicon substrate from which the surface particles, organic matter, etc. contamination and natural oxide layer have been removed is placed in a high-temperature (1000° C.) furnace, and the surface of the silicon substrate is oxidized through an oxidation reaction. An oxide layer with a thickness of about 150 angstroms is formed, followed by n-well implantation and p-well implantation in sequence, wherein the n-well implantation adopts high-energy implantation, for example, the implantation energy is about 200KeV to produce a well with a junction depth of about 1 μm; Before, a mask layer needs to be deposited, and the active regions are defined by a photolithography process, which will not be described in detail here; then isolation between the active regions is formed by the existing shallow trench isolation process; A silicon dioxide layer with a thickness of about 20-50 angstroms is formed on the surface of the substrate 100, and the silicon dioxide layer is used to form a gate dielectric layer 1011; A polysilicon layer is used to form the gate electrode layer 1012; then, a silicon nitride film of 3000 angstroms is deposited as the hard mask layer 1013 of the gate stack 101, and the position of the gate is defined by a photolithography process, and etching is performed to form the gate stack 101; then, define the source/drain regions 103 of the transistor through two photolithography processes and two lightly doped drain implantation processes; The silicon nitride film outside the gate sidewall is etched and removed until the source/drain region 103 is exposed to form the sidewall spacer 102; then, the source/drain implantation process is performed to form the source/drain region 103; finally, titanium is deposited on the surface of the substrate 100 layer, through annealing, the silicon on the surface of the source/drain region 103 in contact with the titanium layer reacts with titanium to form titanium silicide, and the unreacted titanium is chemically etched away.

In step S02 , a blocking mask layer 104 and an auxiliary spacer 105 located outside the sidewall spacer 102 and above the blocking mask layer 104 are sequentially formed, as shown in FIG. 2C to FIG. 2E .

In this embodiment, the blocking mask layer 104 is a silicon dioxide layer, the material of the auxiliary spacer 105 is polysilicon material, and the selective etching ratio of the auxiliary spacer 105 to the blocking mask layer 104 is greater than 50 : 1, that is, the blocking mask layer 104 serves as an etch stop layer for the auxiliary spacer 105 . Of course, the auxiliary spacers 105 may also be amorphous silicon. It should be noted that the auxiliary spacer 105 is used to form the sacrificial layer of the contact portion 107 , and the ILD layer 106 has been formed before the auxiliary spacer 105 is removed. Therefore, in order to reduce the impact on the ILD layer 106 when the auxiliary spacer 105 is removed damage, the selective etching ratio of the auxiliary spacer 105 to the ILD layer 106 is greater than 50:1.

In a specific embodiment, a silicon dioxide film with a thickness of about 2-4 nm is formed on the substrate 100 by chemical vapor deposition (PECVD) as the blocking mask layer 104; then, by low pressure chemical vapor deposition (low pressure chemical vapor deposition) Vapor deposition, LPCVD) to form a polysilicon layer with a thickness of about 5000 angstroms on the silicon dioxide film; then, the polysilicon layer other than the gate sidewalls is removed by anisotropic etching to form auxiliary spacers 105 . It should be noted that, after the auxiliary spacers 105 are formed, etching may be continued to remove the silicon dioxide exposed on the surface of the substrate 100, depending on the specific situation. In addition, the thickness of the above-mentioned polysilicon layer determines the width of the contact portion 107 , and the thickness of the polysilicon layer can be determined according to the required size of the contact portion 107 .

Step S03 , forming an interlayer dielectric layer 106 and performing surface planarization until the gate stack 101 is exposed, as shown in FIGS. 2F to 2G .

In this embodiment, the interlayer dielectric layer 106 may be one or more ILD layers 106 formed by chemical vapor deposition, spin coating, High Aspect Ratio Process (HARP), etc., refer to the above ILD Layer 106 details the information.

The hard mask layer 1013 of the gate stack 101 and silicon dioxide have a large difference in the removal rate of grinding, and the removal rate of the hard mask layer 1013 is lower, and the hard mask layer 1013 can be used as a CMP stop layer. Since the auxiliary spacer 105 is formed on the silicon dioxide layer, and the silicon dioxide layer is formed on the gate stack 101 , the height of the spacer 102 formed in step S03 is higher than that of the gate stack 101 . When CMP stops on the hard mask layer 1013, the auxiliary spacers 105 and silicon dioxide are both exposed.

In a specific embodiment, a silicon dioxide layer with a thickness greater than the height of the gate stack 101 is deposited on the surface of the substrate 100 by a chemical vapor deposition method; then, a CMP process is performed until the gate stack 101 is exposed.

Step S04 , removing the auxiliary spacer 105 and the blocking mask layer 104 in contact with the auxiliary spacer 105 to expose the metal silicide layer 1031 , as shown in FIG. 2H .

In this embodiment, the auxiliary spacer 105 is a sacrificial layer used to form the contact portion 107 , and the selective etching ratio of the auxiliary spacer 105 to the ILD layer 106 is greater than or equal to 50:1. Therefore, after removing the auxiliary spacer 105, the structure of the ILD layer 106 will not be damaged; in addition, the top of the gate stack 101 is a hard mask layer 1013, and the selective etching ratio of the hard mask layer 1013 and the auxiliary spacer 105 is ≥50:1 , the hard mask layer 1013 can protect the gate stack 101 from being damaged. After removing the auxiliary spacer 105, the blocking mask layer 104 is exposed. The selective etching ratio of the blocking mask layer 104 and the auxiliary spacer 105 is ≥50:1. Therefore, the blocking mask layer 104 is used as the The etch stop layer of the auxiliary spacer 105 is used to protect the source/drain region 103 and the metal silicide layer 1031 on the surface of the source/drain region 103 from being damaged when the auxiliary spacer 105 is removed. The removal of the auxiliary spacer 105 will not cause the contact resistance between the contact portion 107 and the source/drain region 103 to increase or the electrical performance of the device to be affected.

In a specific implementation, the auxiliary spacer 105 is removed by wet etching with a 40% potassium hydroxide solution; then, the exposed blocking mask layer 104 is removed by using a solution containing hydrofluoric acid.

It should be noted that, since the blocking mask layer 104 and the ILD layer 106 are both composed of silicon dioxide, when removing the exposed blocking mask layer 104, it is necessary to control the etching time to remove this thin layer of blocking mask. film layer 104, and ensure that the structure of the ILD layer 106 is not damaged.

Step S05 , filling the groove with metal and performing planarization until the gate stack 101 is exposed, as shown in FIG. 2I to FIG. 2J .

In this embodiment, the metals may include but are not limited to: tungsten, titanium, aluminum, copper, and alloys of these metals; correspondingly, suitable chemical vapor deposition, physical vapor deposition ( PVD), electroplating, etc.; then, excess metal is removed by a planarization process to form self-aligned contacts 107 without any lithography-related steps. It should be noted that layers such as titanium, platinum, titanium nitride, etc. may be deposited before metal preparation as a diffusion barrier layer and/or an adhesive layer, so as to reduce the diffusion of the contact portion 107 into the sidewall spacer 102 and/or the ILD layer 106 particle.

In a specific implementation, a thin metal titanium layer is deposited by PVD as an adhesive layer between the contact portion 107 and the silicon dioxide; then, a CVD method is used to deposit the titanium nitride layer and the diffusion barrier layer on the titanium layer to serve as the contact portion 107; Next, tungsten metal is deposited by the CVD method, and the opening formed by removing the auxiliary spacer 105 is filled to form a tungsten plug; finally, the tungsten metal is ground and polished by a CMP process until the gate stack 101 is exposed, wherein the gate stack 101 is exposed. The hard mask layer 1013 of the stack 101 can be removed if desired. Of course, grinding can be continued until the gate electrode layer 1012 is exposed, which depends on the actual situation and is not limited here.

In the embodiment of the present invention, the auxiliary spacer 105 is formed conformally outside the gate spacer 102, and the auxiliary spacer 105 is used as a sacrificial layer for forming the contact portion 107. After the ILD layer 106 is formed, the auxiliary spacer is removed by removing the auxiliary spacer 105. The wall 105 is used to expose the metal silicide layer 1031 on the surface of the source/drain region 103 , and then the contact portion 107 is formed by depositing a metal layer and a planarization process. Since the method provided by the present invention forms the auxiliary spacer 105 conformally on the outside of the gate spacer 102, and then self-aligns to form the contact portion 107 after removing the auxiliary spacer 105, no photolithography process is required, and no photolithography occurs. The problem of inaccurate alignment in the process greatly reduces the difficulty of forming the contact portion 107; in addition, the distance between the contact portion 107 and the gate is only the thickness of the sidewall 102, which effectively reduces the contact portion 107 and the gate. The distance between the gate and the contact portion 107 can be precisely controlled by controlling the thickness of the sidewall 102, which effectively solves the problem that the distance between the gate and the contact portion 107 cannot be accurately and easily reduced in the prior art. Small current delay improves device performance.

Embodiment 2

A method for forming a self-aligned contact is as described in the first embodiment, the difference is that in this embodiment, the substrate 100 is an SOI substrate; the gate is a metal gate 109; The preparation process is a gate-last process, which mainly includes: forming a dummy gate on the substrate 100 (same as the formation process of the gate stack 101 in the first embodiment), source/drain regions 103, sidewall spacers 102, contacts 107 and ILD layer 106, such as Removing the dummy gate to form a metal gate groove; forming a metal gate dielectric layer 108 in the metal gate groove; filling the metal gate groove with metal; performing planarization until the sidewall spacers 102 are exposed .

A method of forming self-aligned contacts 107 includes:

Steps S11 to S15 are the same as steps S01 to S05 in the first embodiment, and will not be described in detail here.

In step S16, the gate stack 101 is removed to form a metal gate groove, as shown in FIG. 3A.

In this embodiment, the gate stack 101 is removed by dry etching, wet etching and other processes to form a metal gate groove, and the metal gate groove is used to form the metal gate 109 .

In a specific embodiment, a mixed gas of chlorine, hydrobromic acid, helium and oxygen is used as the etching gas, and the gate stack 101 is removed by dry etching to form a metal gate groove.

It should be noted that the etching gas may etch the exposed parts of the ILD layer 106 and the like in a small amount, and the composition of the etching gas depends on the specific use effect.

Step S17 , forming a metal gate dielectric layer 108 in the metal gate groove, as shown in FIG. 3B .

In this embodiment, the metal gate dielectric layer 108 may be a high-k material, as described above.

In a specific embodiment, a hafnium oxide thin film is deposited as a high-k dielectric layer by atomic layer deposition (ALD); then, an annealing process is performed.

Step S18, filling the metal gate groove with metal, as shown in FIG. 3C .

In this embodiment, a metal layer with a thickness greater than the height of the gate stack 101 is formed by an ALD method, a PVD method, a CVD method, or the like. It should be noted that the metal layer is used to form the metal gate 109, and the metal gate 109 at least includes a metal work function layer and a metal gate electrode layer. In addition, the metal gate 109 may also include an adhesive layer and a diffusion barrier layer. The specific types are as described above.

In step S19, planarization is performed until the sidewalls 102 are exposed, as shown in FIG. 3D.

In this embodiment, since the finally formed metal gate electrode layer and the top of the sidewall spacers 102 are at the same level, when the sidewall spacers 102 are exposed by planarization, the metal gate 109 will be formed.

In a specific embodiment, a CMP process is used for planarization until the sidewall spacers 102 are exposed, and excess metal is removed to form a metal gate 109 .

In this embodiment, after the self-aligned contact portion 107 is formed by the method provided by the present invention, a high-k metal gate device having the self-aligned contact portion 107 is fabricated by combining with the high-k metal gate-last process in the prior art.

Embodiment 3

A method for forming a self-aligned contact is as described in the first embodiment, the difference is that in this embodiment, the gate is the metal gate 109 , and the steps of forming the dummy gate for forming the metal gate 109 are the same as The steps of forming the gate stack 101 in the first embodiment; the metal gate 109 and the contact portion 107 are formed at the same time; the filling of the groove with metal and planarization until the gate stack 101 is exposed includes: filling the groove with filler 207 , and planarize until the gate electrode layer 1012 is exposed, the selective etching ratio of the filler 207 to the gate electrode layer 1012 is ≥50:1, and the selective etching ratio of the filler 207 to the gate dielectric layer 1011 is ≥ 50:1; remove the gate stack 101, and form a metal gate dielectric layer 108, and the selective etching ratio of the metal gate dielectric layer 108 and the filler 207 is ≤1:50; remove the filler 207; use metal The grooves are filled and planarized until the sidewalls 102 are exposed.

Steps S21 to S24 are the same as steps S01 to S04 in the first embodiment, and will not be described in detail here.

Step S25, fill the groove with filler 207, and perform planarization until the gate electrode layer 1012 is exposed, the selective etching ratio of the filler 207 to the gate electrode layer 1012 is ≥50:1, the filler The selective etching ratio of 207 to the gate dielectric layer 1011 is ≥50:1. As shown in FIGS. 4A to 4C .

In this embodiment, the selection of the filler 207 is very important, the selective etching ratio of the filler 207 to the gate electrode layer 1012 is ≥50:1, and the filler 207 and the gate dielectric layer 1011 The selective etching ratio is greater than or equal to 50:1, which ensures that the filler 207 will not be damaged during the subsequent removal of the dummy gate (polysilicon gate stack 101 in the embodiment).

In a specific embodiment, amorphous carbon is used as the filler 207 to fill the groove formed after the auxiliary sidewall 105 is removed. Of course, the filler 207 can also be resin or the like, as shown in FIG. 4B . Then, the excess filler is removed through a CMP process until the gate electrode layer 1012, ie, the polysilicon dummy gate, is exposed, as shown in FIG. 4C .

In step S26, the gate stack 101 is removed, and a metal gate dielectric layer 108 is formed, and the selective etching ratio of the metal gate dielectric layer 108 and the filler 207 is greater than or equal to 50:1, as shown in FIG. 4D to FIG. 4E .

In this embodiment, the gate stack 101 is removed by dry etching or wet etching. It should be noted that, in step S25, the hard mask layer 1013 of the gate stack 101 has been removed, and this step only needs to remove the remaining gate stack 101 to expose the surface of the silicon substrate under the gate stack 101; Then, a metal gate dielectric layer 108 is formed on the exposed surface of the silicon substrate.

In a specific embodiment, the gate stack 101 is removed by a reactive ion etching (RIE) method by using a mixture of hydrobromic acid, chlorine and oxygen as an etching gas, wherein the gate electrode layer 1012 and the gate dielectric layer 1011 are etched The composition of the etching gas may be different, and the larger the selective etching ratio of the gate electrode layer 1012 to the ILD layer 106, the better. Then, a hafnium oxide film is deposited by ALD as a high-k gate dielectric layer, and then the high-k gate dielectric layer other than the gate can be removed by CMP again.

It should be noted that, since the metal gate 109 and the contact portion 107 are to be formed at the same time, the non-conductive metal gate dielectric layer 108 cannot exist at the bottom of the contact portion 107 . Therefore, the filling cannot be removed before the metal gate dielectric layer 108 is formed. Otherwise, a non-conductive metal gate dielectric layer 108 will be formed between the contact portion 107 and the metal silicide layer 1031. After the metal gate dielectric layer 108 is formed, the filler 207 will be removed (during the period, the metal gate dielectric layer 108 cannot be damaged. The formed metal gate dielectric layer 108), in this way, the groove for preparing the contact portion 107 and the groove for preparing the metal gate 109 in which the metal gate dielectric layer 108 has been formed are simultaneously formed. Therefore, the metal gate The selective etching ratio of the dielectric layer 108 to the filler 207 is ≥50:1. In practical applications, using amorphous carbon as the filler 207 and using hafnium oxide as the metal gate dielectric layer 108 both satisfy the above conditions; of course, there are other substances meeting the above conditions, which are not listed here.

In step S27, the filler 207 is removed, as shown in FIG. 4F .

In this embodiment, the amorphous carbon can be reacted with oxygen to generate gaseous carbon dioxide through a process such as thermal oxidation to remove the amorphous carbon.

In step S28, the grooves are filled with metal and planarized until the sidewall spacers 102 are exposed, as shown in FIG. 4G to FIG. 4H .

In this embodiment, the filling of the groove with metal may be to fill the groove with a metal or a stack of multiple metals to form the metal gate 109 , for example, the metal gate 109 may include an adhesive layer, Diffusion barrier layer, work function layer, metal gate electrode layer, etc. Since the sidewall spacers 102 and the ILD layer 106 have the same level, after the sidewall spacers 102 are exposed by planarization, the metal gate 109 and the contact portion 107 are isolated by the sidewall spacer 102, which will not cause a CTG short circuit. At the same time, the contact portion 107 and the metal gate 109 are simultaneously formed and exposed on the surface of the substrate 100 . Since the metal gate 109 and the contact portion 107 are formed at the same time, the composition of the contact portion 107 is the same as that of the metal gate 109 .

In a specific embodiment, a titanium metal layer is deposited as an adhesive layer by ALD method; then, a metal work function layer is deposited by ALD method, for example, a titanium aluminum layer is used as the metal work function layer of nMOS; of course, titanium nitride can also be deposited As the diffusion barrier layer of the metal gate electrode layer; then, deposit the metal gate electrode layer, and the material of the metal gate electrode layer is as described above. Finally, excess metal is removed through a CMP process until the spacers 102 are exposed, so as to form the contact portion 107 and the metal gate 109 at the same time.

In the embodiment of the present invention, since the method adopts the filler 207 that satisfies certain conditions with the selective etching ratio of the sidewall spacer 102 , the gate electrode layer 1012 , and the metal gate dielectric layer 108 , it is possible to adjust the process sequence to achieve the above Filler 207 fills the groove formed after removing the auxiliary spacer 105, and then removes the polysilicon gate stack 101, firstly forms a metal gate dielectric layer 108, then removes the filler 207, and finally forms the contact portion 107 and The high-k metal gate effectively improves the fabrication efficiency of the device, and at the same time solves the problem that the distance between the gate and the contact portion 107 cannot be accurately and easily reduced in the prior art, reduces the current delay, and improves the performance of the device .

Embodiment 4

A method for forming a self-aligned contact portion, as described in the second embodiment, the difference is that in this embodiment, the contact portion 107 and the high-k metal gate are simultaneously formed by adjusting the process sequence, wherein the said Removing the auxiliary spacer 105 and the silicon dioxide inside the auxiliary spacer 105, and exposing the metal silicide layer 1031 includes: removing the auxiliary spacer 105, the gate stack 101 and connecting with the auxiliary spacer 105 The blocking mask layer 104 exposes the metal silicide layer 1031 and the substrate 100 under the gate stack 101; a metal work function layer is formed.

Steps S31 to S33 are the same as steps S11 to S13 in the first embodiment, and are not described in detail here.

Step S34 , removing the auxiliary spacer 105 , the gate stack 101 and the blocking mask layer 104 in contact with the auxiliary spacer 105 , exposing the metal silicide layer 1031 and the gate stack 101 . The lower substrate 100 is shown in FIG. 5A to FIG. 5B .

In this embodiment, the auxiliary spacer 105 , the gate stack 101 and the auxiliary spacer 105 are removed by wet etching, dry etching or dry etching in combination with wet etching. The adjacent blocking mask layer 104 exposes the metal silicide layer 1031 and the substrate 100 under the gate stack 101 .

In a specific embodiment, first, use hot phosphoric acid to remove the silicon nitride hard mask layer 1013 on the top of the gate stack 101, and in step S33, the gate stack 101 may be exposed by a CMP process and then continue to grind downward until the gate stack 101 is exposed. the gate electrode layer 1012; then, a mixture of hydrobromic acid, chlorine and oxygen is used as an etching gas to remove the auxiliary sidewall spacer 105 and the gate electrode layer 1012 by a reactive ion etching (RIE) method; The solution of hydrofluoric acid etches the gate dielectric layer 1011 and the exposed blocking mask layer 104 , exposing the metal silicide layer 1031 and the substrate 100 under the gate stack 101 .

In step S35, a metal gate dielectric layer 108 is formed, as shown in FIG. 5C.

In this embodiment, the forming of the metal gate dielectric layer 108 includes: depositing a high-k dielectric layer; and removing the high-k dielectric layer 108 outside the gate stack 101 . Specifically, a thin layer of high-k material is deposited by atomic layer deposition, physical vapor deposition, etc. to form the metal gate dielectric layer 108, for example, a 10 angstrom hafnium oxide film is deposited by ALD; The high-k dielectric layer at the gate stack 101 is protected by a photoresist and/or a hard mask, the unprotected high-k dielectric layer is removed by an etching process, and then the photoresist is removed to form a metal gate dielectric layer 108 .

It should be noted that the photolithography process in this step is difficult, but through this step, the metal gate 109 and the contact portion 107 can be simultaneously formed in subsequent steps, so as to simplify the device fabrication process.

In step S36, the grooves are filled with metal and planarized until the sidewall spacers 102 are exposed, as shown in FIGS. 5D to 5E.

In this embodiment, the metal may be one metal or a stack of multiple metals. For example, the metal may include: an adhesive layer, a metal work function layer, a diffusion barrier layer, and a gate electrode layer. Since the sidewall spacers 102 and the ILD layer 106 have the same level, after the sidewall spacers 102 are exposed by planarization, the metal gate 109 and the contact portion 107 are isolated by the sidewall spacer 102, which will not cause a CTG short circuit. At the same time, the contact portion 107 and the metal gate 109 are simultaneously formed and exposed on the surface of the substrate 100 . Specifically, titanium nitride is deposited as the diffusion barrier layer of the metal gate electrode layer; then, the metal gate electrode layer is deposited, and the material of the metal gate electrode layer is as described above. Finally, excess metal is removed through a CMP process until the spacers 102 are exposed, so as to form the contact portion 107 and the metal gate 109 at the same time. In addition, the composition of the contact portion 107 is the same as that of the metal gate 109 .

In the embodiment of the present invention, since the method adjusts the process sequence, the auxiliary spacer 105 and the polysilicon gate stack 101 are removed to form a groove, then a layer of dielectric is deposited, and a metal gate is formed by a photolithography process and an etching process The dielectric layer 108 finally forms the contact portion 107 and the high-k metal gate at the same time, which effectively improves the fabrication efficiency of the device and solves the problem that the distance between the gate and the contact portion 107 is not easily reduced in the prior art. Improved device performance.

Embodiment 5

A method for forming a self-aligned contact is as described in any one of Embodiments 1 to 4, the difference is that in this embodiment, fins 1001 are formed on the substrate 100 for manufacturing Fin-FETs.

Step S41 , providing a substrate 100 on which a fin 1001 and the gate stack 101 are formed, the gate stack 101 is located above the fin 1001 in a direction perpendicular to the fin 1001 , and the The source/drain regions 103 are located on the fins 1001 on both sides of the spacers 102 , and the metal silicide layer 1031 is located on the source/drain regions 103 .

In this embodiment, the fin 1001 and related structures can be formed by the following steps:

First, a substrate 100 is provided on which fins 1001 and isolation are formed. Specifically, a first hard mask of silicon nitride (not shown) is formed on a silicon substrate; Etching techniques, such as RIE (Reactive Ion Etching), etch the substrate 100 to form the fins 1001, thereby forming the fins 1001 on the substrate 100, as shown in FIG. 6A; then, perform isolation filled with silicon dioxide Then, the hard mask of silicon nitride can be removed by wet etching, such as high-temperature phosphoric acid; then, the hard mask of a certain thickness can be removed by etching with hydrofluoric acid. isolation material, leaving part of the isolation material between the fins 1001 to form isolation; then, deposit a gate dielectric layer 1011 and a polysilicon layer with a thickness > the height of the fins 1001, and planarize to form a flat polysilicon surface; The position of the gate stack 101 is defined by an etching process, and the gate stack 101 is formed by an etching process, as shown in FIG. 6B ; then, spacers are formed on both sides of the gate stack 101 by the process of forming spacers in the prior art (not shown in the figure). out); then, a source/drain implantation process is performed to form the source/drain region 103; finally, a metal silicide layer 1031 is formed on the surface of the source/drain region 103, as shown in FIG. 6C. It should be noted that, since the Fin-FET is a three-dimensional device, when spacers (not shown in the figure) are formed on both sides of the gate stack 101, spacers (not shown in the figure) are also formed on both sides of the fin 1001, but the gate The height of the stack 101 is higher than the height of the fins 1001. By increasing the etching time of the anisotropic etching, the spacers (not shown) on both sides of the fins 1001 can be removed, and then the gate stack 101 that is not protected by the spacers can be removed. Can.

Next, the contact portion 107 can be formed on the Fin-FET separately by using the steps after the substrate 100 is provided as shown in the second embodiment to the fourth embodiment, as shown in the second embodiment; or simultaneously on the Fin-FET The contact portion 107 and the metal gate 109 are formed, which will not be described in detail here.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify them into equivalents of equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention still fall within the protection scope of the technical solutions of the present invention.

Claims (7)

1. a kind of method for forming self-aligned contacts portion characterized by comprising

Substrate is provided, the side wall that grid stack and stack two sides positioned at the grid, the side wall two sides are formed on the substrate Substrate on be formed with source/drain region and the metal silicide layer on the source/drain region；

Sequentially form block mask layer and the auxiliary side wall except the side wall, on the block mask layer；

Interlayer dielectric layer is formed, and carries out surface planarisation until the exposure grid stack；

The block mask layer for removing the auxiliary side wall and connecting with the auxiliary side wall, the exposure metal silicide Layer；

Groove is filled up with metal, and carries out planarization until the exposure grid stack；

It sequentially includes: the gate dielectric layer of substrate, gate electrode layer and the grid on the gate dielectric layer that the grid, which stack, Hard mask layer on electrode layer；

The method also includes:

It removes the grid to stack, forms metal grid recess；

Metal gate dielectric layer is formed in the metal grid recess；

The metal grid recess is filled with metal；

Planarization is carried out until the exposure side wall；

It is described that groove is filled up with metal, and planarization is carried out until the exposure grid stacking includes:

Groove is filled with filler, and carries out planarization until the exposure gate electrode layer, the filler and the gate electrode Selective etching ratio >=the 50:1, selective etching ratio >=50:1 of the filler and the gate dielectric layer of layer；

It removes the grid to stack, and forms metal gate dielectric layer, and the selection of the metal gate dielectric layer and the filler is carved Lose ratio >=50:1；

Remove the filler；

Groove is filled with metal and is planarized, until the exposure side wall.

2. the method according to claim 1, wherein the filler is indefinite form carbon.

3. the method according to claim 1, wherein the removal auxiliary side wall and with the auxiliary side wall The block mask layer to connect, the exposure metal silicide layer include:

The auxiliary side wall is removed, the block mask layer that the grid stack and connect with the auxiliary side wall, described in exposure The substrate under metal silicide layer and grid stacking；

Form metal gate dielectric layer.

4. according to the method described in claim 3, it is characterized in that, the formation metal gate dielectric layer includes:

Deposit high-k dielectric layer；

Remove the high-k dielectric layer except the grid stack.

5. method according to any one of claims 1 to 4, which is characterized in that be also formed with fin, the grid on the substrate It stacks to be located on the fin perpendicular to the direction of the fin, and the source/drain region is located at the fin of the side wall two sides On, and the metal silicide layer on the source/drain region.

6. method according to any one of claims 1 to 4, which is characterized in that the material of the auxiliary side wall includes following Any one: polysilicon, amorphous silicon.

7. method according to any one of claims 1 to 4, which is characterized in that the contact portion includes following any one layer Or multilayer: bonding coat, metal work function layer, diffusion barrier layer, metal gate electrode layer.