CN106531113B - A kind of display panel, drive circuit and its driving method, display device - Google Patents
A kind of display panel, drive circuit and its driving method, display device Download PDFInfo
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- CN106531113B CN106531113B CN201710002812.3A CN201710002812A CN106531113B CN 106531113 B CN106531113 B CN 106531113B CN 201710002812 A CN201710002812 A CN 201710002812A CN 106531113 B CN106531113 B CN 106531113B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
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Abstract
The embodiment of the present invention provides a kind of display panel, drive circuit and its driving method, display device, is related to showing actuation techniques field, for reducing the difference reduced between practical common voltage and ideal common voltage.The driving method includes that controller issues control instruction.Processor receives control instruction, and according to control instruction, voltage data is obtained from memory.Processor determines benchmark common voltage value from voltage data, and the voltage data other than benchmark common voltage value is divided into multiple voltage data groups；Each voltage data group includes opposite polarity the first voltage value and second voltage value；The pressure difference of the first voltage value and second voltage value respectively with benchmark common voltage is equal or approximately equal.Processor exports the first voltage value being located in same voltage data group and second voltage value one by one.Digital analog converter carries out digital-to-analogue conversion to the voltage value that the processor exports.The driving method of display panel is for driving common voltage.
Description
Technical field
The present invention relates to display actuation techniques field more particularly to a kind of display panel, drive circuit and its driving method,
Display device.
Background technique
Display device, such as LCD (Liquid Crystal Display, liquid crystal display), because it is with small in size, function
The features such as low, radiationless and cost of manufacture is relatively low is consumed, and is applied in high-performance display field more and more.
It include public electrode and pixel electrode in LCD, during display display, respectively to public electrode and pixel
Electrode applies voltage, to drive liquid crystal molecule to deflect.When showing tableaux, liquid crystal molecule always works at a certain solid
Under fixed electric field action, then the characteristic of liquid crystal molecule will solidify.After extra electric field changes, liquid crystal molecule be cannot respond to
The variation of extra electric field, to aging phenomenon occur.Therefore to the pixel that in order to avoid there is aging phenomenon, pixel electrode is provided
The polarity of voltage Vp can be inverted in adjacent two image frame, such as shown in Figure 1, pixel is electric in the first image frame
Press Vp1For positive polarity, the pixel voltage Vp in the second image frame2It is reversed to negative polarity.
Generally, ideal common voltage Vcom is in the center of the pixel voltage Vp of positive-negative polarity, as shown in Figure 1,
Vp1- Vcom=Vcom-Vp2, i.e., | V1|=| V2|, the grayscale of two image frame sub-pixes is identical at this time.However, due to commissioning device
Error and Vcom IC register minimum resolution limitation, as shown in Fig. 2, practical common voltage Vcom ' with it is ideal public
There are a difference f by voltage Vcom, it can be seen that (Vp1-Vcom’)<(Vcom’-Vp2), i.e., | V1’|<|V2' |, pixel at this time
Data are biased to negativity area A.When showing tableaux, the grayscale of adjacent two image frame is not identical, and then leads to adjacent two picture
Frame display brightness is not identical.When display is when carrying out the display of next frame picture, above-mentioned difference is due to that can not eliminate and after renewing
?.When display is for a long time in use, above-mentioned difference f can be accumulated constantly, lead in sub-pix that there are remaining DC voltages, it should
Remaining DC voltage will lead to the appearance of image retention.
Summary of the invention
The embodiment of the present invention provides a kind of display panel, drive circuit and its driving method, display device, for reducing
Reduce the difference between practical common voltage and ideal common voltage.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
The one side of the embodiment of the present invention provides a kind of driving method of display panel, comprising: controller issues control and refers to
It enables；Processor receives the control instruction, and according to the control instruction, voltage data is obtained from memory；The processing
Device determines benchmark common voltage value from the voltage data, and by the voltage number other than the benchmark common voltage value
According to being divided into multiple voltage data groups；Wherein, each described voltage data group includes opposite polarity the first voltage value and
Two voltage values；The first voltage value and the second voltage value are equal or approximate with the pressure difference of the benchmark common voltage respectively
It is equal；The processor exports the first voltage value being located in same voltage data group and second voltage value one by one；Number
Mode converter carries out digital-to-analogue conversion to the voltage value that the processor exports.
Optionally, the processor determines benchmark common voltage value from the voltage data, and will be in addition to the base
Voltage data other than quasi- common voltage value is divided into after multiple voltage data groups, the driving method further include: the place
It manages device and obtains multiple voltage data groups, and the identical voltage value of polarity in the multiple voltage data group is arranged successively, with true
The output timing of fixed multiple voltage data groups；The processor will be located at the first voltage value and second in same voltage data group
It includes: the processor according to the output timing that voltage value carries out output one by one, will be successively located in multiple voltage data groups
The first voltage value and second voltage value in same voltage data group are exported one by one.
Optionally, when the processor will be located at the first voltage value in same voltage data group and second voltage value one by one
When being exported, each voltage value of the processor output keeps a preset time, wherein the preset time is 1
Hour~12 hours.
The another aspect of the embodiment of the present invention provides a kind of display panel, drive circuit characterized by comprising control
Device, processor, memory and digital analog converter；The memory is for storing voltage data；The controller and the place
Reason device is connected, and the controller is used to export control instruction to the processor；The processor is also connected with the memory,
The processor is used for according to the control instruction, obtains voltage data from the memory, and from the voltage data really
Benchmark common voltage value is made, and the voltage data other than the benchmark common voltage value is divided into multiple voltage datas
Group；The processor is also used to one by one carry out the first voltage value being located in same voltage data group and second voltage value defeated
Out；Wherein, each described voltage data group includes opposite polarity the first voltage value and second voltage value；The first voltage
The pressure difference of value and the second voltage value respectively with the benchmark common voltage value is equal or approximately equal；The digital analog converter
It is connected with the processor, the voltage that the digital analog converter is used to export the processor carries out digital-to-analogue conversion.
Optionally, the processor includes logical-sequential control unit and the first cache unit；The logical sequence control
Unit processed is connected with the memory, and the logical-sequential control unit from the memory for obtaining the voltage number
According to；First cache unit is connected with the logical-sequential control unit, and first cache unit is for patrolling described
It collects multiple voltage data groups that timing control unit is got from the memory to be cached, and in the logical-sequential control
In will be data cached under the control of unit, the first voltage value and second voltage value in same voltage data group carry out one by one
Output.
Further, the processor further includes the second cache unit being connected with the logical-sequential control unit；
The controller includes conversion circuit；Control instruction includes the first open command and the second open command；Second caching is single
Member is used to cache the benchmark common voltage value that the logical-sequential control unit is got from the memory, and in institute
State the voltage value that caching is exported under the control of logical-sequential control unit；Conversion circuit is used for the logical-sequential control unit
Export first open command or second open command；The logical-sequential control unit is opened according to described first to be referred to
It enables, controls the first cache unit output voltage data；Alternatively, the logical-sequential control unit is opened according to described second
Instruction controls the second cache unit output voltage data.
Further, the conversion circuit includes first resistor and second resistance；One end of the first resistor connects institute
One end of logical-sequential control unit, the second resistance is stated, the other end connects reference power source, the other end of the second resistance
Ground connection.
Optionally, which further includes amplification voltage regulator circuit；The amplification voltage regulator circuit includes first
Voltage stabilizing module, amplification module and the second Voltage stabilizing module；First Voltage stabilizing module is connected with the digital analog converter, and described
One Voltage stabilizing module is used to stablize the voltage signal of the digital analog converter output；The amplification module and first Voltage stabilizing module
It is connected, the voltage that the amplification module is used to export first Voltage stabilizing module amplifies；Second Voltage stabilizing module
It is connected with the amplification module, second Voltage stabilizing module is used to stablize the voltage signal of the amplification module output.
Further, first Voltage stabilizing module includes first voltage follower；The amplification module includes transistor,
Three resistance, the 4th resistance, the 5th resistance；Second Voltage stabilizing module includes second voltage follower；Wherein, the first voltage
The first input end of follower connects the output end of the digital analog converter, and output end connects the grid of the transistor；It is described
One end of 5th resistance connects the second pole of the second input terminal of the first voltage follower, the transistor, another termination
Ground；One end of the 3rd resistor connects voltage input end, and the other end connects the first pole of the transistor；4th resistance
One end connect the first pole of the transistor, other end ground connection；The first input end of the second voltage follower connects institute
The first pole of transistor is stated, the second input terminal connects output end.
It optionally, further include timer, the timer is connected with the processor, and the timer is for controlling institute
State the output time of any voltage value of processor output.
The another aspect of the embodiment of the present invention provides a kind of display device, including any one display surface as described above
Drive circuit.
The embodiment of the invention provides a kind of display panel, drive circuit and its driving method, display device, the display surfaces
The driving method of plate includes: firstly, controller issues control instruction.Next, processor receives control instruction, referred to according to control
It enables, voltage data is obtained from memory.Then, processor determines benchmark common voltage value from voltage data, and will remove
Voltage data other than the reference voltage value is divided into multiple voltage data groups, specifically, each voltage data group packet
Include opposite polarity the first voltage value and second voltage value；The first voltage value and the second voltage value respectively with the base
The pressure difference of quasi- common voltage is equal or approximately equal.Again, processor will be located at the first voltage value in same voltage data group
It carries out digital-to-analogue conversion one by one with second voltage value and exports.Finally, the voltage value that digital analog converter exports processor counts
Mould conversion.
Based on this, in output voltage data, due to the first voltage value being located in same voltage data group and the second electricity
The polarity of pressure value is on the contrary, and the first voltage value and second voltage value or approximate phase equal with the pressure difference of benchmark common voltage value respectively
Deng, therefore when being exported the first voltage value being located in same voltage data group and second voltage value one by one, same electricity
The first voltage value and second voltage value in pressure data group is approximately uniform with the pressure difference that benchmark common voltage value is formed respectively, and should
The polarity of pressure difference on the contrary, therefore can approximation cancel out each other.So, after display shows a period of time, this time
Pressure difference between the average value and said reference common voltage value of the interior common voltage provided to display is smaller or does not deposit substantially
, in the case, for pixel voltage before reversion, the DC voltage remained in sub-pix is smaller or is substantially not present, from
And display can be reduced for a long time using the probability for being also easy to produce image retention.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the schematic diagram that common voltage is located at pixel voltage center in the prior art；
Fig. 2 is the schematic diagram that common voltage shown in FIG. 1 deviates pixel voltage center；
Fig. 3 is a kind of driving method of display panel provided in an embodiment of the present invention；
Fig. 4 is a kind of driving circuit of display panel provided in an embodiment of the present invention；
Fig. 5 is the driving method of another display panel provided in an embodiment of the present invention；
Fig. 6 is the driving circuit of another display panel provided in an embodiment of the present invention；
Fig. 7 is the driving circuit of another display panel provided in an embodiment of the present invention；
Fig. 8 is the concrete structure schematic diagram of conversion circuit shown in Fig. 7；
Fig. 9 is a kind of driving circuit including amplifying the display panel of voltage regulator circuit provided in an embodiment of the present invention；
Figure 10 is the concrete structure schematic diagram of amplification voltage regulator circuit shown in Fig. 9；
Figure 11 is the operation principle schematic diagram of amplification voltage regulator circuit shown in Fig. 10.
Appended drawing reference:
01- display panel, drive circuit；10- controller；11- conversion circuit；20- processor；21- logical-sequential control list
Member；The first cache unit of 22-；The second cache unit of 23-；30- memory；40- digital analog converter；50- amplifies voltage regulator circuit；
The first Voltage stabilizing module of 51-；52- amplification module；The second Voltage stabilizing module of 53-；60- timer；61- crystal oscillator.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of driving method of display panel, as shown in Figure 3, comprising:
Step S101, controller 10 as shown in Figure 4 issues control instruction.
Step S102, processor 20 as shown in Figure 4 receives above-mentioned control instruction, and according to the control instruction from such as Fig. 4
Shown in obtain voltage data in memory 30.
Specifically, above-mentioned control instruction refer to include the storage address of voltage data in memory 30 instruction.Herein
In the case of, processor 20 30 is addressed in memory according to the storage address in above-mentioned control instruction, thus according to addressing
As a result voltage data corresponding with the storage address is found, and the voltage data is extracted in processor 20.
Step S103, processor 20 determines benchmark common voltage value V0 from voltage data, and will be public in addition to benchmark
Voltage data other than voltage value V0 is divided into multiple voltage data groups (B1, B2, B3 ...).
Wherein, each voltage data group (in B1, B2, B3 ... any one) includes opposite polarity first voltage
Value V1 and second voltage value V2；And the first voltage value V1 and second voltage value V2 the pressure difference phase with benchmark common voltage value V0 respectively
Deng or it is approximately equal.
It should be noted that the voltage data in first, memory 30 is pre-set one group of voltage data, the voltage
The setting value of data determines according to actual test, the present invention to the specific setting value of the voltage data without limitation.Such as voltage
Data can be set to second group of data as shown in table 1 below, be followed successively by 7.62V, 7.71V, 7.79V, 7.90V, 8.01V,
8.10V,8.19V,8.22V,8.30V,8.39V.On this basis, in order to improve be divided into multiple voltage data groups (B1, B2,
B3 ...) after, the electricity of the first voltage value V1 and second in same voltage data group (in B1, B2, B3 ... any one)
The neutralization effect of the pressure difference of pressure value V2 and benchmark common voltage value V0, it is preferred that the voltage value that voltage data is arranged is one group etc.
Difference series.Further, in order to reduce the voltage value of output and the pressure difference of benchmark common voltage value V0, the pressure difference is avoided to cause residual
The DC voltage stayed is excessive, it is preferred that the margin of tolerance of the voltage data of above-mentioned equal difference is 0.1V-1V.For example, voltage data can
To be set as first group of data as shown in table 1 below, be followed successively by 7.6V, 7.7V, 7.8V, 7.9V, 8V, 8.1V, 8.2V, 8.3V,
8.4V。
The second, above-mentioned polarity refers on the contrary, the voltage value in any one voltage data group and benchmark common voltage value V0
It compares, when the voltage value is greater than benchmark common voltage value V0, which is positive polarity；Conversely, when voltage value is less than base
When quasi- common voltage value V0, which is negative polarity.In any voltage data group, include one group of opposite polarity first electricity
Pressure value V1 and second voltage value V2.
Third, when the first voltage value V1 and benchmark common voltage value V0 pressure absolute value of the difference f1, second voltage value V2 with
The pressure absolute value of the difference f2 of benchmark common voltage value V0, meet 0V≤| f1-f2 | when≤0.02V, it is believed that belong to definition of the present invention
Pressure difference respectively with benchmark common voltage value V0 of the first voltage value V1 and second voltage value V2 be equal or approximately equal.
The following are the occurrences of two groups of voltage datas provided in an embodiment of the present invention, and by taking the voltage data as an example, to place
Reason device 20 determines benchmark common voltage value V0 from voltage data, and by the voltage number other than benchmark common voltage value V0
It is specifically described according to multiple voltage data groups (B1, B2, B3 ...) are divided into.It should be noted that above-mentioned two groups of voltage
Data are not the restriction to the voltage data stored in memory 30, but understand provided by the invention show in order to clearer
Example.Specifically, as shown in table 1:
Table 1
In first group of voltage data, the voltage value of voltage data is arithmetic progression, and the tolerance of arithmetic progression is 0.1V.Place
It manages device 20 and determines that benchmark common voltage value V0 is 8V, and the voltage data other than benchmark common voltage value V0 is divided into four
A voltage data group, in voltage data group B1, the first voltage value V1 is negative polarity, and occurrence 7.6V is public with benchmark
The pressure absolute value of the difference f1 of voltage value V0 is 0.4V；Second voltage value V2 is positive polarity, and occurrence 8.4V is public with benchmark
The pressure absolute value of the difference f1 of voltage value V0 be 0.4V, meet 0V≤| f1-f2 |≤0.02V, therefore, it is considered that the first voltage value V1 and
Second voltage value V2 is equal with the pressure difference of benchmark common voltage value V0 respectively.In voltage data group B2-B4, the first voltage value V1
As shown in table 1 with the division of the occurrence of second voltage value V2, details are not described herein again.In second group of voltage data, Ge Ge electricity
Press the first voltage value V1 and the division of second voltage value V2 occurrence of data group as shown in table 1, details are not described herein again.
Step S104, processor 20 will be located at the in same voltage data group (in B1, B2, B3 ... any one)
One voltage value V1 and second voltage value V2 are exported one by one.
It should be noted that when exporting the voltage data of multiple voltage data groups in voltage data, processor 20
To be located at same voltage data group in the first voltage value V1 and second voltage value V2 output sequence without limitation.In addition, this
Invention to the output sequencings of multiple voltage data groups (B1, B2, B3 ...) also without limitation.For example, with first in table 1
For group voltage data, 7.6V, 8.4V in first one by one output voltage data group B1, then output voltage data group B2 one by one
In 7.7V, 8.3V, next, by voltage data group B3 and B4 the first voltage value V1 and second voltage value V2 carry out one by one
Output.
Step S105, digital analog converter 40 as shown in Figure 4 carries out digital-to-analogue conversion to the voltage value that processor 20 exports.
Since the voltage value exported by processor 20 is a digital signal, it is used to drive by the voltage value of output
When liquid crystal is shown, need to convert digital signals into electric signal output by digital analog converter 40.
Based on this, in output voltage data, due to the first voltage value V1 and second being located in same voltage data group
The polarity of voltage value V2 is on the contrary, and the first voltage value V1 and second voltage value V2 the pressure difference phase with benchmark common voltage value V0 respectively
Deng or it is approximately equal, therefore carried out one by one by the first voltage value V1 being located in same voltage data group and second voltage value V2
When output, the first voltage value V1 and second voltage value V2 in same voltage data group are formed with benchmark common voltage value V0 respectively
Pressure difference it is approximately uniform, and the pressure difference polarity on the contrary, therefore can approximation cancel out each other.To export first group in table 1 electricity
Data instance is pressed, after display shows a period of time, the average value of the common voltage provided in this time to display is
Pressure difference between 8V, with said reference common voltage value V0 (8V) is 0V.In the case, pixel voltage Vp is before reversion,
The DC voltage remained in sub-pix is substantially not present, so as to reduce practical common voltage and benchmark common voltage value V0
Between difference.
On this basis, when exporting the voltage value in multiple voltage data groups, if processor 20 exports multiple voltage numbers
According to group data when, the two neighboring voltage value exported one by one amplitude difference it is larger, for example, output voltage data group B1's
After 8.4V, when 7.8V in output voltage data group B3, the difference of the amplitude of two neighboring voltage value is 0.2V at this time；In output electricity
After the 8.4V for pressing data group B1, when 7.7V in output voltage data group B2, the difference of the amplitude of two neighboring voltage value is at this time
0.1V；Two kinds of way of outputs are compared, first output voltage data group B1, then when output voltage data group B3, the common voltage of output
Hopping amplitude it is larger, to increase the loss of the circuit for providing common voltage.Therefore, it is mentioned to reduce processor 20
For the circuit loss of common voltage, it is preferred that control the output timing of multiple voltage data groups.
Specifically, above-mentioned driving method further include: after executing above-mentioned steps S102, processor 20 obtains multiple voltages
Data group, and the identical voltage value of polarity in multiple voltage data groups is arranged successively, with the defeated of the multiple voltage data groups of determination
Timing out.It should be noted that the identical voltage value of polarity is arranged successively in multiple voltage data groups, can for from small to large with
This is arranged, at this time the output timing of multiple voltage data groups are as follows: the identical voltage value of polarity is arranged from small to large in voltage data group
Column, or be arranged successively from big to small, at this time the output timing of multiple voltage data groups are as follows: polarity phase in voltage data group
Same voltage value arranges from big to small.
For example, being illustrated by taking first group of voltage data in table 1 as an example.Processor 20 is by multiple voltage data groups
The first voltage value V1 in (B1, B2, B3, B4) is arranged successively from small to large, and determines multiple voltage data groups according to the sequence
The output timing of (B1, B2, B3, B4) is B1, B2, B3, B4.So, in output voltage data, output is electric one by one first
Press data group B1 7.6V, 8.4V, then one by one 7.7V, 8.3V in output voltage data group B2, B3, B4,7.8V, 8.2V,
7.9V, 8.1V, at this point, the hopping amplitude of common voltage is 0.1V, to reduce the circuit for providing common voltage
Loss.
On this basis, when the conversion frequency of the voltage value of output is larger, cause the voltage value of output unstable, in turn
Driving effect of the common voltage to sub-pix that will affect output, in order to avoid the generation of above situation, it is preferred that work as processor
20 by be located at same voltage data group in the first voltage value V1 and second voltage value V2 exported one by one when, processor 20 is defeated
Each voltage value out keeps a preset time.
In the case, if the preset time was less than 1 hour, the conversion frequency of the voltage value of output is larger, causes to export
Voltage value it is unstable, and then influence the common voltage of output to the driving effect of sub-pix；If it is small that the preset time is greater than 12
When, the difference between the voltage value and benchmark common voltage value V0 of output can make the accumulation of sub-pix remaining DC voltage compared with
Greatly, and then before exporting next voltage value and offsetting to the difference, lead to the appearance of image retention, influence the normal aobvious of display
Show.It is therefore preferred that above-mentioned preset time is 1 hour~12 hours.So, on the one hand when preset time is small less than 1,
In output voltage data, the conversion frequency of the voltage value of output is smaller, and the voltage value of output is more stable, therefore to the public affairs of output
Common voltage is smaller to the driving influential effect of sub-pix；On the other hand, when processor 20 is exported voltage value one by one,
Difference in 1 hour~12 hours retention time of the voltage value of output, between the voltage value and benchmark common voltage value V0 of output
Remaining DC voltage in sub-pix caused by being worth, is not enough to be cancelled the appearance of leading picture of disabling in the difference.
On this basis, user in actual use, user and the influence of image retention is not concerned with sometimes, as long as that is, will
The benchmark common voltage value V0 of setting is exported, and does not consider the common voltage and ideal benchmark common voltage value of reality output
The problem of residual voltage caused by difference between V0.In order to meet the demand, as shown in figure 5, executing above-mentioned steps
After S103, above-mentioned driving method further include:
Above-mentioned control instruction is judged, when judging the control instruction for the first open command, executes above-mentioned steps
S104。
When judging the control instruction for the second open command, execute step S201: processor 20 is by benchmark common voltage
Value V0 output.
So, user can select to export the voltage in multiple voltage data groups by the way that above-mentioned control instruction is arranged
Data or outputting reference common voltage value V0, facilitate user to select according to actual needs.
The embodiment of the invention also provides a kind of display panel, drive circuits 01, as shown in Figure 4, comprising: controller 10, place
Device 20, memory 30 and digital analog converter 40 are managed, memory 30 is for storing voltage data.
On this basis, controller 10 is connected with processor 20, and controller 10 is used to refer to the output control of processor 20
It enables.
On this basis, processor 20 is also connected with memory 30, processor 20 be used for according to above-mentioned control instruction from
Voltage data is obtained in memory 30, and benchmark common voltage value V0 is determined from above-mentioned voltage data, and will be in addition to the base
Voltage data other than quasi- common voltage value V0 is divided into multiple voltage data groups.
Wherein, each voltage data group includes opposite polarity the first voltage value V1 and second voltage value V2；First electricity
Pressure difference of the pressure value V1 and second voltage value V2 respectively with said reference common voltage value V0 is equal or approximately equal.
Specifically, above-mentioned control instruction refer to include the storage address of voltage data in memory 30 instruction.Herein
In the case of, processor 20 30 is addressed in memory according to the storage address in above-mentioned control instruction, thus according to addressing
As a result voltage data corresponding with the storage address is found, and the voltage data is extracted in processor 20.
In addition, above-mentioned processor 20 is also used to that the first voltage value V1 in same voltage data group and second voltage will be located at
Value V2 is exported one by one.
For example, being illustrated by taking first voltage data group in table 1 as an example.In first one by one output voltage data group B1
7.6V, 8.4V, then the first voltage value 7.7V, 8.3V in output voltage data group B2, and be sequentially output voltage data group
Voltage value in B3, B4.
On this basis, digital analog converter 40 is connected with processor 20, and digital analog converter 40 is for defeated to processor 20
Voltage value out carries out digital-to-analogue conversion.
Since the voltage value exported by processor 20 is a digital signal, it is used to drive by the voltage value of output
When liquid crystal is shown, need to convert digital signals into electric signal output by digital analog converter 40.
Based on this, in output voltage data, due to the first voltage value V1 and second being located in same voltage data group
The polarity of voltage value V2 is on the contrary, and the first voltage value V1 and second voltage value V2 the pressure difference phase with benchmark common voltage value V0 respectively
Deng or it is approximately equal, therefore carried out one by one by the first voltage value V1 being located in same voltage data group and second voltage value V2
When output, the first voltage value V1 and second voltage value V2 in same voltage data group are formed with benchmark common voltage value V0 respectively
Pressure difference it is approximately uniform, and the pressure difference polarity on the contrary, therefore can approximation cancel out each other.To export first group in table 1 electricity
Data instance is pressed, after display shows a period of time, the average value of the common voltage provided in this time to display is
Pressure difference between 8V, with said reference common voltage value V0 (8V) is 0V.In the case, pixel voltage Vp is before reversion,
The DC voltage remained in sub-pix is substantially not present, so as to reduce practical common voltage and benchmark common voltage value V0
Between difference.
On this basis, since the read or write speed of memory 30 itself is slower, and in memory 30 other than voltage data,
Also store other a large amount of data, processor 20 when determining the voltage data of output, need to be found from memory 30 with
Target voltage data are exported, so that the output speed of voltage data slows down.In order to improve the output speed of voltage data,
Preferably, as shown in fig. 6, processor 20 includes logical-sequential control unit 21 and the first cache unit 22.Wherein, when logic
Sequence control unit 21 is connected with memory 30, and logical-sequential control unit 21 is for obtaining voltage data from memory 30.
Specifically, the first cache unit 22 is connected with logical-sequential control unit 21, the first cache unit 22 for pair
Multiple voltage data groups that logical-sequential control unit 21 is got from memory 30 are cached, and in logical-sequential control list
In will data cached under the control of member 21, by the same voltage data group the first voltage value V1 and second voltage value V2 by
It is a to be exported.
For example, being illustrated by taking first voltage data group in table 1 as an example.By the voltage in voltage data group B1-B4
Data buffer storage will be located at B1 in voltage data group in the first cache unit 22 under the control of logical-sequential control unit 21
7.6V, 8.4V be sequentially output, then the voltage data in voltage data group B2-B4 is exported one by one.
So, since the read or write speed of the first cache unit 22 itself is very fast, logical-sequential control unit 21
According to above-mentioned control instruction, controlling the first cache unit 22 will be data cached, the first voltage in same voltage data group
The speed that value V1 and second voltage value V2 are exported one by one improves；Further, due to by the electricity in multiple voltage data groups
It presses data buffer storage in the first cache unit 22, in voltage data output, can be addressed to avoid from memory 30 to incite somebody to action
Target voltage data output, so that the problem of output speed of voltage data slows down.
On this basis, user in actual use, user and the influence of image retention is not concerned with sometimes, as long as that is, will
The benchmark common voltage value V0 of setting is exported, and does not consider the common voltage and ideal benchmark common voltage value of reality output
The problem of residual voltage caused by difference between V0.In order to meet the demand, as shown in fig. 7, above-mentioned processor 20 also wraps
Include the second cache unit 23.Above-mentioned control instruction includes the first open command and the second open command, for single to the first caching
Member 22 and the second cache unit 23 are selected the voltage value to determine output.
Specifically, logical-sequential control unit 21 controls 22 output voltage of the first cache unit according to the first open command
Data；Logical-sequential control unit 21 controls 23 output voltage data of the second cache unit according to the second open command.
It should be noted that the present invention to the way of output of above-mentioned control instruction without limitation, can be arranged by software
Or hardware circuit selection.For example, when by the software program setting in controller 10, selection open the first cache unit 22 or
The second cache unit of person 23.
Perhaps in another example selecting to open the first cache unit 22 or the second cache unit 23 by hardware circuit.Specifically
, as shown in fig. 7, controller 10 includes conversion circuit 11, conversion circuit 11 is used for the output of logical-sequential control unit 21 the
One open command or the second open command.
Specifically, as shown in figure 8, above-mentioned conversion circuit 11 includes first resistor R1 and second resistance R2.Wherein, the first electricity
One end of one end connection processor 20 and second resistance R2 of R1 is hindered, the other end connects reference power source Vcc, and second resistance R2's is another
One end ground connection.
In the case, when reference power source Vcc is connected, first resistor R1 pull-up is high level, at this point, conversion circuit 11
High level is exported to logical-sequential control unit 21, to control 22 output voltage data of the first cache unit；As reference power source Vcc
When disconnection, second resistance R2 drop-down is low level, at this point, conversion circuit 11 exports low level to logical-sequential control unit 21,
Control 23 output voltage data of the second cache unit.
In addition, in practical applications, above-mentioned logical-sequential control unit 21, the first cache unit 22, the second cache unit
23, memory 30 and digital analog converter 40 are integrated in a chip, and the output voltage of the chip is typically small, so that number
The value for the corresponding electric signal of digital signal that mode converter 40 exports is also smaller, so that the electric signal provides for public electrode
Common voltage be unsatisfactory for the desired value of public electrode.
For these reasons, the electric signal for needing logarithm mode converter 40 to export amplifies.Specifically, as shown in figure 9,
Above-mentioned display panel, drive circuit 01 further includes amplification voltage regulator circuit 50.Wherein, amplification voltage regulator circuit 50 includes the first pressure stabilizing mould
Block 51, amplification module 52 and the second Voltage stabilizing module 53.
Specifically, the first Voltage stabilizing module 51 is connected with digital analog converter 40, the first Voltage stabilizing module 51 is for stablizing digital-to-analogue
The voltage signal that converter 40 exports.
Amplification module 52 is connected with the first Voltage stabilizing module 51, what amplification module 52 was used to export the first Voltage stabilizing module 51
Voltage amplifies.
Second Voltage stabilizing module 53 is connected with amplification module 52, and the second Voltage stabilizing module 53 is for stablizing the output of amplification module 52
Voltage signal.
The specific structure of amplification voltage regulator circuit 50 is described in detail below.As shown in Figure 10, the first Voltage stabilizing module
51 include first voltage follower；Amplification module 52 includes transistor M1,3rd resistor R3, the 4th resistance R4, the 5th resistance R5；
Second Voltage stabilizing module 53 includes second voltage follower OP2.
Specifically, the output end of the first input end connection digital analog converter 40 of first voltage follower OP1, output end connect
Connect the grid of transistor M1.The second input terminal and transistor M1 of one end connection first voltage follower OP1 of 5th resistance R5
The second pole, the other end ground connection.One end of 3rd resistor R3 connects voltage input end VDD, and the other end connects the of transistor M1
One pole.The first pole of one end connection transistor M1 of 4th resistance R4, other end ground connection.The first of second voltage follower OP2
Input terminal connects the first pole of transistor M1, and the second input terminal connects output end.
The working principle of above-mentioned amplification voltage regulator circuit 50 is illustrated below.As shown in figure 11, above-mentioned digital analog converter
The analog electrical signal of 40 outputs exports after first voltage follower OP1 stablizes to the grid G of transistor M1, i.e. grid voltage
For VG, hypothesis of embodiment of the present invention grid voltage VGSo that transistor M1 work is in saturation amplification region, transistor M1 is connected at this time,
Then transistor M1 meets following formula:Wherein, VGS=VG-VS, μ is the migration speed of electronics
Rate, W/l are breadth length ratio, COXFor unit area gate oxide capacitance, VGS(th)For the threshold voltage of transistor M1.As transistor M1
After determination, above-mentioned μ, W, COX、VGS(th)And W/l is constant.
As shown from the above formula, as grid voltage VGWhen change, VGSIt can change, thus according to flow through transistor
The electric current I of M1DIt changes, so that the electric current for flowing through the 5th resistance R5 changes.When transistor M1 work is being saturated
When amplification region, the self-resistance of transistor M1 can be ignored.As shown in figure 11, the 4th resistance R4 is in parallel close with the 5th resistance R5
System, the electric current due to flowing through the 5th resistance R5 change, then the voltage at the 5th both ends resistance R5 can change, so that
The voltage at the 4th both ends resistance R4 changes.It is flowed through when flowing through the voltage change at the 4th both ends resistance R4 according to Ohm's law
The electric current at the 4th both ends resistance R4 also changes；Since 3rd resistor R3 and the 4th resistance R4 is series relationship, then the is flowed through
The electric current I of three resistance R3R3Also it can change.As shown in Figure 10,3rd resistor R3 and the node of the 4th junction resistance R4 electricity
Press Vout=VDD-IR3× R3, due to flowing through the electric current I of 3rd resistor R3R3It changes, then 3rd resistor R3 and the 4th resistance
The node voltage V of the junction R4outAlso it changes.Then by the node of above-mentioned 3rd resistor R3 and the 4th junction resistance R4
Voltage VoutAfter output carries out pressure stabilizing to second voltage follower OP2, second voltage follower OP2 outputting common voltage Vcom。
In addition, when voltage data is exported according to above-mentioned output timing, when the conversion frequency of the voltage value of output is larger,
Cause the voltage value of output unstable, and then will affect driving effect of the common voltage to sub-pix of output, in order to avoid upper
The occurrence of stating, it is preferred that above-mentioned display panel, drive circuit 01 is as shown in figure 9, further include timer 60.Wherein, timing
Device 60 is connected with processor 20, the output time for any voltage value that timer 60 is exported for control processor 20.
It should be noted that when exporting the benchmark common voltage value V0 in above-mentioned second cache unit 23, the electricity of output
Pressure value is uniquely that there is no need to timers 60 to be timed, and voltage value can be exported directly by digital analog converter 40.
When the multiple voltage data groups cached in exporting above-mentioned first cache unit 22, timer 60 is to multiple voltage numbers
It is controlled according to the output time of the voltage value in group.In order to simplify the display panel, drive circuit 01, it is preferred that processor 20
Each voltage value of output keeps a preset time.If the preset time was less than 1 hour, the transformation frequency of the voltage value of output
Rate is larger, causes the voltage value of output unstable, and then influences driving effect of the common voltage to sub-pix of output；If this is pre-
If the time is greater than 12 hours, the difference between the voltage value and benchmark common voltage value V0 of output can make sub-pix remaining straight
It is larger to flow potential accumulations, and then before exporting next voltage value and being offset to the difference, leads to the appearance of image retention, influences to show
Show the normal display of device.It is therefore preferred that above-mentioned preset time is 1 hour~12 hours.So, on the one hand, when default
Time, in output voltage data, the conversion frequency of the voltage value of output was smaller, and the voltage value of output is more stable less than 1 hour,
Therefore smaller to the driving influential effect of sub-pix to the common voltage of output；On the other hand, processor 20 by voltage value by
It is a when being exported, within 1 hour~12 hours retention time of the voltage value of output, the voltage value and benchmark common electrical of output
Remaining DC voltage in sub-pix caused by difference between pressure value V0, be not enough to the difference be cancelled it is leading disable as
Occur.
It should be noted that in practical applications, above-mentioned logical-sequential control unit 21, the first cache unit 22, second
Cache unit 23, memory 30, timer 60 and digital analog converter 40 are integrated in a chip.If being integrated with crystal oscillator in chip
61, the crystal oscillator 61 in timer 60 and chip cooperates with completion timing function at this time.It, should when in chip without integrated crystal oscillator 61
Display panel, drive circuit 01 further includes crystal oscillator 61, as shown in figure 9, crystal oscillator 61 is connected with timer 60, for being timer
60 provide the clock cycle.
The embodiment of the invention also provides a kind of display devices comprising display panel described in the embodiment of the present invention drives
Dynamic circuit 01.In the specific implementation, display device provided in an embodiment of the present invention can for display base plate, display panel, mobile phone,
Any product having a display function such as tablet computer, television set, display, laptop, Digital Frame, navigator or portion
Part.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can be stored in a computer readable storage medium, the program
When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: ROM, RAM, magnetic disk or light
The various media that can store program code such as disk.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (9)
1. a kind of driving method of display panel characterized by comprising
Controller issues control instruction；
Processor receives the control instruction, and according to the control instruction, voltage data is obtained from memory；
The processor determines benchmark common voltage value from the voltage data, and will be in addition to the benchmark common voltage value
Voltage data in addition is divided into multiple voltage data groups；
Wherein, each described voltage data group includes opposite polarity the first voltage value and second voltage value；First electricity
Pressure value and the second voltage value are equal with the pressure difference of the benchmark common voltage respectively；
The processor exports the first voltage value being located in same voltage data group and second voltage value one by one；
Digital analog converter carries out digital-to-analogue conversion to the voltage value that the processor exports；
The processor determines benchmark common voltage value from the voltage data, and will be in addition to the benchmark common voltage value
Voltage data in addition is divided into after multiple voltage data groups, the driving method further include:
The processor obtains multiple voltage data groups, and successively by the identical voltage value of polarity in the multiple voltage data group
Arrangement, with the output timing of the multiple voltage data groups of determination；
The first voltage value being located in same voltage data group and second voltage value are carried out output by the processor one by one
The processor according to the output timing, will successively be located in same voltage data group in multiple voltage data groups the
One voltage value and second voltage value are exported one by one.
2. driving method according to claim 1, which is characterized in that when the processor will be located at same voltage data group
In the first voltage value and second voltage value when being exported one by one, each voltage value of the processor output keeps one
Preset time, wherein the preset time is 1 hour~12 hours.
3. a kind of display panel, drive circuit characterized by comprising controller, processor, memory and digital-to-analogue conversion
Device；
The memory is for storing voltage data；
The controller is connected with the processor, and the controller is used to export control instruction to the processor；
The processor is also connected with the memory, and the processor is used to be obtained according to the control instruction from the memory
Voltage data is taken, and determines benchmark common voltage value from the voltage data, and will be in addition to the benchmark common voltage value
Voltage data in addition is divided into multiple voltage data groups；The processor be also used to be located in same voltage data group the
One voltage value and second voltage value are exported one by one；
Wherein, each described voltage data group includes opposite polarity the first voltage value and second voltage value；First electricity
Pressure value and the second voltage value are equal with the pressure difference of the benchmark common voltage value respectively；
The digital analog converter is connected with the processor, and the digital analog converter is used for the voltage exported to the processor
Carry out digital-to-analogue conversion；
The processor includes logical-sequential control unit and the first cache unit；
The logical-sequential control unit is connected with the memory, and the logical-sequential control unit is used for from the storage
The voltage data is obtained in device；
First cache unit is connected with the logical-sequential control unit, and first cache unit is for patrolling described
It collects multiple voltage data groups that timing control unit is got from the memory to be cached, and in the logical-sequential control
In will be data cached under the control of unit, the first voltage value and second voltage value in same voltage data group carry out one by one
Output.
4. display panel, drive circuit according to claim 3, which is characterized in that the processor further includes patrolling with described
Collect the second cache unit that timing control unit is connected；The controller includes conversion circuit；Control instruction is opened including first
Open instruction and the second open command；
Second cache unit is used for the benchmark common electrical got to the logical-sequential control unit from the memory
Pressure value is cached, and the voltage value of caching is exported under the control of the logical-sequential control unit；
Conversion circuit is used to export first open command or second open command to the logical-sequential control unit；
The logical-sequential control unit controls the first cache unit output voltage number according to first open command
According to；
Alternatively, the logical-sequential control unit controls the second cache unit output electricity according to second open command
Press data.
5. display panel, drive circuit according to claim 4, which is characterized in that the conversion circuit includes first resistor
And second resistance；
One end of the first resistor connects one end of the logical-sequential control unit, the second resistance, other end connection
Reference power source, the other end ground connection of the second resistance.
6. display panel, drive circuit according to claim 3, which is characterized in that further include amplification voltage regulator circuit；It is described
Amplifying voltage regulator circuit includes the first Voltage stabilizing module, amplification module and the second Voltage stabilizing module；
First Voltage stabilizing module is connected with the digital analog converter, and first Voltage stabilizing module turns for stablizing the digital-to-analogue
The voltage signal of parallel operation output；
The amplification module is connected with first Voltage stabilizing module, and the amplification module is for defeated to first Voltage stabilizing module
Voltage out amplifies；
Second Voltage stabilizing module is connected with the amplification module, and second Voltage stabilizing module is for stablizing the amplification module
The voltage signal of output.
7. display panel, drive circuit according to claim 6, which is characterized in that first Voltage stabilizing module includes first
Voltage follower；The amplification module includes transistor, 3rd resistor, the 4th resistance, the 5th resistance；Second Voltage stabilizing module
Including second voltage follower；
Wherein, the first input end of the first voltage follower connects the output end of the digital analog converter, output end connection
The grid of the transistor；
One end of 5th resistance connects the second pole of the second input terminal of the first voltage follower, the transistor,
Other end ground connection；
One end of the 3rd resistor connects voltage input end, and the other end connects the first pole of the transistor；
One end of 4th resistance connects the first pole of the transistor, other end ground connection；
The first input end of the second voltage follower connects the first pole of the transistor, the connection output of the second input terminal
End.
8. display panel, drive circuit according to claim 3, which is characterized in that it further include timer, the timer
It is connected with the processor, the timer is used to control the output time of any voltage value of the processor output.
9. a kind of display device, which is characterized in that including display panel, drive circuit described in any one of claim 3-8.
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| CN107193147B (en) * | 2017-07-24 | 2020-05-05 | 武汉华星光电技术有限公司 | Touch display panel, display method thereof and display device |
| CN108428437B (en) * | 2018-04-03 | 2021-02-19 | 昆山龙腾光电股份有限公司 | Public voltage driving circuit, control method thereof and display device |
| CN109308885A (en) * | 2018-12-11 | 2019-02-05 | 惠科股份有限公司 | Method for improving signal transmission rate and display panel |
| CN110148386A (en) * | 2019-05-08 | 2019-08-20 | 深圳市华星光电技术有限公司 | Common voltage provides circuit and display panel |
| US20240161680A1 (en) * | 2022-11-10 | 2024-05-16 | Novatek Microelectronics Corp. | Timing controller and polarity control method thereof |
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| CN105355185B (en) * | 2015-12-14 | 2018-08-03 | 厦门天马微电子有限公司 | Driving circuit, display device and its driving method of display panel |
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