CN106531045B

CN106531045B - Timing controller and display device including the same

Info

Publication number: CN106531045B
Application number: CN201510578973.8A
Authority: CN
Inventors: 詹劲峰; 车致镐
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2015-09-11
Filing date: 2015-09-11
Publication date: 2021-06-22
Anticipated expiration: 2035-09-11
Also published as: CN106531045A

Abstract

The present invention provides a timing controller and a display device including the timing controller. The timing controller includes: a memory controller that reads compressed LUT data from an external memory; a decompressor that decompresses the compressed LUT data received from the memory controller and generates original LUT data before compression ; temporarily store the line buffer of the original LUT data received from the decompressor; use the original LUT data stored in the line buffer to compensate the MURA defect (MURA defect of the input image signal data) ) of the image signal processing section.

Description

Time schedule controller and display device comprising same

Technical Field

The invention relates to a time schedule controller and a display device comprising the same.

Background

A display device generally includes a display panel and a driving unit of the display panel. The display panel comprises a plurality of gate lines, a plurality of data lines and a plurality of pixels. The driving part of the display panel comprises a time schedule controller, a grid driver and a source driver.

Generally, the pixel includes a plurality of transistors, a storage capacitor, and an organic light emitting element. The difference in luminance between the pixels caused by the threshold voltage distribution of the transistors has a problem of generation of a MURA defect. The panel that produces such a MURA defect is called a MURA panel (MURA panel).

In this case, in order to compensate for the MURA defect, a Look-Up Table (LUT) may be used. However, recently, the resolution of the display panel becomes higher, and as the number of bits used for the LUT increases, the size of the LUT also increases, and thus there is a problem that a larger memory capacity is required to store the LUT. In addition, in order to reduce the size of the LUT as a whole, there is a problem that when one LUT data is used per specific unit pixel, the quality of compensation for the trace defect is degraded.

Disclosure of Invention

The present invention provides a timing controller capable of reducing the size of a memory required for storing LUT data and compensating for MURA defects of a display panel with high quality.

Another object of the present invention is to provide a display device capable of compensating for MURA defects of a display panel with high quality while reducing the size of a memory required for storing LUT data.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not yet mentioned will be apparent to those skilled in the art from the following descriptions.

In order to solve the above-described problem, a timing controller according to the present invention includes: a memory controller that reads the compressed LUT data from the external memory; a decompressor for decompressing said compressed LUT data received from said memory controller and generating pre-compressed raw LUT data; a line buffer to temporarily store the raw LUT data received from the decompressor; and an image signal processing unit for compensating for a MURA defect (MURA defect) in the input image signal data by using the original LUT data stored in the line buffer.

In some embodiments of the present invention, the image signal processing section may include: a demura control unit that reads the original LUT data from the line buffer, receives the image signal data from an external device, and synchronizes the original LUT data and the image signal data; a de-MURA processing section receiving the raw LUT data and the image signal in synchronization from the de-MURA control section, and eliminating the MURA defect contained in the image signal using the raw LUT data, thereby generating compensated image signal data.

In some embodiments of the present invention, the MURA defect may include a non-uniform contrast, luminance or brightness value between image signals of adjacent pixels.

In some embodiments of the invention, the decompressor may generate the raw LUT data from the compressed LUT data using a lossless decompression algorithm.

In some embodiments of the invention, the lossless decompression algorithm may comprise a CTW, LZ77, or LZW decompression algorithm.

In some embodiments of the invention, the image signal data comprises data for N pixels (N being a positive integer), and the raw LUT data may comprise compensation values for all of the N pixels.

In some embodiments of the present invention, the image signal data includes data on L × M pixels (the L and M are positive integers), and the original LUT data may include compensation values corresponding to the L vertical lines and compensation values corresponding to the M horizontal lines.

In some embodiments of the present invention, the image signal data comprises data for N pixels (N being a positive integer), and the raw LUT data may comprise one compensation value for every K unit pixels (K being a positive integer smaller than N).

In some embodiments of the present invention, the timing controller may be included in a semiconductor package without the external memory.

In order to solve the above problem, a display device according to the present invention includes: a display panel; an external memory storing compressed LUT data; an image capturing means for capturing a plurality of output images of the display panel for a plurality of input images for uniformity test, and generating original LUT data corresponding to compensation data based on the captured plurality of output images, and storing compressed LUT data in the external memory; and a timing controller for compensating for a MURA defect included in image signal data input from the outside using the compressed LUT data stored in the external memory, and supplying the compensated image signal data to the display panel.

In some embodiments of the present invention, the image capturing apparatus may include: a controller for applying the plurality of input images for uniformity test to the display panel; a camera that captures a plurality of output images of the display panel; a processor for generating the raw LUT data corresponding to compensation data based on the captured plurality of output images; a compression compressor of the original LUT data; an interface section for transferring the compressed LUT data to the external memory.

In some embodiments of the invention, the compressor may utilize a CTW, LZ77, or LZW compression algorithm to compress the raw LUT data.

In some embodiments of the invention, the image capture device may be included within the timing controller.

In some embodiments of the present invention, the image capturing apparatus may be included in a semiconductor package separate from the timing controller and the external memory.

In some embodiments of the present invention, the timing controller may include: a memory controller that reads compressed LUT data from the external memory; a decompressor for decompressing said compressed LUT data and generating said original LUT data prior to compression; a line buffer to temporarily store the raw LUT data received from the decompressor; and an image signal processing unit for compensating for the MURA defect of the input image signal data by using the original LUT data stored in the line buffer.

In some embodiments of the invention, the decompressor may process the raw LUT data using an algorithm complementary to the compressor.

In some embodiments of the present invention, the timing controller may be included in a semiconductor package separate from the external memory and the image capturing device.

Another aspect of the display device of the present invention for solving the above problems includes: a plurality of pixels respectively arranged at crossing regions of the plurality of gate lines and the plurality of data lines; a gate driver driving the plurality of gate lines; a source driver driving the plurality of data lines; an external memory storing compressed LUT data; and a timing controller for controlling the gate driver and the source driver in response to image signal data and a control signal inputted from the outside, compensating for a MURA defect included in the inputted image signal data using the compressed LUT data stored in the external memory, and supplying the compensated image signal data to the source driver.

In some embodiments of the present invention, the method may further comprise: and an image capturing device for capturing a plurality of output images of the plurality of pixels for each of a plurality of uniformity test input images, generating original LUT data corresponding to the compensation data based on the plurality of captured output images, and storing the compressed LUT data in the external memory.

In some embodiments of the present invention, the image capturing apparatus may include: a control unit for applying the plurality of uniformity test input images to the plurality of pixels; a camera that captures a plurality of output images with respect to respective ones of the plurality of pixels; a processor for generating raw LUT data corresponding to compensation data based on the plurality of captured output images; a compressor to compress the original LUT data; an interface section for transferring the compressed LUT data to the external memory.

In some embodiments of the present invention, the timing controller may be included in a semiconductor package separate from the external memory.

Other embodiments of the invention are included in the detailed description and the accompanying drawings.

Drawings

Fig. 1 is a block diagram for explaining a display device according to an embodiment of the present invention.

Fig. 2 is a block diagram for explaining the timing controller shown in fig. 1.

FIG. 3 is a block diagram of an embodiment of the video signal processing unit of FIG. 2.

Fig. 4 is a block diagram for explaining a display device according to another embodiment of the present invention.

Fig. 5 is a block diagram for explaining a display device according to still another embodiment of the present invention.

FIG. 6 illustrates a block diagram of an image capture device according to some embodiments of the inventions.

FIG. 7 is a flow chart of a method of operation of an image capture device according to some embodiments of the invention.

Fig. 8 is a diagram of a display module according to an embodiment of the present invention.

Fig. 9 is a diagram of a display system according to an embodiment of the present invention.

Fig. 10 is an illustration of applications in which a display device according to some embodiments of the invention is mounted on a variety of electronic products.

Detailed Description

The advantages, features and methods of accomplishing the same will become apparent from the drawings and the detailed description of the embodiments that follow. However, the present invention is not limited to the embodiments described herein, and may be embodied in other different forms. Rather, the embodiments disclosed herein make the present invention more complete and provide those skilled in the art with a complete idea of the present invention. The invention is defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The term "connected" or "coupled" between one element and another element means that the element is directly connected to the other element or that the element is connected to the other element with interposition of another element. On the other hand, the term "directly connected" or "directly coupled" to one element or another means that there is no intervening element or elements present. Like reference numerals refer to like elements throughout the specification. "and/or" is inclusive of all combinations of each item and more than one.

For the purpose of describing various elements, components and/or sections, it is to be understood that these elements, components and/or sections are not limited by these terms, although 1 st, 2 nd, etc. terms are used. These terms are only used to distinguish one element, component, and/or section from another element, component, and/or section. Therefore, the 1 st element, the 1 st component or the 1 st part mentioned in the present specification may be the 2 nd element, the 2 nd component or the 2 nd part within the technical idea of the present invention.

The terminology used in the description is for the purpose of describing the embodiments and is not intended to be limiting of the invention. The singular references include the plural references unless the context clearly dictates otherwise. The terms "comprising," "including," or "having," and the like, as used in the specification, do not preclude the presence or addition of one or more other components, steps, acts, and/or elements.

Unless defined otherwise, all terms (including technical and scientific terms) used in the specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Also, terms defined in a commonly used dictionary should not be interpreted as meanings in an ideal or exaggerated form without specific definitions.

Hereinafter, a timing controller and a display device including the same according to some embodiments of the present invention will be described with reference to fig. 1 to 10.

Referring to fig. 1, a display device 1000 according to one line embodiment of the present invention may employ any one of various display devices. For example, it may be an organic Light emitting diode display Device (OLED), a liquid crystal display Device (LCD), an electrochromic display (ECD), a Digital Micromirror Device (DMD), an Actuated Micromirror Device (AMD), a GLV (Grating Light value), a Plasma Display Panel (PDP), or an electroluminescent display (ELD). Hereinafter, the display panel will be described by taking an organic light emitting panel as an example.

Specifically, the display device 1000 includes a display panel 1100 and a display driving circuit 1201.

The display panel 1100 includes: a plurality of gate lines GL1 to GLj for transmitting scanning signals in a row direction; a plurality of data lines DL1 to DLk arranged in a direction intersecting the gate lines and transmitting data signals in a column direction; a plurality of pixels PX arranged in regions where the gate lines GL1 to GLj and the data lines D1 to Dk intersect.

When the plurality of gate lines GL1 to Gj are sequentially selected, the gray-scale voltage Vg is applied to the pixels PX connected to the selected gate lines through the plurality of data lines DL1 to DLk.

Each pixel PX may include: a switching transistor Tsw, a driving transistor Tdrv, a storage capacitor Cst, and an organic light emitting diode D. The gate line GL and the data line DL are connected to a gate electrode and a source electrode of the switching transistor Tsw, a drain electrode of the switching transistor Tsw and the power voltage VDD are connected to a gate electrode and a source electrode of the driving transistor Tdrv, respectively, and a drain electrode of the driving transistor Tdrv is connected to an anode electrode of the organic light emitting diode D.

In such a pixel structure, when the gate line GL is selected, the switching transistor Tsw is turned on, and the gray-scale voltage supplied thereto is applied to the gate of the driving transistor Tdrv through the data line DL, and the driving current Idrv flows through the organic light emitting diode D to emit light according to a voltage difference between the driving power voltage VDD and the gray-scale voltage, thereby completing the display operation.

The display driving circuit 1201 may include: a timing controller 100, a source driver 200, a gate driver 300, a voltage generator 400, a 1 st interface circuit 500, a 2 nd interface circuit 340, and an external memory 190.

The timing controller 100 may receive the 1 st image signal data RGB and the 1 st command CMD1 from the outside (e.g., a system host in which the display device 1000 is mounted), and provide the source driver 200 and the gate driver 300 with control signals CNT1, CNT2, and the 2 nd image signal data RGB'.

Specifically, the timing controller 100 may control the gate driver 300 and the source driver 200 in response to image signal data and a control signal inputted from the outside, compensate for a MURA defect (MURA defect) included in the inputted image signal data using compressed LUT data stored in the external memory 190, and supply the compensated image signal data to the source driver 200.

In this case, the timing controller 100 may include: memory controller 110, decompressor 120, line buffer 130, and image signal processing section 140. Specific components of the timing controller 100 and the operation of these components will be described later with reference to fig. 2.

The external memory 190 may function as an operation memory required for the timing controller 100 to operate. In some embodiments of the present invention, the external memory 190 may be configured outside the timing controller 100 as shown. Specifically, the external memory 190 may be packaged in a package on package (PoP) type, which is different from the timing controller 100. The invention is not so limited.

The source driver 200 converts digital data (i.e., 2 nd image signal data RGB') applied from the timing controller 100 into gray scale voltages and outputs the gray scale voltages to the data lines DL1 to DLk of the panel 1100. The gate driver 300 sequentially scans the gate lines GL1 to GLj of the panel 1100. The gate driver 300 applies the turn-on voltage Von to a selected gate line to activate the selected gate line, and the source driver 200 outputs a corresponding gray scale voltage to pixels connected to the activated gate line. Thus, the panel 1100 displays an image in units of horizontal lines, i.e., line by line.

The voltage generator 400 receives a power supply Voltage (VCI) applied from the outside, and generates voltages AVDD, Von, and Voff required by the source driver 200 and the gate driver 300.

The 1 st interface circuit 500 is used to communicate with a host (e.g., an application processor). The 1 st interface circuit 500 receives the 1 st image signal data RGB and the 1 st command CMD1 applied in parallel or in series by the host, and supplies the 1 st image signal data RGB and the 1 st command CMD1 to the timing controller 100. The 1 st image signal data RGB and the 1 st command CMD1 may be transmitted by a system host on which the display device 1000 is loaded. The 1 st interface circuit 500 may receive the 1 st image signal data RGB and the 1 st command CMD1 in an interface method corresponding to the host transfer method. For example, the interface mode used by the interface circuit 1 may be one of an RGB interface, a CPU interface, a Service provider interface (PSI), a Mobile Display Digital Interface (MDDI) and a Mobile Industry Processor Interface (MIPI).

The 2 nd interface circuit 340 is for communicating with other display driving circuits, i.e., the 2 nd display driving circuit (not shown). The 2 nd interface circuit 340 may provide the 1 st sync signal SSYNC1 generated by the timing controller 100 to the 2 nd display driving circuit (not shown). The 1 st sync signal SSYNC1 is responsive to the end signal EXE, and a signal generated thereby. Interface 2 circuit 340 may be a different form of interface than interface 1 circuit 500. For example, Interface 2 circuit 340 may be a Serial Peripheral Interface (SPI), inter-integrated circuit (I)²C: inter Integrated Circuit), etc., but is not limited thereto.

Fig. 2 is a block diagram for explaining the timing controller shown in fig. 1. FIG. 3 is a block diagram of an embodiment of the video signal processing unit of FIG. 2.

Referring to fig. 2, a Timing Controller (TCON)100 according to an embodiment of the present invention may include: a memory controller 110, a decompressor 120, a line buffer 130, and an image signal processing section 150.

The memory controller 110 may be connected to an external memory 190.

In particular, memory controller 110 is configured to access external memory 190. For example, the memory controller 110 is configured to control read, write, erase, and background (background) actions of the external memory 190. The memory controller 110 is configured to provide an interface between the external memory 190 and the timing controller 100. Memory controller 110 is configured to drive firmware that controls external memory 190. Thus, the memory controller 110 may read the compressed LUT data from the external memory 190. The memory controller 110 may then transfer the read compressed LUT data to the decompressor 120.

Decompressor 120 may decompress the compressed LUT data received from memory controller 110 to produce the original LUT data before compression. The raw LUT data may include data for compensating for MURA defects of the display panel 1100. The MURA defect may include having non-uniform contrast, luminance or brightness values between image signals of adjacent pixels.

Therefore, when the display panel 1100 has the MURA defect, a difference in contrast, luminance, or brightness value is significantly generated between the 1 st pixel and the 2 nd pixel adjacent to the 1 st pixel. Such MURA defects may include line MURA, (black spot MURA), (white spot MURA), (black area MURA), (white area MURA), (ring MURA), and the like.

Decompressor 120 may generate raw LUT data from the compressed LUT data using a lossless decompression algorithm. At this time, the lossless decompression algorithm may include a CTW, LZ77, or LZW decompression algorithm. The lossless decompression algorithm is a well-known technique, and a detailed description thereof is omitted. The decompressor 120 may then transmit the raw LUT data to the line buffer 130.

A line buffer 130 may temporarily store the raw LUT data received from the decompressor 120. Since the line buffer 130 has a relatively large size of the original LUT data, the original LUT data can be temporarily stored in order to operate the image signal processing unit 150 when the compressed LUT data is decompressed. Thereby, the image signal processing section 150 can continuously receive the original LUT data. Also, the line buffer 130 may play a role of buffering between the image signal processing section 150 and the decompressor 120 in order to minimize a time delay required for decompressing the compressed LUT data at the decompressor 120. However, the present invention is not limited thereto, and the line buffer 130 may be omitted when the decompressor 120 has a high data processing speed.

Referring to fig. 2 and 3, the image signal processing part 150 may compensate for the MURA defect of the input 1 st image signal data RGB using the original LUT data stored in the line buffer 130 to generate 2 nd image signal data RGB'.

Specifically, the image signal processing section 150 may include: a demura control unit 152(De-MURA controller), and a demura processing unit 154(De-MURA core).

The demura control section 152 may synchronize the raw LUT data and the image signal after reading the raw LUT data from the line buffer 130 and receiving the 1 st image signal data RGB from an external device. The demura control section 152 may transmit the raw LUT data and the image signal aligned (aligning) to the demura processing section 154.

The demura processing section 154 receives the synchronized original LUT data and the image signal from the demura control section 152, and eliminates the MURA defect included in the image signal using the original LUT data, thereby generating the compensated 2 nd image signal data RGB'.

Specifically, the demura process section 154 changes the 1 st image signal data RGB into the 2 nd image signal data RGB' for compensating the MURA defect by using the original LUT data. In this case, the demura processing section 154 may use a MURA correction algorithm (MURA correction algorithm) such as a brute-force algorithm (brute-force algorithm), for example, in order to compensate the 1 st image signal data RGB to the 2 nd image signal data RGB'. Thus, the MURA panel (MURA panel) in which the MURA defect occurs can be the display panel 1100 that operates normally. However, the raw LUT data used to enable the MURA correction algorithm may require a relatively large memory capacity, thereby creating a burden of requiring a relatively large memory device. Therefore, in the present invention, the original LUT data is compressed by the compression algorithm, whereby the compressed LUT data reduced to require a small memory capacity can be stored in the external memory 190. In addition, the external memory 190 is separated from the memory controller 110, whereby the size and manufacturing cost of the memory controller 110 can be reduced.

In embodiments of the present invention in which the display device 1000 includes N (where, N is a natural number) pixels, the 1 st image signal data RGB may have data on the N pixels. Also, the raw LUT data may contain compensation values corresponding to all of the N pixels. That is, the raw LUT data may have MURA defect compensation values for all of the individual pixels. In this case, the compensation processing quality regarding the MURA defect is high, but the memory capacity for storing the original LUT data increases.

In another embodiment of the present invention, the display device 1000 includes N (here, N is a natural number) pixels, and the 1 st image signal data RGB may have data on the N pixels. Also, the original LUT data may contain one compensation value for every K unit pixels (here, K is a natural number smaller than N). That is, the original LUT data may have MURA defect compensation values with respect to the respective unit pixels. In this case the compensation process for MURA defects is of somewhat lower quality, but the memory capacity for storing the raw LUT data is somewhat reduced.

In still another embodiment of the present invention, the display device 1000 includes L × M (here, L and M are natural numbers) pixels, and the 1 st image signal data RGB may have data on the L × M pixels. Also, the original LUT data may contain compensation values corresponding to the L vertical lines, and compensation values corresponding to the M horizontal lines. That is, the original LUT data may have MURA defect compensation values corresponding to vertical and horizontal lines of the display panel 1100, respectively. In this case the compensation process for MURA defects is of low quality, but the memory capacity for storing the raw LUT data is significantly reduced.

As such, to compensate for the MURA defect, the LUT may be utilized. However, recently, the resolution of the display panel becomes higher, and as the number of bits used by the LUT increases, the size of the LUT also increases, and thus, a larger memory capacity is required for storing the LUT. In addition, in order to reduce the size of the entire LUT, when one LUT data is used per specific unit pixel, the compensation quality of the MURA defect is degraded. In order to solve such a problem, the display device 1000 according to an embodiment of the present invention compresses the original LUT data and stores the compressed LUT data in the external memory 190, and can perform high-quality compensation processing on a display panel including a MURA defect using a small memory capacity.

In addition, the memory controller 110 and the external memory 190 are separated, whereby the size and manufacturing cost of the memory controller 110 can be reduced.

As described above, some of the original LUT data for compensating the MURA defect may be selected in consideration of the display apparatus and various condition matters. The invention is not so limited.

Fig. 4 is a block diagram for explaining a display device according to another embodiment of the present invention. Fig. 5 is a block diagram for explaining a display device according to still another embodiment of the present invention. For convenience of explanation, the same matters as those in the previously explained embodiment will be omitted from the explanation, and the explanation will be mainly focused on the differences.

Referring to fig. 4 and 5, the

display devices

1001 and 1002 according to some embodiments of the present invention include a display panel 1100, a timing controller 100, and an external memory 190. Actually, the

display devices

1001 and 1002 can perform the same operation as the display device 1000 described with reference to fig. 1.

The

display devices

1001, 1002 according to some embodiments of the present invention may also include an image capture device 160.

The image capturing apparatus 160 may capture an image output at the display panel 1100. Specifically, the contrast, luminance, or brightness value of each pixel included in the display panel 1100 may be captured. This makes it possible to determine whether or not the display panel 1100 has a MURA defect. When there is a MURA defect on the display panel 1100, the image capturing apparatus 160 may calculate a compensation value regarding the MURA defect and then generate raw LUT data including the compensation value.

Specifically, the image capturing apparatus 160 may capture a plurality of output images of the display panel 1100 with respect to a plurality of uniformity test input images (series of uniform test input images), generate raw LUT data corresponding to the compensation data based on the plurality of captured output images, and store the compressed LUT data in the external memory 190. Then, the timing controller 100 may compensate for a MURA defect included in image signal data input from the outside using the compressed LUT data stored in the external memory 190 and provide the compensated image signal data to the display panel 1100. By this compensation, the display panel 1100 that outputs the MURA defect (i.e., the MURA panel) operates in the normal range.

In the display device 1001 according to another embodiment of the present invention, the image capturing device 160 may be included in a semiconductor package separate from the timing controller 100 and the external memory 190. That is, it may be formed with a module separate from the timing controller 100 and the external memory 190.

However, the present invention is not limited thereto, and in the display device 1002 according to still another embodiment of the present invention, the image capturing device 160 may be included in the timing controller 100. In this case, however, the timing controller 100 and the image capturing apparatus 160 may be included in a semiconductor package separate from the external memory 190.

FIG. 6 shows a block diagram of an image capture device according to some embodiments of the invention.

Referring to fig. 6, an image capture device 160 according to some embodiments of the present invention may include a camera 161, a processor 162, a compressor 163, a controller 164, an interface section 165, an internal memory 166, and a bus 167. The camera 161, the processor 162, the compressor 163, the controller 164, the interface section 165, and the internal memory 166 may be combined with each other via a bus 167. The bus 167 corresponds to a path (path) for data movement.

The camera 161 may include an image sensor. The camera 161 may capture an image output at the display panel 1100. In particular, a plurality of output images of the display panel 1100 may be captured. For example, the camera 161 may capture a contrast, illumination, or brightness value of each pixel included in the display panel 1100. The invention is not so limited. The values thus captured may be temporarily stored in the internal memory 166 and may be utilized for calculations by the processor 162.

Processor 162 may perform the operations necessary to drive image capture device 160. In some embodiments of the invention, processor 162 may be configured as a multi-core environment comprising a plurality of cores. The processor 162 may generate raw LUT data corresponding to the compensation data based on a plurality of output images captured by the camera 161.

The compressor 163 may compress the raw LUT data. At this time, the compressor 163 may compress the original LUT data using a compression algorithm. The compression algorithm may be in a complementary relationship to the decompression algorithm used by the decompressor 120 of the timing controller 100. For example, compressor 163 may compress the raw LUT data using a CTW, LZ77, or LZW compression algorithm. The compressed LUT data may be temporarily stored in the internal memory 166 and then transferred to the external memory 190. However, depending on the data transfer capability of the interface section 165, the data can be directly transferred to the external memory 190 without passing through the internal memory 166.

The controller 164 may control the overall operation of the image capture device 160. The controller 164 may comprise at least one of a microprocessor, digital signal processing, microcontroller, and logic elements capable of performing similar functions to these. Specifically, the controller 164 may perform an instruction to apply a plurality of uniformity test input images (series of uniformity test input images) to the display panel 1100, and then may control the camera 161 to capture an output image of the display panel 1100 related to the uniformity test. The invention is not so limited. The plurality of input images for uniformity test are input values for confirming whether there is a MURA defect on the display panel 1100 and generating basic data as compensation data. A plurality of input images for uniformity testing may be transmitted to the display panel 1100 through the timing controller 100.

The interface section 165 may perform a function of transmitting data to or receiving data from a communication network. The interface portion 165 may be wired or wireless. For example, the interface section 165 may include an antenna, a wired/wireless general-purpose transceiver, and the like. The interface 165 can provide an environment necessary for a clear connection with an external device (for example, a motherboard). Thus, the interface section 165 can be provided with various channels and ports so as to be interchangeable with an external device connected to the image capturing apparatus 160. The interface section 165 may transfer the compressed LUT data from the compressor 163 to the external memory 190.

Internal memory 166 may store data and/or instructions and the like that are processed internally within image capture device 160. The internal memory 166 may provide an environment for the processor 162 to connect to external devices for high-speed operation. The internal memory 166 may temporarily store a plurality of input image values for uniformity measurement, LUT data compressed by the compressor 163, or the like. However, the present invention is not limited thereto.

Referring to fig. 6 and 7, first, the controller 164 of the image capturing apparatus 160 applies the plurality of uniformity test input images to the display panel 1100. Next, the camera 161 captures a plurality of output images of the display panel 1100 for the plurality of input images for uniformity test (S210).

Next, the processor 162 performs a calibration (calibration) operation on the plurality of output images (S220). The calibration operation refers to calibration of a plurality of images, and a focus (focus), a tone scale (tone scale), sensitivity (sensitivity), and the like of each image may be calibrated. The invention is not so limited.

Next, the processor 162 generates the original LUT data corresponding to the compensation data based on the calibrated plurality of output images (S230). In this case, for the input for the uniformity test, the compensation data may be formed based on different points with respect to the plurality of output image data. As described above, the raw LUT data may contain compensation values for all pixels, or may contain compensation values for only horizontal or vertical lines, or may contain one compensation value for each unit pixel. The invention is not so limited.

Next, the compressor 163 compresses the original LUT data to generate compressed LUT data (S240). At this time, the compressor 163 utilizes a compression algorithm, which may include, for example, a CTW, LZ77, or LZW compression algorithm. Also, the algorithm may be in a complementary relationship to the decompression algorithm used by the decompressor 120.

Next, the interface section 165 transfers the compressed LUT data to the external memory 190 (S250). The compressed LUT data stored in the external memory 190 can be utilized by the timing controller 100. The timing controller 100 may compensate for the MURA defect included in the input image signal data using the compressed LUT data stored in the external memory 190, and transmit the compensated image signal data to the display panel 1100. Specifically, the timing controller 100 may include: a memory controller 110 that reads compressed LUT data from the external memory 190; a decompressor 120 which decompresses the compressed LUT data and generates the original LUT data before compression; a line buffer 130 for temporarily storing the raw LUT data received from the decompressor 120; and an image signal processing unit 150 for compensating for the MURA defect of the input image signal data by using the raw LUT data stored in the line buffer 130.

Thus, the display device can perform high-quality full-frame compensation processing operation using a small amount of memory. In addition, the memory controller 110 is separated from the external memory 190, so that the size and manufacturing cost of the memory controller 110 can be reduced.

Referring to fig. 8, the display module 2000 may include a display device 2100, a polarizing plate 2200, and a window glass 2301. The display device 2100 includes a display panel 2110, a printed circuit board 2120, and a display driver chip 2130.

The window glass 2301 is generally made of acryl or tempered glass, and protects the display module 2000 from scratches caused by external impact or repeated touch. The polarizing plate 2200 is used to improve the optical characteristics of the display panel 2110. The display panel 2110 is formed on a printed circuit board 2120 by patterning a transparent electrode. The display panel 2110 includes a plurality of pixel units for displaying a frame. According to an embodiment, the display panel 2110 may be an organic light emitting diode panel. The pixel unit includes an organic light emitting diode that emits light in response to a flow of current. But is not limited thereto, the display panel 2110 may include various display elements. For example, the display panel 2110 may be one of an LCD, ECD, DMD, AMD, GLV, PDP, ELD, LED display, VFD.

The display driver chip 2130 may include the display driver circuit described above. In the present embodiment, the chip is shown, but not limited thereto. A plurality of driving chips may be mounted. Also, a COG type may be mounted on the printed circuit board 2120 of a glass material. This is merely an example, and the display driver chip 213O may be mounted in various forms such as COF, COB, etc.

The display module 2000 may further include a touch panel 2300 and a touch controller 2400. The touch panel 2300 is formed by patterning a transparent electrode, which is the same as ito (indium Tin oxide), on a glass substrate or a pet (polyethylene terephthalate) film. The touch controller 2400 detects a touch on the touch panel 2300, calculates touch coordinates, and transmits the calculated touch coordinates to a host computer (not shown). The touch controller 2400 may be integrated with the display driver chip 2130 on one semiconductor chip.

Referring to fig. 9, the display system 3000 may include a processor 3100, a display device 3200, a peripheral device 3300, and a memory 3400 electrically connected to the system bus 3500.

The processor 3100 controls data input and output of the peripheral device 3300, the memory 3400, and the display device 3200, and may perform image data processing transferred between the devices.

The display device 3200 includes a panel 3210 and a driving circuit 3220, and image data applied through the system bus 3500 is stored in a frame memory included in the driving circuit 3220 and then displayed on the panel 3210. The display device 3200 may be the display device 1000 of fig. 1. Therefore, the processor 3100 and the processor 3100 are asynchronously operated, so that the load on the system of the processor 3100 can be reduced.

The peripheral device 3300 may be a device such as a camera, a scanner, a web camera, or the like that converts a video or still image into an electric signal. Image notes obtained by the peripheral device 3300 may be stored in the memory 3400 or displayed on a panel of the display device 3200 in real time.

The memory 3400 may include volatile memory elements such as DRAM and/or non-volatile memory elements such as flash memory. The memory 3400 may be composed of DRAM, PRAM, MRAM, ReRAM, FRAM, NOR flash, NAND flash, and fusion flash (e.g., a memory logically combined by SRAM buffers, NAND flash, and NOR interface), and the like. The memory 3400 may store image data obtained from the peripheral device 3300 or image signals processed in the processor 3100.

The display system 3000 according to an embodiment of the present invention may include a mobile electronic product such as a smart phone. But is not limited thereto. The display system 3000 may include various electronic products that display images.

The display device 4000 according to some embodiments of the present invention may be used on various electronic products. The system can be widely used not only in a mobile phone 4100 but also in a TV 4200, an ATM 4300 for automatically drawing cash instead of bank, an elevator 4400, an automatic ticket vending machine 4500 used in a subway station, etc., a PMP 4600, an e-book4700, a navigation device 4800, etc.

The display device 4000 according to some embodiments of the present invention may operate asynchronously with the processor of the system. Therefore, the driving load of the processor is reduced, the processor can be operated at a high speed with low power, and the functions of the electronic product can be improved. The display device 4000 compresses the original LUT data related to the MURA panel and stores the compressed data in an external memory separate from the timing controller, thereby using a small memory capacity and also performing a high-quality compensation process on a display panel including MURA defects.

Although the embodiments of the present invention have been described with reference to the drawings, those skilled in the art of the present invention will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the described embodiments are illustrative in all respects, and are not intended to limit the invention.

Claims

1. a sequence controller, is characterized in that, comprises:

The memory controller reads the compressed look-up table LUT data from the external memory;

a decompressor that decompresses the compressed LUT data received from the memory controller and generates original LUT data before compression;

line buffer, which temporarily stores raw LUT data received from the decompressor;

The image signal processing part uses the original LUT data stored in the line buffer to compensate the MURA defect of the input image signal data,

Among them, the image signal processing part includes:

Go to the MURA control section, read the original LUT data from the line buffer, and after receiving the image signal data from the external device, synchronize the original LUT data and the image signal data; and

The de-MURA processing section receives the synchronized original LUT data and image signal data from the de-MURA control section, and uses the original LUT data to eliminate MURA defects contained in the image signal data, thereby generating compensated image signal data.

2. The timing controller according to claim 1, wherein,

MURA defects include non-uniform contrast, illuminance, or brightness values between the image signals of adjacent pixels.

3. The timing controller of claim 1, wherein the decompressor generates the original LUT data from the compressed LUT data using a lossless decompression algorithm.

4. The timing controller of claim 3, wherein the lossless decompression algorithm comprises a CTW, LZ77, or LZW decompression algorithm.

5. The timing controller according to claim 1, wherein,

The image signal data contains data about N pixels, where N is a positive integer,

The original LUT data contains all compensation values corresponding to N pixels.

6. The timing controller according to claim 1, wherein,

The image signal data contains data on L×M pixels, where L and M are positive integers,

The original LUT data includes compensation values corresponding to L vertical lines and compensation values corresponding to M horizontal lines.

7. The timing controller of claim 1, wherein,

The original LUT data contains a compensation value for every K unit pixels, where K is a positive integer smaller than N.

8. The timing controller of claim 1, wherein,

The timing controller is contained in a semiconductor package that does not contain external memory.

9. A display device, characterized in that, comprising:

display panel;

External memory to store compressed LUT data;

The image capture device captures a plurality of output images of the display panel for a plurality of input images for uniformity testing, and generates original look-up table LUT data corresponding to the compensation data based on the captured plurality of output images, and stores the compressed LUT data in the external memory; and

The timing controller uses the compressed LUT data stored in the external memory to compensate the MURA defect contained in the image signal data input from the outside, and provides the compensated image signal data to the display panel,

wherein the image capture device is configured to perform a calibration operation on the plurality of output images to generate raw look-up table LUT data corresponding to the compensation data, the calibration operation comprising calibrating the focus, tonal range and/or the plurality of output images or sensitivity.

10. The display device of claim 9, wherein the image capture device comprises:

a controller that applies a plurality of input images for uniformity testing to the display panel;

a camera to capture multiple output images of the display panel;

a processor that generates raw LUT data corresponding to the compensation data based on the captured plurality of output images;

a compressor, which compresses raw LUT data; and

The interface unit transfers the compressed LUT data to the external memory.

11. The display device of claim 10, wherein the compressor compresses the original LUT data using a CTW, LZ77 or LZW compression algorithm.

12. The display device of claim 9, wherein the image capture device is included within a timing controller.

13. The display device of claim 9, wherein the image capture device is contained in a semiconductor package separate from the timing controller and the external memory.

14. The display device of claim 9, wherein the timing controller comprises:

Memory controller to read compressed LUT data from external memory;

A decompressor, which decompresses the compressed LUT data and generates the original LUT data before compression;

The image signal processing section uses the original LUT data stored in the line buffer to compensate for the MURA defect of the input image signal data.

15. The display device of claim 14, wherein the decompressor processes raw LUT data using an algorithm complementary to the compressor.

16. A display device, comprising:

a plurality of pixels respectively arranged in the intersection regions of the plurality of gate lines and the plurality of data lines;

a gate driver, driving the plurality of gate lines;

a source driver, driving the plurality of data lines;

External memory, storing compressed lookup table LUT data;

The timing controller controls the gate driver and the source driver in response to the image signal data and the control signal input from the outside, and uses the compressed LUT data stored in the external memory to compensate the MURA included in the input image signal data defect, providing compensated image signal data to the source driver; and

an image capture device for capturing a plurality of output images for each of the plurality of pixels for a plurality of input images for uniformity testing, and performing a calibration operation on the plurality of output images to generate raw look-up table LUT data corresponding to the compensation data and storing the compressed LUT data in the external memory, wherein the calibration operation includes calibrating the focus, tonal range and/or sensitivity of the plurality of output images.

17. The display device of claim 16, wherein the timing controller comprises:

Memory controller to read compressed LUT data from external memory;

The image signal processing unit compensates for the MURA defect of the input image signal data by using the original LUT data stored in the line buffer.

18. The display device of claim 16, wherein the image capture device comprises:

a control unit for applying a plurality of input images for uniformity testing to the plurality of pixels;

a camera that captures a plurality of output images for each of the plurality of pixels;

Compressor, which compresses raw LUT data;

The interface unit transfers the compressed LUT data to the external memory.