CN106525231A - A Multi-photon Coincidence Counter Based on Programmable Logic Device - Google Patents

Abstract

The invention discloses a multi-photon coincidence counter based on a programmable logic device. Based on the large capacity of DDR, it can support counting multiple coincidence types at the same time, and adopts a shunt mechanism to solve the problem of insufficient reading and writing speed of DDR, and improves the coincidence rate. The event rate of the system; and, through the introduction of pulse shaping and synchronous clocks, the occurrence of accidental coincidence can be double suppressed; at the same time, the pulse delay can be dynamically adjusted. Due to the use of FPGA IO resources, the adjustment accuracy is as high as tens of picoseconds, linear good degree. The dynamic adjustment solves the problem that the delay of the input signal may not be consistent every time; moreover, the introduction of the scanning mechanism makes it possible to extrapolate the correctness of the matching result when the single-channel count distribution is known. In addition, the PC can know the working status of the system according to the status word, and then adjust the system parameters through the control word, so as to automate the workflow and increase the robustness of the system.

Description

A Multi-photon Coincidence Counter Based on Programmable Logic Device

technical field

The invention relates to the field of photon counting, in particular to a multi-photon coincidence counter based on a programmable logic device.

Background technique

Multiphoton entanglement is a peculiar quantum phenomenon, which is an indispensable resource in the study of quantum nonlocality, quantum error correction and quantum simulation. The greater the number of photons, the greater the degree of freedom of a single photon, and the stronger the ability of the multi-photon system to process information. In the latest experimental advance, the entanglement of eight photons has been achieved.

In multi-photon entanglement experiments, converting the quantum properties of entanglement into quantities that can be observed in our empirical world requires counting and counting the number of photons. Since entanglement is a many-body process, counting is coincidence counting. The function of the coincidence counter is to judge and count the coincidence between two or more signals.

In 2005, Gaertner et al. proposed an address mapping scheme. As shown in Figure 1, the system consists of a detection unit, a first-in-first-out buffer (FIFO), a microcontroller and on-chip random access memory (RAM). The working principle of the coincidence detection unit is to take the signal after the logical OR of the input signal as the sampling trigger, and the sampled pattern is buffered into the FIFO as the address of the counter.

In 2015, BYUNG KWON PARK and others also implemented an eight-body coincidence counter on FPGA with an AND gate. As shown in Figure 2, the system is integrated on the FPGA, which includes a delay module, a pulse shaping module, a signal generator, a counter and a processor, and the FPGA communicates with the PC through a serial port to USB. The principle of the coincidence signal generator is to determine the coincidence configuration by gating the multi-input AND gate through a multiplexer, and each multi-input AND gate corresponds to a coincidence type.

In optical quantum communication and optical quantum computing, it is usually required to measure multi-photon coincidence events. The number of eight-photon experimental channels has reached 16, and the types of coincidences are as many as 2 ¹⁶ -1. Some meaningless coincidences are eliminated, and the types of coincidences are at least geometrically growing. , At the same time, the brightness of the light source has also reached the level of a single-channel count rate of megahertz and a system event rate of ten megahertz. With the rapid development of experimental technology, the number of channels and the brightness of light sources will continue to increase.

However, Gaertner's scheme realizes arbitrary coincidence of eight channels, and cannot be simply extended to dozens of channels, because the type of coincidence increases exponentially with the number of channels, and the event rate will also increase accordingly. At this time, the capacity of the memory And speed will be the bottleneck. The level of integration and flexibility of discrete devices cannot match that of FPGAs. More importantly, the event rate of the system is 0.8MHz, the dead time is 14ns, and the data cannot be read out in real time, so it cannot meet the needs of today's experiments.

At the same time, although the minimum coincidence window of PARK's scheme is 0.47ns and the maximum input frequency is 163MHz, it can only count several coincidence situations selected in advance because of the use of AND gates. When the number of channels increases to dozens, the connection of AND gates will become very complicated.

Contents of the invention

The purpose of the present invention is to provide a multi-photon coincidence counter based on programmable logic devices, by realizing dozens of channels on the FPGA, tens of megahertz case rate, many types, coincidence below 1ppm by chance, real-time reading counting, An automated and scalable solution for multiphoton coincidence counters that can also be used in particle physics experiments.

The purpose of the present invention is achieved through the following technical solutions:

A multi-photon coincidence counter based on programmable logic devices, including: FPGA chip, DDR and PC; wherein:

The FPGA chip is used to sequentially perform delay adjustment, integer operation, sampling, and logical judgment on the received N electrical pulses and store them in the corresponding FIFO, and then perform a coincidence counting operation by a counter connected to the corresponding FIFO ; The trigger condition of the above sampling is the clock signal output by the internal clock management module of the FPGA chip;

The DDR is controlled by the MCB in the FPGA chip, and is used to store the coincidence count of the corresponding counter;

The PC is used to read out the coincidence count between the DDR and the Block RAM inside the FPGA chip and perform post-processing.

Further, the FPGA chip includes: a delay unit, a pulse shaping unit, a sampling register, a logic judgment module, a clock management module, a Block RAM FIFO and a first counter, a DDR FIFO and a second counter, a BlockRAM, a WISHBONE bus and MCB; where:

The delay unit is used to delay and adjust the received N electrical pulses, so that the N electrical pulses are completely aligned;

The pulse shaping unit is used to shape the aligned N electrical pulses into narrow pulses;

The clock management module is configured to output a corresponding clock signal as a trigger condition for sampling after receiving the synchronous clock provided by the laser;

The sampling register is used to store sampling results;

The logical judging module has a shunt function, and is used to sequentially make logical judgments on the sampling results according to a predetermined judgment method, and send corresponding matching address mappings to Block RAM FIFO or DDR FIFO according to the judgment results;

The first counter is connected with the Block RAM FIFO, and the second counter is connected with the DDR FIFO, and both counters are used for coincident counting; the counting result of the first counter is stored in the Block RAM, and the counting result of the second counter is Store in DDR through MCB;

The WISHBONE bus is connected to the PC through the USB interface, and is used for reading and writing the data in the Block RAM and DDR, and writing the control word and reading the status word to the delay unit and the clock management module.

Further, the delay adjustment and sampling adopt a scanning mechanism, and the steps are as follows:

The first step is to adjust the phase of the clock management module to the minimum;

In the second step, every time the clock management module increases a unit phase, it counts all channels for a certain period of time. When the phase reaches the maximum, because the count distribution reflects the waveform of the pulse, it can be known whether all the pulses are within the scanning range. If not, it means that the delay exceeds the dynamic adjustment range, after manual addition and subtraction of the line length, restart from the first step until all pulses are within the scanning range;

The third step is to adjust the delay unit to align all the pulse centers to the pulse center with the largest delay, which is defined as the pulse center;

The fourth step is to adjust the clock management module to align the clock sampling edge with the pulse center.

Further, the coincidence logic judging module sends the coincident type addresses with a high count rate to the Block RAM FIFO according to a predetermined judgment method, and sends the remaining coincident type addresses to the DDR FIFO.

Further, both Block RAM and MCB contain dual ports, one of which is used by the counter, and the other port is accessed by the PC through the WISHBONE bus; the two ports of Block RAM cannot write to the same address at the same time, and the two ports of MCB share Bandwidth, that is, the sum of the data rates of the two ports does not exceed the bandwidth of DDR.

Further, the delay unit, the clock management module, and the Block RAM FIFO and DDR FIFO are all equipped with a status word, and the PC obtains the current system working status through the status word; it includes: when the synchronous clock is abnormal, the Block RAM FIFO or the DDR FIFO is full , the PC will prompt an error message; after that, the PC tries to automatically restart the data collection, and the data collection process ends, and the data is automatically saved to the PC;

The PC also controls the working mode of the delay unit and the clock management module by writing the control word to the delay unit and the clock management module; it includes: writing the control word to the delay unit to control the delay adjustment process of the electric pulse; The clock management module writes the control word to adjust the dynamic phase shifting process.

Further, the method further includes: changing the coincidence address mapping scheme of the coincidence logic judging module in a predetermined manner.

It can be seen from the above-mentioned technical solutions provided by the present invention that 1) the large capacity of the DDR enables counting of more coincidence types at the same time. 2) The shunt mechanism solves the problem of slow reading and writing speed of DDR, and improves the event rate of the system. 3) The introduction of pulse shaping and synchronous clock can double suppress the occurrence of accidental coincidence. 4) The pulse delay can be adjusted dynamically. Due to the use of FPGA IO resources, the adjustment accuracy is as high as tens of picoseconds, and the linearity is good. Dynamic adjustment solves the problem that the delay of the input signal may not be guaranteed to be consistent every time. 5) The synchronous clock can be dynamically phase-shifted, and the scanning mechanism is introduced, so that the correctness of the coincidence result can be extrapolated when the single-channel count distribution is known, which is better than the prior art by testing whether the coincidence result of the known coincidence signal is Program as expected. 6) When counting and counting, the matching count can be read out, as long as the read and write rate is within the DDR bandwidth, the count will not be lost. 7) The PC can know the working status of the system according to the status word, and then adjust the system parameters through the control word, so as to automate the workflow and increase the robustness of the system. 8) The coincidence logic can be reconfigured, so it can be applied to different coincidence experiments within the allowable range of system speed and capacity. 9) High structural portability.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative work.

1 is a schematic diagram of an address mapping scheme provided by the background technology of the present invention; wherein, (a) is a structural block diagram; (b) is a detailed structural diagram of a detection unit;

Fig. 2 realizes the synoptic diagram of eight-body coinciding counter on FPGA with AND gate that Fig. 2 provides for background technology of the present invention; Wherein, (a) is the block diagram of overall scheme structure; (b) is coincident signal generator structural diagram;

Fig. 3 is a kind of multi-photon coincidence counter based on programmable logic device that the embodiment of the present invention provides; Wherein, (a) is the schematic diagram of overall scheme; (b) is FPGA logic structure diagram;

Fig. 4 is the timing diagram of the pulse delay, integer type, and sampling process provided by the embodiment of the present invention; wherein, (a) to (d) are sequentially: the timing diagram of the initial signal, the timing diagram after the delay, and the timing diagram after the integer type timing diagram, timing diagram based on clock sampling

FIG. 5 is a flowchart of a scanning method provided by an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The embodiment of the present invention provides a multi-photon coincidence counter based on a programmable logic device; the multi-photon coincidence counter mainly includes an FPGA chip for judging the type of coincidence and counting, and a synchronous clock provided by the laser for storing a large amount of coincidence data Double Data Rate Synchronous Dynamic RAM (DDR) and a personal computer (PC) that dynamically adjusts matching parameters and reads matching counts.

FPGA chips contain a large number of programmable logic resources, but only when users organically interconnect these logic resources into a whole can they complete specific tasks. The FPGA logic of the present invention includes a delay unit, a pulse shaping unit, a sampling register, a logical judgment module, a clock management module, a Block RAM FIFO and a first counter, a DDR FIFO and a second counter, a Block RAM, a WISHBONE bus (WISHBONE Bus ) and MCB (Memory Controller Block).

DDR has the advantages of large capacity and high speed, and is suitable as a memory for data. When the number of channels is n, there are a total of 2 ⁿ -1 matching types, which grows exponentially. If the number of channels is 20 and the data width is 32bit, the required storage capacity is 32Mbit, so SRAM with limited capacity is not suitable.

In the embodiment of the present invention, a shunt mechanism is adopted to solve the problem of insufficient reading and writing speed of DDR, and the event rate conforming to the system is improved. That is, the logical judgment module performs logical judgment on the sampling results in turn according to the predetermined judgment method, and sends the corresponding data to the Block RAM FIFO or DDR FIFO according to the judgment result; then reads the address of the FIFO cache by the corresponding counter, Count the data of the corresponding address of RAM (Block RAM FIFO or DDR FIFO).

In addition, count loss can also be avoided by employing the above-mentioned shunt mechanism. Assuming that the bit width of the data is 64bit, the counting operation requires the data to be read plus one to write back, and the case rate is 30MHz, then the data volume is 3840Mbps, which may be lost due to insufficient processing by DDR alone. Based on the above shunting mechanism, the DDR read data is added and written back only for a part of the match, and the other part of the match (it can be the match data with a high count rate) is shunted to the Block RAM in the FPGA chip for processing, because its speed is faster than that of DDR. Fast, ensuring data integrity. However, the storage space of the Block RAM is limited, so the splitting scheme should be properly selected according to the experiment.

There are dark noise and environmental noise in the detector signal, and the coincidence caused by the noise is called accidental coincidence. Accidental matching can lead to wrong results, which we don't want to happen. In order to reduce the probability of accidental coincidence, the present invention adopts double measures, firstly, to compress the coincidence window, and secondly, to use a synchronous clock. Only pulses within the matching window can be matched. In the present invention, the parameter that affects the matching window is the pulse width. Therefore, the pulse is compressed into a narrow pulse by the shaping unit before the matching. This compression does not affect the time when the rising edge occurs. Using a synchronous clock as the sampling trigger, rather than the first occurring pulse, eliminates the possibility of false triggering.

During the multi-photon experiment, the experimenter needs to obtain some matching counts in real time to adjust the experimental parameters, and if the count is found to be abnormal during the long-term data collection, the experiment can be stopped immediately, saving time. In order to realize the function of reading data while counting is in progress, Block RAM and MCB adopt a dual-port design, one port is used for the counter, and the other port is used for USB access. The two ports of Block RAM cannot write to the same address at the same time. The two ports of MCB share the bandwidth. As long as the USB read data rate is not too high, that is, the combined data rate of the two ports does not exceed the bandwidth of DDR, it will not cause loss of numbers.

If the data collection process requires the experimenter to manually operate step by step, it will cause a waste of human resources. The invention can collect data automatically, without the need for the experimenter to wait hard. The PC obtains the current system working status through the status word, and then adjusts the system parameters through the control word. The delay unit, the clock management module, and the two FIFOs are all provided with status words. When the synchronous clock is abnormal and the Block RAM FIFO or DDR FIFO is full, the PC will prompt an error message and try to automatically restart the data collection. After the data collection process is over, the data is automatically saved to the PC. In addition, the PC also controls the working mode of the delay unit and the clock management module by writing the control word to the delay unit and the clock management module; which includes: writing the control word to the delay unit to control the delay adjustment process of the electric pulse ; Write the status word to the clock management module to adjust the dynamic phase shift process.

Different experiments have different matching requirements, such as the number of channels, matching types, and even the same experiment will change. If the same compliance system could be applied to these different scenarios, it would save considerable time and money. Due to the reconfigurable feature of FPGA, for different needs, as long as the number of channels and the amount of data do not exceed the limit of the system, the change is logical, and the reuse of the same set of hardware is realized.

For ease of understanding, the above solutions of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 3 is a multi-photon coincidence counter based on a programmable logic device provided by an embodiment of the present invention; wherein, (a) is a schematic diagram of the overall scheme; (b) a logic structure diagram of FPGA.

In the schematic diagram of the overall solution shown in FIG. 3( a ), the dotted arrows are optical signals, and the other arrows are electrical signals. The laser (laser) is incident into the optical system (Optical System), and the space is separated into n optical paths, which are respectively received by n single photon detectors and converted into n electrical pulses. The electrical pulse is first converted into a 3.3V TTL signal by a discriminator, and then input to the FPGA chip (FPGA Chip) through a common IO pin. The laser inputs a 76MHz clock synchronized with the laser pulse to the FPGA chip through a dedicated clock pin. The FPGA chip is connected to the DDR and USB chip through PCB wiring, and the PC is connected to the USB chip through a USB cable.

The main functions of the above-mentioned FPGA chip, DDR and PC are as follows: FPGA chip is used to sequentially perform delay adjustment, integer operation, sampling, and logical judgment on the received N electrical pulses and encode them into RAM (Block RAM or DDR) The address of the address is stored in the corresponding FIFO, and then the counter connected to the corresponding FIFO performs the coincidence counting operation; DDR is controlled by the MCB in the FPGA chip, which is used to store the coincidence count of the corresponding counter; PC, used to read out DDR and FPGA Count the coincidences in the Block RAM inside the chip and perform post-processing and control the working process of the coincidence counter.

In the embodiment of the present invention, the specific numerical values involved are all examples and do not constitute a limitation; for example, in the above embodiment, it can be applied to the eight-photon entanglement experiment, and the degree of freedom of each photon is 2, so there are a total of 2 ² ×8=32 channels, that is, n=32 above.

Exemplarily, the FPGA chip can be selected SPARTAN-6XC6SLX16-2CSG324C of XILINX company, the DDR can be selected Micron Technology MT46H64M16LFCK-5, and the USB can be selected CY7C68013A of CYPRESS company. The parameters of each device can be flexibly adjusted according to the experimental plan, for example, choose a DDR with a capacity greater than 1Gbit, and a serial communication with a bandwidth of more than 10MBps such as a Gigabit network.

In the embodiment of the present invention, the internal structure of the FPGA chip is shown in FIG. data signal.

The FPGA chip mainly includes: a delay unit (IODELAY2), a pulse shaping unit (Pulse Shaping), a sampling register (Register), a logical judgment module (Coincidence Logic), a clock management module (DCM), a Block RAM FIFO and a first A counter, DDR FIFO and second counter, Block RAM, WISHBONE bus and MCB; where:

The delay unit is used to delay and adjust the received N electrical pulses, so that the N electrical pulses are completely aligned;

The pulse shaping unit is used to shape the aligned N electrical pulses into narrow pulses;

The clock management module is configured to output a corresponding clock signal as a trigger condition for sampling after receiving the synchronous clock provided by the laser;

The sampling register is used to store sampling results;

The logical judging module is used to sequentially judge the sampling results according to a predetermined judgment method, and send the corresponding corresponding mapping address to the Block RAM FIFO or DDR FIFO according to the judgment result;

The first counter is connected with the Block RAM FIFO, and the second counter is connected with the DDR FIFO, and both counters are used for coincident counting; the counting result of the first counter is stored in the Block RAM, and the counting result of the second counter is Store in DDR through MCB;

The WISHBONE bus is connected to the PC through the USB interface, and is used for reading and writing the data in the Block RAM and DDR, and writing the control word and reading the status word to the delay unit and the clock management module.

Exemplarily, as mentioned above, assuming that n=32, the 32 electrical pulses are first adjusted for delay by IODELAY2 in the IO resource, and the aligned pulses are converted into narrow pulses by the integer module and then sampled by the clock output by the DCM , the timing diagram of the pulse is shown in Figure 4, and the input clock of the DCM is the synchronous clock provided by the laser. The sampled code pattern is divided into two parts according to the preset judgment method by the logical judgment module, one part is buffered to the FIFO of DDR, and the other part is buffered to the BlockRAM FIFO. After the counter of the Block RAM obtains the data in the Block RAM FIFO, it reads the data from the corresponding address of the Block RAM and adds one and writes it back to the Block RAM. After the DDR counter obtains the data in the DDR FIFO, it reads the data from the corresponding address of the DDR through the MCB and adds one and writes it back to the DDR. The WISHBONE bus can write control words and read status words to IODELAY2 and DCM, and can also directly read and write arbitrary data in Block RAM and read and write arbitrary data in DDR through MCB. The USB host device in WISHBONE is connected to the USB chip through common IO pins.

For example, the status word of IODELAY2 is busy, indicating whether the delay unit is currently in the shifting state. If busy is set high, IODELAY2 cannot accept new shifting instructions. The status words of the clock management module are lock, psdone, and limit, indicating whether the clock is locked, whether the phase shift is completed, and whether the phase is out of range. The status word of the two FIFOs is full, indicating whether the FIFO is full or not. WISHBONE bus is connected with two FIFOs through status word and control word, which is not shown in Fig. 3(b).

As shown in Figure 4, (a) to (d) are sequentially: the timing diagram of the initial signal, the timing diagram after delay, the timing diagram after integer, and the timing diagram based on clock sampling. Fig. 4 only shows CH1~CH3, 3 pulses.

In the embodiment of the present invention, a scanning mechanism is required to complete the alignment and sampling of pulses, as shown in FIG. 5 , the steps are as follows:

The first step is to adjust the phase of the clock management module to the minimum;

In the second step, every time the clock management module increases a unit phase, it counts all channels for a certain period of time. When the phase reaches the maximum, because the count distribution reflects the waveform of the pulse, it can be known whether all the pulses are within the scanning range. If not, it means that the delay exceeds the dynamic adjustment range, after manual addition and subtraction of the line length, restart from the first step until all pulses are within the scanning range;

The third step is to adjust the delay unit to align all the pulse centers to the pulse center with the largest delay, which is defined as the pulse center;

The fourth step is to adjust the clock management module to align the clock sampling edge with the pulse center.

Those skilled in the art can understand that the predetermined judgment method in the logic judgment module can be adjusted according to the actual situation, for example, according to the predetermined judgment method, the address of the matching type with a high count rate is sent to the Block RAM FIFO, and the rest of the matching type addresses are sent to the Block RAM FIFO. to DDR FIFOs.

Exemplarily, in the eight-photon entanglement experiment, since single-photon and two-photon coincidence accounts for more than 90% of the total coincidence cases, reaching 20MHz, therefore, the coincidence logic judgment module can combine single-photon and two-photon data according to a predetermined judgment method Send to the block RAM with fast processing speed, and the DDR is enough to handle the coincidence of more than two photons.

After the distribution scheme is determined, the address mapping scheme can be discussed. The maximum counting rate in the corresponding category is up to megahertz, and an experiment may be carried out for dozens of hours. The bit width of the counter is large enough to ensure that it will not overflow, so 64bit bit width is selected. There are 2 ³² -1 types of coincidences in 32 channels, but there are many invalid coincidences among them. In the channel corresponding to a photon, there can only be at most one coincidence with a pulse at the same time as a valid coincidence. Therefore, there are 6 possibilities for a photon. 3bit encoding, 8 photons total 24bit. 24bit address width, 64bit data width, a total of 1Gbit space, such a large storage space requirements, DDR is the ideal choice.

Block RAM does not have a 1Gbit storage space, so the single-photon and two-photon address mapping scheme requires the address width to be as small as possible. The address is divided into two parts, corresponding to two photons. One photon only needs to know which photon and which channel two One piece of information, photon information occupies 3 bits, channel information occupies 2 bits, one photon has 5 bits, and two photons have a total of 10 bits. If a single photon coincides, the two photons have the same information.

In the embodiment of the present invention, since the FPGA chip adopts the logic structure shown in FIG. 3( b ), the corresponding address mapping scheme of the Block RAM can be changed in a predetermined manner. Those skilled in the art can understand that the predetermined manner may be a conventional manner in the field.

The above scheme of the embodiment of the present invention mainly obtains the following beneficial effects:

1) The large capacity of DDR makes it possible to count more coincidence types at the same time.

2) The shunt mechanism solves the problem of insufficient reading and writing speed of DDR, and improves the event rate in line with the system.

3) The introduction of pulse shaping and synchronous clock can double suppress the occurrence of accidental coincidence.

4) The pulse delay can be adjusted dynamically. Due to the use of FPGA IO resources, the adjustment accuracy is as high as tens of picoseconds, and the linearity is good. Dynamic adjustment solves the problem that the delay of the input signal may not be guaranteed to be consistent every time.

5) The synchronous clock can be dynamically phase-shifted, and the scanning mechanism is introduced, so that the correctness of the coincidence result can be extrapolated when the single-channel count distribution is known, which is better than the prior art by testing whether the coincidence result of the known coincidence signal is Program as expected.

6) When counting and counting, the matching count can be read out, as long as the read and write rate is within the DDR bandwidth, the count will not be lost.

7) The PC can know the working status of the system according to the status word, and then adjust the system parameters through the control word, so as to automate the workflow and increase the robustness of the system.

8) The coincidence logic can be reconfigured, so it can be applied to different coincidence experiments within the allowable range of system speed and capacity.

9) The structure has high portability, and series FPGAs such as SPARTAN, VIRTEX, and KINTEX of XILINX Company all support the structure of the present invention.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technical field can easily conceive of changes or changes within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (7)

1. A multi-photon coincidence counter based on programmable logic device, is characterized in that, comprises: FPGA chip, DDR and PC; Wherein: The FPGA chip is used to sequentially perform delay adjustment, integer operation, sampling, and logical judgment on the received N electrical pulses and store them in the corresponding FIFO, and then perform a coincidence counting operation by a counter connected to the corresponding FIFO ; The trigger condition of the above sampling is the clock signal output by the internal clock management module of the FPGA chip; The DDR is controlled by the MCB in the FPGA chip, and is used to store the coincidence count of the corresponding counter; The PC is used to read out the coincidence count between the DDR and the Block RAM inside the FPGA chip and perform post-processing. 2. a kind of multi-photon coinciding counter based on programmable logic device according to claim 1, is characterized in that, described FPGA chip comprises: delay unit, pulse shaping unit, sampling register, coinciding logic judgment module, clock Management module, Block RAM FIFO and first counter, DDR FIFO and second counter, Block RAM, WISHBONE bus and MCB; where: The delay unit is used to delay and adjust the received N electrical pulses, so that the N electrical pulses are completely aligned; The pulse shaping unit is used to shape the aligned N electrical pulses into narrow pulses; The clock management module is configured to output a corresponding clock signal as a trigger condition for sampling after receiving the synchronous clock provided by the laser; The sampling register is used to store sampling results; The logical judging module has a shunt function, and is used to sequentially make logical judgments on the sampling results according to a predetermined judgment method, and send corresponding matching address mappings to Block RAM FIFO or DDRFIFO according to the judgment results; The first counter is connected with the Block RAM FIFO, and the second counter is connected with the DDR FIFO, and both counters are used for coincident counting; the counting result of the first counter is stored in the Block RAM, and the counting result of the second counter is Store in DDR through MCB; The WISHBONE bus is connected to the PC through the USB interface, and is used for reading and writing the data in the Block RAM and DDR, and writing the control word and reading the status word to the delay unit and the clock management module. 3. a kind of multi-photon coincidence counter based on programmable logic device according to claim 2, is characterized in that, delay adjustment and sampling adopt scanning mechanism, and its steps are as follows: The first step is to adjust the phase of the clock management module to the minimum; In the second step, every time the clock management module increases a unit phase, it counts all channels for a certain period of time. When the phase reaches the maximum, because the count distribution reflects the waveform of the pulse, it can be known whether all the pulses are within the scanning range. If not, it means that the delay exceeds the dynamic adjustment range, after manual addition and subtraction of the line length, restart from the first step until all pulses are within the scanning range; The third step is to adjust the delay unit to align all the pulse centers to the pulse center with the largest delay, which is defined as the pulse center; The fourth step is to adjust the clock management module to align the clock sampling edge with the pulse center. 4. A kind of multi-photon coinciding counter based on programmable logic device according to claim 2, it is characterized in that, coinciding logic judging module sends the tall coinciding type address of counting rate to BlockRAMFIFO according to predetermined judging mode, and the remaining coinciding The class address is sent to the DDR FIFO. 5. a kind of multi-photon coincidence counter based on programmable logic device according to claim 2, is characterized in that, Both Block RAM and MCB contain dual ports, one of which is used by the counter, and the other port is accessed by the PC through the WISHBONE bus; the two ports of Block RAM cannot write to the same address at the same time, and the two ports of MCB share the bandwidth, that is The sum of the data rates of the two ports does not exceed the bandwidth of DDR. 6. a kind of multi-photon coincidence counter based on programmable logic device according to claim 2, is characterized in that, The delay unit, the clock management module, and the Block RAM FIFO and DDR FIFO all have a status word, and the PC obtains the current system working status through the status word; it includes: when the synchronous clock is abnormal, the Block RAM FIFO or the DDR FIFO is full, the PC will An error message will be prompted; after that, the PC tries to automatically restart the data collection, and the data collection process is completed, and the data is automatically saved to the PC; The PC also controls the working mode of the delay unit and the clock management module by writing the control word to the delay unit and the clock management module; it includes: writing the control word to the delay unit to control the delay adjustment process of the electric pulse; The clock management module writes the control word to adjust the dynamic phase shifting process. 7. A multi-photon coincidence counter based on a programmable logic device according to claim 2, further comprising: changing the coincidence address mapping scheme of the coincidence logic judging module in a predetermined manner.