CN106502630B

CN106502630B - A kind of system based on the soft core acquisition ASCII form data of FPGA

Info

Publication number: CN106502630B
Application number: CN201610877594.3A
Authority: CN
Inventors: 姚廷伟
Original assignee: Hebei Hanguang Heavy Industry Ltd
Current assignee: Hebei Hanguang Heavy Industry Ltd
Priority date: 2016-10-09
Filing date: 2016-10-09
Publication date: 2018-11-20
Anticipated expiration: 2036-10-09
Also published as: CN106502630A

Abstract

The invention discloses a kind of systems based on the soft core acquisition ASCII form data of FPGA, which includes one piece of digital signal processing chip and fpga chip；It include serial data receiving module, first in, first out buffer area FIFO, soft core, data conversion module and the first dual port RAM in fpga chip；Serial data receiving module receives externally input ASCII form data, and is sent in FIFO；The second dual port RAM is created in soft core, the second dual port RAM data bit is 32；Soft core reads data parallel parsing in FIFO, extracts information needed, sends the information needed in the second dual port RAM；Information needed is read out carry out data conversion by data conversion module from the second dual port RAM, and transformation result is stored in the first dual port RAM；First dual port RAM is connected with digital signal processing chip；Digital signal processing chip reads above-mentioned transformation result from the first dual port RAM, realizes reception of the digital signal processing chip to ASCII form data.

Description

A kind of system based on the soft core acquisition ASCII form data of FPGA

Technical field

The invention belongs to electrical engineering technical field, be related to a kind of be based on the soft core acquisition ASCII form data of FPGA System.

Background technique

Since FPGA is good at compared in terms of timing control in combinational logic, it is not so good as to use C language in terms of parsing ASCII protocol Speech parsing is convenient.Therefore, it is desirable to solve the problems, such as this by the soft core (microblaze) of FPGA, microblaze is as FPGA's A kind of embeded processor can be adopted and show a C language program and avoid the weakness of FPGA in this respect.

However ASCII is 8 data modes, the 32 data bit forms and digital signal that can be handled with the soft core of FPGA The 16 of processor are that data bit form is different, therefore has certain difficulty using fpga chip processing ascii data, at present There has been no effective solution methods.

Summary of the invention

In view of this, can be realized the present invention provides a kind of system based on the soft core acquisition ASCII form data of FPGA Fast resolving of the FPGA to ASCII form data.

In order to achieve the above object, the technical scheme is that：One kind acquiring ASCII form data based on the soft core of FPGA System, the system include one piece of digital signal processing chip and fpga chip.

It include serial data receiving module, first in, first out buffer area FIFO, soft core microblaze, data in fpga chip Conversion module and the first dual port RAM.

Serial data receiving module is the software module created in FPGA, for receiving externally input ASCII form Data, and the ASCII form data are sent in FIFO.

FIFO is created in the IP kernel of FPGA, and data fifo type is 8, and FIFO output interface includes 8 output datas Line, 1 place reading are according to line and 1 non vacuum data line.

Microblaze has 10 GPIO mouthfuls and connects one to one respectively with 10 data lines of FIFO；? The second dual port RAM is created in microblaze, the second dual port RAM data bit is 32；The non-empty of microblaze reading FIFO Current potential in data line, when there is data in FIFO, FIFO non vacuum data line becomes low potential, which is obtained by microblaze After taking, microblzae carries out set by the read data line to FIFO, and after the read data line set of FIFO, microblaze is logical 8 output data lines for crossing FIFO read data in FIFO, and microblaze parses the data of reading, extract wherein institute Information is needed, sends the information needed in the second dual port RAM in microblaze.

Data conversion module reads out information needed from the second dual port RAM, and will be needed in the second dual port RAM Information carries out data bit transition and 32 data is converted to 16, and transformation result is stored in the first dual port RAM.

First dual port RAM creates in the IP kernel of FPGA, and the data bit of the first dual port RAM is 16；First dual port RAM with Digital signal processing chip is connected；Digital signal processing chip reads above-mentioned transformation result from the first dual port RAM, realizes number Reception of the word signal processing chip to ASCII form data.

Beneficial effect：

The core data processing board of this system is made of one piece of digital signal processing chip (OMAPL138) with FPGA, system Operation needs two chips to cooperate.Using FPGA as the interface interacted with exogenous data, cooperate OMAPL138 work.When When external serial communication data protocol is ASCII mode, FPGA is able to carry out fast resolving.

Detailed description of the invention

Fig. 1 is system block diagram.

Specific embodiment

The present invention will now be described in detail with reference to the accompanying drawings and examples.

The system block diagram of the system is as shown in Figure 1, including includes string in one piece of digital signal processing chip and FPGA, FPGA Mouth data reception module (realizes) that FIFO (can be created, data fifo type is 8, data fifo in IP kernel using code Output includes 8 output data lines, and 1 place reading is according to line, 1 non vacuum data line), embeded processor (microblaze, insertion There are formula processor 10 GPIO mouthfuls 10 data lines respectively at FIFO to connect；It needs to add twoport in embeded processor RAM controller and dual port RAM, the dual port RAM data are defaulted as 32), data conversion module (employs codes to realize 32 Position data are converted to 16), dual port RAM (can create, dual port RAM data type is 16) in IP kernel.

The serial data of ASCII form enters serial data receiving module, and serial data receiving module will receive Data are sent in FIFO, and when there is data in FIFO, FIFO non-empty flag data line (empty) becomes low potential, the low electricity After position is obtained by microblaze, microblzae passes through the read data line of control FIFO, and microblaze passes through 8 of FIFO Output data line reads data in FIFO, and microblaze parses the data of reading, wherein information needed is extracted, by this Information needed is sent in the dual port RAM of microblazede, is read out the information from dual port RAM by data conversion module Come, and carry out providing conversion, transformation result is stored in 16 dual port RAMs, 16 dual port RAMs and Digital Signal Processing Chip is connected.Digital signal processing chip can read above-mentioned transformation result from the dual port RAM.

Embodiment 1：

By taking deep water compass system (its core board is made of digital signal processor OMAPL138 and FPGA) as an example, deep water sieve Through needing to receive GPS information in water general work.GPS provides the information such as position and speed, sends the data to depth by serial ports Water compass system, specific serial port protocol are as follows：

$GPRMC,010006.00,A,3650.1230000,N,11250.0000345,E,12.000,40.0,16,0.0, Wherein $ GPRMC is data head by W, N*3F, and 010006.00 is the time, and A is that data are effective, and 3650.1230000 be latitude, 11250.0000345 being longitude.

Deep water compass system serial ports receive pin (RX) be connected with the transmission pin (TX) of GPS, when GPS pass through serial ports to When outer transmission data, the FPGA of deep water compass system detects reception leg signal, and FPGA passes through serial ports receiving module for data Character type data storage is converted into FIFO, indicates that data line (empty) is dragged down when there are data in FIFO.Due to empty Pin is connect with microblaze, and microblaze is believed after detecting the low level of empty by the reading that control is connect with FIFO Number RD sends read signal, passes through data line and obtains data in FIFO.A packet is obtained by operating above, in microblaze The completion data of GPS.In microblzae, we extract location information therein (above such as by writing C programmer Latitude 3650.1230000, longitude 11250.0000345), location information is stored in the dual port RAM of itself, data turn Change the mold block will microblaze RAM data convert after storage to digital signal processor (omapl138) to the twoport of connection In RAM, reads and use for digital signal processor.

To sum up, the above is merely preferred embodiments of the present invention, it is not intended to limit the scope of the present invention.It is all Within the spirit and principles in the present invention, any modification, equivalent replacement, improvement and so on should be included in protection of the invention Within the scope of.

Claims

1. a kind of system based on the soft core acquisition ASCII form data of FPGA, which is characterized in that the system is believed including a block number word Number processing chip and fpga chip；

It include serial data receiving module, first in, first out buffer area FIFO, soft core microblaze, data in the fpga chip Conversion module and the first dual port RAM；

The serial data receiving module is the software module created in FPGA, for receiving externally input ASCII form Data, and the ASCII form data are sent in FIFO；

The FIFO is created in the IP kernel of FPGA, and data fifo type is 8, and FIFO output interface includes 8 output datas Line, 1 place reading are according to line and 1 non vacuum data line；

The microblaze has 10 GPIO mouthfuls and connects one to one respectively with 10 data lines of FIFO；? The second dual port RAM is created in microblaze, the data bit of second dual port RAM is 32；Microblaze reads FIFO Non vacuum data line in current potential, when there is data in FIFO, FIFO non vacuum data line becomes low potential, the low potential by After microblaze is obtained, microblaze carries out set by the read data line to FIFO, after the read data line set of FIFO, Microblaze reads data in FIFO by 8 output data lines of FIFO, and microblaze solves the data of reading Analysis extracts wherein information needed, sends the information needed in the second dual port RAM in microblaze；

The data conversion module reads out information needed from the second dual port RAM, and will be described in the second dual port RAM Information needed carries out data bit transition and 32 data is converted to 16, and transformation result is stored in the first dual port RAM；

First dual port RAM creates in the IP kernel of FPGA, and the data bit of the first dual port RAM is 16；First dual port RAM with Digital signal processing chip is connected；The digital signal processing chip reads above-mentioned transformation result from the first dual port RAM, real Existing reception of the digital signal processing chip to ASCII form data.