CN106486485A - Memory element and manufacturing method thereof - Google Patents

Abstract

The invention discloses a memory element and a manufacturing method thereof. The memory element comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, a source region and a drain region. The tunneling dielectric layer is located on the substrate. The floating gate includes a second portion having a first portion on and over the tunneling dielectric layer. The first part contains a first dopant and a second dopant; the second portion contains a first dopant. The first fraction has a particle size smaller than that of the second fraction, and the average particle size of the first fraction is betweenToThe inter-gate dielectric layer is positioned on the floating gate. The control gate is located on the inter-gate dielectric layer. The source region and the drain region are located in the substrate at two sides of the floating gate.

Description

Memory element and its manufacturing method

technical field

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory element and its manufacturing method.

Background technique

Electronic products such as digital cameras, cell phone cameras, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Because flash memory (Flash Memory) has the characteristics of data non-volatility, power saving, small size and no mechanical structure, it is most suitable as a storage medium for such portable and battery-powered electronic products.

However, under the continuous pursuit of high integration density and size reduction of integrated circuits, the area occupied by each memory cell of the flash memory must be reduced, and the line width of the device must also be reduced accordingly. In this way, the gate coupling ratio between the floating gate and the control gate will also decrease accordingly. The reduction of the gate coupling ratio will not only widen the distribution of the programming threshold voltage (threshold voltage; Vt), but also reduce the memory window (memory window), and the reliability of the memory element (such as data retention and durability) will also follow. reduce.

Contents of the invention

The present invention provides a memory element and method of manufacturing the same, wherein the memory element can be formed with improved reliability of data retention and endurance.

The invention provides a storage element, which includes a substrate, a control gate, a floating gate, a tunnel dielectric layer, an inter-gate dielectric layer, and a source region and a drain region. The tunneling dielectric layer is on the substrate. The floating gate includes a first part on the tunnel dielectric layer and a second part on it, wherein the first part contains the first dopant and the second dopant; the second part contains the first dopant. The particle size of the first part is smaller than the particle size of the second part, and the average particle size of the first part is between to An inter-gate dielectric layer is on the floating gate. The control gate is on the inter-gate dielectric layer. The source region and the drain region are located in the substrate on both sides of the floating gate.

In the memory element according to the embodiment of the present invention, the materials of the first part and the second part include doped polysilicon, and the concentration of the first dopant in the first part is lower than that of the first dopant in the second part. Dopant concentration.

In the memory element according to an embodiment of the present invention, the first dopant includes arsenic, phosphorus or boron; the second dopant includes carbon, nitrogen, oxygen or a combination thereof.

The invention provides a storage element, which includes a substrate, a control gate, a floating gate, a tunnel dielectric layer, an inter-gate dielectric layer, and a source region and a drain region. The tunneling dielectric layer is on the substrate. The floating gate includes a first part on the tunnel dielectric layer and a second part on it, wherein the first part contains the first dopant and the second dopant; the second part contains the first dopant. The conductivity of the first portion is less than the conductivity of the second portion. An inter-gate dielectric layer is on the floating gate. The control gate is on the inter-gate dielectric layer. The source region and the drain region are located in the substrate on both sides of the floating gate.

In the memory element according to the embodiment of the present invention, the materials of the first part and the second part include doped polysilicon, and the concentration of the first dopant in the first part is lower than that of the first dopant in the second part. Dopant concentration.

In the memory element according to an embodiment of the present invention, the first dopant includes arsenic, phosphorus or boron; the second dopant includes carbon, nitrogen, oxygen or a combination thereof.

According to the memory element described in the embodiment of the present invention, wherein the average particle diameter of the first part is between to

The invention provides a manufacturing method of a storage element, which includes forming a tunnel dielectric layer on a substrate. Next, a first deposition process is performed, and a first mixed gas is introduced during the first deposition process to form a first portion on the tunnel dielectric material layer, wherein the first mixed gas includes a silicon source, The first doping gas and the second doping gas. Then, a second deposition process is performed, and a second mixed gas is introduced during the second deposition process to form a second part on the first part, wherein the second mixed gas includes the gas and the the first dopant gas. Afterwards, an inter-gate dielectric layer is formed on the second portion. Furthermore, a control gate is formed on the inter-gate dielectric layer. Thereafter, forming a source region and a drain region in the base of the sidewall of the floating gate, wherein the conductivity types of the first portion and the second portion are determined by the first dopant gas, And the particle size of the first part is controlled by the second dopant gas.

According to the manufacturing method of the memory element described in the embodiment of the present invention, the first dopant gas includes arsine, phosphine or diborane; the second dopant gas includes ethylene, ammonia, ozone, or combination.

According to the method for manufacturing a memory element according to an embodiment of the present invention, the concentration of the first dopant doped by the first doping gas in the first part is lower than that in the second part by the first doping gas. The concentration of the first dopant for gas doping.

Based on the above, in the process of forming the floating gate in the present invention, because the dopant gas containing the dopant that can prevent the diffusion of silicon atoms is first introduced, a layer with a smaller particle size can be deposited on the tunneling dielectric layer. A small doped layer with low conductivity helps the memory device to achieve a narrower threshold voltage distribution curve, thereby improving the reliability of the memory device. Therefore, the memory device of the present invention has high reliability for data storage and endurance.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

1A to 1C are cross-sectional views of a manufacturing process of a memory device according to an embodiment of the present invention.

FIG. 2 is a graph of programmed threshold voltage distributions of memory elements.

【Symbol Description】

100: base

102, 102a: tunneling dielectric material layer

102b: tunneling dielectric layer

103: strip laminated structure

104, 104a: first doped layer

104b: Part I

105: floating gate

106, 106a: second doped layer

106b: Part II

108: inter-gate dielectric material layer

108a: inter-gate dielectric layer

110: conductor material layer

110a: Control grid

112: Gate structure

114: source region and drain region

detailed description

1A to 1C are cross-sectional views of a manufacturing process of a memory device according to an embodiment of the present invention.

First, referring to FIG. 1A , a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator substrate (Semiconductor Over Insulator, SO1). Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed of atoms of group IIIA and group VA, such as gallium arsenide.

Next, a tunneling dielectric material layer 102 is formed on the substrate 100 . The material of the tunneling dielectric material layer 102 is, for example, silicon oxide, silicon oxynitride or a dielectric material with a dielectric constant higher than 4. Referring to FIG. The method for forming the tunneling dielectric material layer 102 includes chemical vapor deposition, in-situ steam generation (ISSG), low-pressure free radical oxidation, or furnace tube oxidation.

Then, a first deposition process is performed to form a first doped layer 104 on the tunneling dielectric material layer 102 . The material of the first doped layer 104 is, for example, doped polysilicon. The first deposition process is, for example, performed by a low-pressure chemical vapor deposition method. The operating pressure is, for example, between 50 Torr and 200 Torr, and the process temperature is, for example, between 450 degrees Celsius and 650 degrees Celsius. The thickness of the first doped layer 104 is, for example, to

In this embodiment, the first mixed gas is introduced during the first deposition process. The first mixed gas includes a silicon source, a first dopant gas and a second dopant gas, and the formed first doped layer 104 contains the first dopant provided by the first dopant gas and the second dopant provided by the second dopant gas. The second dopant provided. The silicon source is, for example, silane (SiH ₄ ), silethane (Si ₂ H ₆ ) or a combination thereof. The first doping gas is, for example, phosphine (PH ₃ ), arsine (AsH ₃ ) or diborane (B ₂ H ₆ ). In this embodiment, the conductivity type of the first doped layer 104 can be determined by the first doping gas. For example, when the N-type first doped layer 104 is to be formed, the first doped gas The impurity gas is PH ₃ or AsH ₃ ; when the P-type first doped layer 104 is to be formed, the first doped gas injected is B ₂ H ₆ . The second dopant gas is, for example, ethylene (C ₂ H ₄ ), ammonia (NH ₃ ), ozone (O ₃ ) or a combination thereof. The first dopant is, for example, phosphorous, arsenic or boron. The second dopant is, for example, carbon, nitrogen, oxygen or a combination thereof. The second dopant (such as carbon, nitrogen, oxygen, or a combination thereof) provided by the second dopant gas will prevent the diffusion of silicon atoms during the first deposition process, thereby reducing the expansion of the grain boundary (grain boundary), so the formed The particle size of the first doped layer 104 will be smaller. That is to say, the particle size of the first doped layer 104 can be controlled by adjusting the flow rate of the second doped gas. The average grain size of the first doped layer 104 is, for example, between to In an exemplary embodiment, the first mixed gas is a mixed gas of SiH4, PH ₃ and C ₂ H ₄ , wherein the SiH ₄ flow range is 100 sccm to 250 sccm; the PH ₃ flow range is 10 sccm to 200 sccm; the C ₂ H ₄ flow range 1 sccm to 10 sccm.

Afterwards, please continue to refer to FIG. 1A , a second deposition process is performed to form a second doped layer 106 on the first doped layer 104 . In an embodiment, the material of the second doped layer 106 may be the same as that of the first doped layer 104 , such as doped polysilicon. The second doped layer 106 may also contain the first dopant. However, the concentration of the first dopant in the second doped layer 106 is greater than the concentration of the first dopant in the first doped layer 104 . The ratio of the concentration of the first dopant in the first doped layer 104 to the concentration of the first dopant in the second doped layer 106 ranges from 1:6 to 1:2. In an exemplary embodiment, the ratio of the concentration of the first dopant in the first doped layer 104 to the concentration of the first dopant in the second doped layer 106 is about 1:3. In one embodiment, there is no second dopant in the second doped layer 106 . In another embodiment, there may also be a second dopant in the second doped layer 106, but the concentration of the second dopant in the second doped layer 106 is smaller than the concentration of the second dopant in the first doped layer 104 . In other embodiments, a progressively doped layer (not shown) may also be formed on the tunneling dielectric material layer 102 to replace the first doped layer 104 and the second doped layer 106 . The concentration of the first dopant in the progressively doped layer decreases from the top of the progressively doped layer toward the base 100, while the concentration of the second dopant in the progressively doped layer decreases from the top of the progressively doped layer toward the base 100. direction increases.

The second deposition process is, for example, performed by low pressure chemical vapor deposition. The second mixed gas is fed during the second deposition process. The second mixed gas includes silicon source and the above-mentioned first dopant gas. The operating pressure of the second deposition process is, for example, between 50 Torr and 200 Torr, and the process temperature is, for example, between 450 degrees Celsius and 650 degrees Celsius. The thickness of the second doped layer 106 is, for example, between to

Since the second doped layer 106 does not contain or only contains very little second dopant that can prevent silicon diffusion, and the concentration of the first dopant in the second doped layer 106 is higher than that in the first doped layer 104 The concentration of the first dopant, therefore, the particle size of the formed second doped layer 106 will be larger than the particle size of the first doped layer 104 . In one embodiment, the average grain size of the first doped layer 104 is between to The average grain size of the second doped layer 106 is, for example, between to In addition, since the particle diameter of the first doped layer 104 is smaller than that of the second doped layer 106, the concentration of the first dopant in the first doped layer 104 is lower than that of the first dopant in the second doped layer 106. concentration, so the conductivity of the first doped layer 104 is smaller than that of the second doped layer 106 .

Next, referring to FIG. 1A and FIG. 1B , the tunneling dielectric material layer 102 , the first doped layer 104 and the second doped layer 106 are patterned by photolithography and etching processes to form a plurality of doped layers on the substrate 100. Strip laminated structure 103 . Each striped stack structure 103 includes a tunneling dielectric material layer 102a, a first doped layer 104a, and a second doped layer 106a from bottom to top. The strip-shaped stacked structure 103 extends along the first direction D1, for example.

Then, an inter-gate dielectric material layer 108 and a conductive material layer 110 are sequentially formed on the substrate 100 . In this embodiment, the inter-gate dielectric material layer 108 is, for example, a composite layer composed of oxide/nitride/oxide (ONO), but the invention is not limited thereto. Composite layers can be three or more layers. The method for forming the inter-gate dielectric material layer 108 includes chemical vapor deposition or thermal oxidation. The material of the conductive material layer 110 is, for example, doped polysilicon. A method of forming the conductive material layer 110 includes performing a chemical vapor deposition method.

Furthermore, referring to FIG. 1C , the conductive material layer 110 , the inter-gate dielectric material layer 108 and the strip-shaped stacked structure 103 are patterned by photolithography and etching processes to form the gate structure 112 on the substrate 100 . The gate structure 112 includes a tunneling dielectric layer 102b, a floating gate 105, an inter-gate dielectric layer 108a, and a control gate 110a from bottom to top. The floating gate 105 includes a first portion 104b and a second portion 106b. Both the control gate 110a and the inter-gate dielectric layer 108a extend along the second direction D2. The second direction D2 is different from the first direction D1, such as being perpendicular to each other.

Next, an ion implantation process is performed by using the gate structure 112 as an implantation mask to form a source region and a drain region 114 in the substrate 100 on both sides of the gate structure 112 . In one embodiment, the substrate 100 has a first conductivity type, and the source region and the drain region 114 have a second conductivity type. The first conductivity type is, for example, P type; the second conductivity type is, for example, N type, and vice versa. So far, the fabrication of the memory element of the present invention is completed.

Hereinafter, examples of the present invention will be given to describe the present invention more specifically. However, materials, usage methods, and the like shown in the following examples may be appropriately changed without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be limited and interpreted by the specific examples shown below.

Example 1

In Example 1, a deposition process was performed using a low pressure chemical vapor deposition method to form a doped polysilicon layer on a silicon substrate. During the deposition process, a mixed gas including silane, phosphine and ethylene was fed, wherein the flow rate of ethylene was 4 sccm.

Example 2

A doped polysilicon layer was formed using a method similar to that of Example 1, the only difference being that the flow rate of ethylene was 7 sccm.

Example 3

A doped polysilicon layer was formed using a method similar to that of Example 1, the only difference being that the flow rate of ethylene was 10 sccm.

comparative example

The doped polysilicon layer was formed using a method similar to that of Example 1, the only difference being that the mixed gas introduced only included silane and phosphine.

Table 1 shows the results of the grain sizes of the doped polysilicon layers formed in Examples 1-3 and Comparative Examples.

Table 1

From the results in Table 1, it can be seen that under the same phosphorus concentration and the presence of C ₂ H ₄ gas, as the flow rate of C ₂ H ₄ gas increases, the particle size of the formed doped polysilicon layer becomes smaller . This is because during the formation of the doped polysilicon layer, the dopant (that is, carbon atoms) provided by the C ₂ H ₄ gas will prevent the diffusion of silicon atoms, thereby reducing the expansion of the grain boundaries, thus forming doped polysilicon with a smaller particle size Floor. It can also be seen from the above results that the particle size of the doped polysilicon layer can be controlled by adjusting the flow rate of the C ₂ H ₄ gas.

FIG. 2 is a graph of programmed threshold voltage distributions of memory elements. The first memory element has the floating gate composed of the first part and the second part of the present invention, and the second memory element has the floating gate only doped with the first dopant. It can be seen from FIG. 2 that since the particle size of the first portion of the floating gate of the first memory element of the present invention is smaller, a narrower programming threshold voltage distribution curve can be achieved, thereby improving the reliability of the memory element.

To sum up, in the process of forming the floating gate, the present invention first introduces a dopant gas containing a dopant that can prevent the diffusion of silicon atoms, so as to deposit a layer of particle size on the tunneling dielectric layer. A smaller doped layer, followed by a doped layer with a larger particle size. The doped layer with a smaller particle size helps to achieve a narrower programming threshold voltage distribution curve, thereby improving the reliability of the memory device.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. a kind of memory component, including：

Tunnel dielectric layer, in substrate；

Floating grid, including on the Part I in the tunnel dielectric layer and the Part I Part II, wherein described Part I contains the first admixture and the second admixture, the Part II Containing first admixture；

Dielectric layer between grid, on the floating grid；

Control gate, positioned between the grid on dielectric layer；And

Source area and drain region, in the substrate of the both sides of the floating grid,

The particle diameter of wherein described Part I is less than the particle diameter of the Part II, and the Part I Average grain diameter betweenExtremely

2. memory component according to claim 1, wherein described Part I and described The material of two parts includes DOPOS doped polycrystalline silicon, first admixture in wherein described Part I dense Degree is less than the concentration of first admixture in the Part II.

3. memory component according to claim 1, wherein described first admixture include arsenic, Phosphorus or boron；Second admixture includes carbon, nitrogen, oxygen or its combination.

4. a kind of memory component, including：

Tunnel dielectric layer, in substrate；

Floating grid, including on the Part I in the tunnel dielectric layer and the Part I Part II, wherein described Part I contains the first admixture and the second admixture, the Part II Containing first admixture；

Dielectric layer between grid, on the floating grid；

Control gate, positioned between the grid on dielectric layer；And

Source area and drain region, in the substrate of the both sides of the floating grid,

The electrical conductivity of wherein described Part I is less than the electrical conductivity of the Part II.

5. memory component according to claim 4, wherein described Part I and described The material of two parts includes DOPOS doped polycrystalline silicon, and the concentration of first admixture in the Part I is low The concentration of first admixture in the Part II.

6. memory component according to claim 4, wherein described first admixture include arsenic, Phosphorus or boron；Second admixture includes carbon, nitrogen, oxygen or its combination.

7. memory component according to claim 4, the average grain of wherein described Part I Footpath betweenExtremely

8. a kind of manufacture method of memory component, including：

Tunnel dielectric layer is formed in substrate；

The first depositing operation is carried out with the first mixed gas, floating to be formed in the tunnel dielectric layer The Part I of grid, wherein described first mixed gas include silicon source, the first impurity gas and Two impurity gas；

The second depositing operation is carried out with the second mixed gas, described floating to be formed on the Part I The Part II of grid is put, wherein described second mixed gas include that the silicon source and described first is mixed Miscellaneous gas；

Dielectric layer between grid is formed on the Part II；

Control gate is formed between the grid on dielectric layer；And

Source area and drain region are formed in the substrate of the side wall of the floating grid,

Wherein determine the Part I and the Part II by first impurity gas Conductivity type, and the particle size of the Part I is controlled by second impurity gas.

9. the manufacture method of memory component according to claim 8, wherein described first mixes Miscellaneous gas includes hydrogen phosphide, arsenic hydride or diborane；Second impurity gas include ethene, ammonia, Ozone or its combination.

10. the manufacture method of memory component according to claim 8, wherein described first The concentration of the first admixture that lease making is adulterated by first impurity gas less than the Part II via The concentration of first admixture of the first impurity gas doping.