CN106486084B

CN106486084B - Shift register cell, gate driving circuit and its driving method, display device

Info

Publication number: CN106486084B
Application number: CN201710004136.3A
Authority: CN
Inventors: 韩明夫; 商广良; 韩承佑; 金志河; 姚星; 郑皓亮; 袁丽君; 王志冲
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2017-01-04
Filing date: 2017-01-04
Publication date: 2019-01-18
Anticipated expiration: 2037-01-04
Also published as: CN106486084A

Abstract

The embodiment of the present invention provides a kind of shift register cell, gate driving circuit and its driving method, display device, is related to field of display technology, can be realized the conversion of multiple pixel resolutions.Pull-up control mould exports the signal of the first signal input part and second signal input terminal to pull-up node in the shift register cell.Pull-up module is by the voltage output at first voltage end to the first signal output end.The part signal that output width control module intercepts the first signal output end is exported to second signal output end.The current potential of pull-down node is pulled down to the voltage at second voltage end by pull-down control module, or by the voltage output of clock signal terminal to pull-down node.The current potential of pull-up node and the first signal output end is pulled down to the current potential at second voltage end by the first pull-down module respectively under the control of pull-down node.The current potential of second signal output end is pulled down to the current potential at second voltage end by the second pull-down module.

Description

Shifting register unit, grid driving circuit and driving method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a grid driving circuit, a driving method of the grid driving circuit and a display device.

Background

A Display device such as an LCD (Liquid Crystal Display) includes an array substrate and a color filter substrate which are aligned with each other. The array substrate comprises a plurality of grid lines and a plurality of data lines which are crossed transversely and longitudinally, and each grid line and one data line are crossed to define a sub-pixel. In this case, the number and pitch of the gate lines and the data lines determine the inherent resolution of the display device.

With the continuous development of high definition technology, in order to meet the display requirements of high definition pictures, the inherent resolution of the display device is higher and higher. However, in the actual display process, when the resolution of the picture to be displayed is lower than the inherent resolution of the display device, if the display device still performs display at the inherent resolution, unnecessary display power consumption is caused.

Disclosure of Invention

Embodiments of the present invention provide a shift register unit, a gate driving circuit, a driving method thereof, and a display device, which can implement conversion of resolutions of a plurality of pixels.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect of the embodiments of the present invention, a shift register unit is provided, including a pull-up control module, a pull-up module, an output width control module, a pull-down control module, a first pull-down module, and a second pull-down module; the pull-up control module is connected with a clock signal end, a first signal input end, a second signal input end and a pull-up node; the pull-up control module is used for outputting signals of the first signal input end and the second signal input end to the pull-up node under the control of the clock signal end; the pull-up module is connected with the pull-up node, the first voltage end and the first signal output end; the pull-up module is used for outputting the voltage of the first voltage end to the first signal output end under the control of the pull-up node; the output width control module is connected with the first signal output end, the first control signal end, the grounding end and the second signal output end; the output width control module is used for intercepting part of signals of the first signal output end and outputting the part of signals to the second signal output end under the control of the first control signal end and the grounding end; the pull-down control module is connected with the first signal input end, the clock signal end, the pull-down node and the second voltage end, and the pull-down control module is used for pulling down the potential of the pull-down node to the voltage of the second voltage end under the control of the first signal input end, or outputting the voltage of the clock signal end to the pull-down node under the control of the clock signal end; the first pull-down module is connected with the pull-down node, the pull-up node, the first signal output end and the second voltage end; the first pull-down module is used for respectively pulling down the potentials of the pull-up node and the first signal output end to the potential of the second voltage end under the control of the pull-down node; the second pull-down module is connected with a second control signal end, a second voltage end and a second signal output end; the second pull-down module is configured to pull down the potential of the second signal output terminal to the potential of the second voltage terminal under the control of the second control signal terminal.

Preferably, the pull-up control module includes: a first transistor and a first capacitor; the grid electrode of the first transistor is connected with the clock signal end, the first pole of the first transistor is connected with the first signal input end, and the second pole of the first transistor is connected with the pull-up node; one end of the first capacitor is connected with the second signal input end, and the other end of the first capacitor is connected with the pull-up node.

Preferably, the drawing-up module includes: and the grid electrode of the second transistor is connected with the pull-up node, the first pole of the second transistor is connected with the first voltage end, and the second pole of the second transistor is connected with the first signal output end.

Preferably, the output width control module includes: a third transistor and a second capacitor; the grid electrode of the third transistor is connected with a first control signal end, the first pole of the third transistor is connected with the second signal output end, and the second pole of the third transistor is connected with the first signal output end; one end of the second capacitor is connected with the first signal output end, and the second pole of the second capacitor is connected with the grounding end.

Preferably, the pull-down control module includes: a fourth transistor and a fifth transistor; the grid electrode and the first electrode of the fourth transistor are connected with the clock signal end, and the second electrode of the fourth transistor is connected with the pull-down node; the grid electrode of the fifth transistor is connected with the first signal input end, the first pole of the fifth transistor is connected with the pull-down node, and the second pole of the fifth transistor is connected with the second voltage end.

Preferably, the first pull-down module includes: a sixth transistor and a seventh transistor; a grid electrode of the sixth transistor is connected with the pull-down node, a first pole of the sixth transistor is connected with the pull-up node, and a second pole of the sixth transistor is connected with the second voltage end; the gate of the seventh transistor is connected to the pull-down node, the first pole of the seventh transistor is connected to the first signal output terminal, and the second pole of the seventh transistor is connected to the second voltage terminal.

Preferably, the second pull-down module includes: and the grid electrode of the eighth transistor is connected with the second control signal end, the first pole of the eighth transistor is connected with the second signal output end, and the second pole of the eighth transistor is connected with the second voltage end.

In another aspect of the embodiments of the present invention, a gate driving circuit is provided for outputting a scan signal to a gate line; the shift register unit comprises a plurality of cascaded shift register units of any one type; a first signal input end of the first-stage shift register unit is connected with an initial signal end; except the first-stage shift register unit, the first signal input ends of the other shift register units are connected with the first signal output end of the first-stage shift register unit; the second signal input end of the last stage of shift register unit is connected with the initial signal end; except the last stage of shift register unit, the second signal input ends of the other shift register units are connected with the first signal output end of the next stage of shift register unit; the second signal output end of each stage of shift register unit is connected with a grid line; each twelve sequentially cascaded shift register units form a driving group; the driving group comprises a first shift register unit, a second shift register unit, a third shift register unit, a fourth shift register unit, a fifth shift register unit, a sixth shift register unit, a seventh shift register unit, an eighth shift register unit, a ninth shift register unit, a tenth shift register unit, an eleventh shift register unit and a twelfth shift register unit which are sequentially cascaded; a first control signal end and a second control signal end of the first shift register unit are respectively connected with a first system clock signal end and a seventh system clock signal end; the first control signal end and the second control signal end of the second shift register unit are respectively connected with the second system clock signal end and the eighth system clock signal end; the first control signal end and the second control signal end of the third shift register unit are respectively connected with a third system clock signal end and a ninth system clock signal end; a first control signal end and a second control signal end of the fourth shift register unit are respectively connected with a fourth system clock signal end and a tenth system clock signal end; a first control signal end and a second control signal end of the fifth shift register unit are respectively connected with a fifth system clock signal end and an eleventh system clock signal end; a first control signal end and a second control signal end of the sixth shift register unit are respectively connected with a sixth system clock signal end and a twelfth system clock signal end; a first control signal end and a second control signal end of the seventh shift register unit are respectively connected with a seventh system clock signal end and a first system clock signal end; a first control signal end and a second control signal end of the eighth shift register unit are respectively connected with an eighth system clock signal end and a second system clock signal end; a first control signal end and a second control signal end of the ninth shift register unit are respectively connected with a ninth system clock signal end and a third system clock signal end; a first control signal end and a second control signal end of the tenth shift register unit are respectively connected with a tenth system clock signal end and a fourth system clock signal end; a first control signal end and a second control signal end of the eleventh shift register unit are respectively connected with an eleventh system clock signal end and a fifth system clock signal end; and a first control signal end and a second control signal end of the twelfth shift register unit are respectively connected with a twelfth system clock signal end and a sixth system clock signal end.

In a further aspect of the embodiments of the present invention, there is provided a method for driving the gate driving circuit as described above, the method including: signals input by any two system clock signal ends connected with the same driving group are different; or when the width of the signal output end of the initial signal end is 4H, the same signal is input into the first system clock signal end and the second system clock signal end; the same signal is input into a third system clock signal end and a fourth system clock signal end; the same signal is input into a fifth system clock signal end and a sixth system clock signal end; the seventh system clock signal end and the eighth system clock signal end input the same signal; the ninth system clock signal end and the tenth system clock signal end input the same signal; the eleventh system clock signal end and the twelfth system clock signal end input the same signal; or when the width of the signal output end of the initial signal end is 8H, the same signal is input into the first system clock signal end, the second system clock signal end, the third system clock signal end and the fourth system clock signal end; inputting the same signals into a fifth system clock signal terminal, a sixth system clock signal terminal, a seventh system clock signal terminal and an eighth system clock signal terminal; the ninth system clock signal end, the tenth system clock signal end, the eleventh system clock signal end and the twelfth system clock signal end input the same signal; or when the width of the signal output end of the initial signal end is 12H, the same signal is input into the first system clock signal end, the second system clock signal end, the third system clock signal end, the fourth system clock signal end, the fifth system clock signal end and the sixth system clock signal end; inputting the same signals into a seventh system clock signal end, an eighth system clock signal end, a ninth system clock signal end, a tenth system clock signal end, an eleventh system clock signal end and a twelfth system clock signal end; wherein, H is a ratio of the scanning time of one image frame to the total number of the grid lines.

In another aspect of the embodiments of the present invention, a display device is provided, which includes the even number of gate driving circuits.

The embodiment of the invention provides a shift register unit, a grid driving circuit, a driving method of the grid driving circuit and a display device. The shift register unit comprises a pull-up control module, a pull-up module, an output width control module, a pull-down control module, a first pull-down module and a second pull-down module. The pull-up control module is connected with the clock signal end, the first signal input end, the second signal input end and the pull-up node. The pull-up control module is used for outputting signals of the first signal input end and the second signal input end to a pull-up node under the control of the clock signal end. The pull-up module is connected with the pull-up node, the first voltage end, the output width control module and the first signal output end. The pull-up module is used for outputting the voltage of the first voltage end to the first signal output end under the control of a pull-up node. The output width control module is connected with the first signal output end, the first control signal end, the grounding end and the second signal output end. The output width control module is used for intercepting part of signals of the first signal output end and outputting the part of signals to the second signal output end under the control of the first control signal end and the grounding end. The pull-down control module is connected with the first signal input end, the clock signal end, the pull-down node and the second voltage end, and the pull-down control module is used for pulling down the potential of the pull-down node to the voltage of the second voltage end under the control of the first signal input end or outputting the voltage of the clock signal end to the pull-down node under the control of the clock signal end. The first pull-down module is connected with the pull-down node, the pull-up node, the first signal output end and the second voltage end. The first pull-down module is used for respectively pulling down the electric potentials of the pull-up node and the first signal output end to the electric potential of the second voltage end under the control of the pull-down node. The second pull-down module is connected with the second control signal end, the second voltage end and the second signal output end. The second pull-down module is used for pulling down the potential of the second signal output end to the potential of the second voltage end under the control of the second control signal end.

Therefore, under the control of the first control signal terminal, the output width control module can intercept part of signals of the first signal output terminal and output the part of signals to the second signal output terminal. Therefore, when the second signal output end is connected with the grid line, the intercepted signal can be output to the grid line connected with the second signal output end through the second signal output end, so that the intercepted signal can be used as a grid scanning signal of the grid line to scan the grid line. In this case, when the gate driving circuit is configured by using the shift register unit described above, in order to reduce resolution, the width of a signal input to the first signal input terminal of the first stage shift register unit, i.e., a start signal, may be adjusted so that signals output from the first signal output terminals of a plurality of shift registers arranged in sequence have overlap. On this basis, the same clock signal may be input to the first control signal terminals of the plurality of shift registers arranged in sequence, so that the second signal output terminals of the plurality of shift registers arranged in sequence all output the signal of the overlapped part under the control of the first control signal terminals respectively. Therefore, the signals output by the second signal output ends of the plurality of shift registers are the same, so that the grid lines connected with the plurality of shift register units are simultaneously opened, and the aim of reducing the resolution ratio is fulfilled. In addition, the second control signal terminal can pull down the potential of the first signal output terminal to the potential of the second voltage terminal when the grid line does not need to receive the grid scanning signal, so that the phenomenon of mistaken output of the grid line in a non-scanning stage can be avoided.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram showing the detailed structure of each module in FIG. 1;

FIG. 3 is a signal timing diagram of each signal terminal and node in FIG. 2;

FIG. 4 is a schematic diagram of a gate driving circuit having the shift register unit shown in FIG. 1 or FIG. 2;

FIG. 5 is a timing diagram of control signals with the inherent resolution of the gate driving circuit shown in FIG. 4;

FIG. 6 is a timing diagram of control signals for one-half of the inherent resolution exhibited by the gate driver circuit of FIG. 4;

FIG. 7 is a timing diagram of control signals with the gate driver circuit of FIG. 4 showing one-fourth of the native resolution;

fig. 8 is a timing diagram of control signals when the display resolution is HD with the gate driving circuit shown in fig. 4.

Reference numerals:

01-a drive group; 10-a pull-up control module; 20-a pull-up module; 30-output width control module; 40-a pull-down control module; 50-a first pulldown module; 60-second pull-down module.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a shift register unit, as shown in fig. 1, including a pull-up control module 10, a pull-up module 20, an output width control module 30, a pull-down control module 40, a first pull-down module 50, and a second pull-down module 60.

Optionally, the pull-up control module 10 is connected to the clock signal terminal CK, the first signal INPUT terminal INPUT, the second signal INPUT terminal BOOT, and the pull-up node PU. The pull-up control module 10 is configured to output signals of the first signal INPUT terminal INPUT and the second signal INPUT terminal BOOT to the pull-up node PU under the control of the clock signal terminal CK.

The pull-up module 20 is connected to the pull-up node PU, the first voltage terminal VDD, and the first signal output terminal OUT. The pull-up module 20 is configured to OUTPUT a voltage of the first voltage terminal VDD to the first signal OUTPUT terminal OUTPUT under the control of the pull-up node PU.

The OUTPUT width control module 30 is connected to the first signal OUTPUT terminal OUT, the first control signal terminal CN1, the ground terminal GND and the second signal OUTPUT terminal OUTPUT. The OUTPUT width control module 30 is configured to intercept a part of the signal of the first signal OUTPUT terminal OUT and OUTPUT the intercepted part of the signal to the second signal OUTPUT terminal OUTPUT under the control of the first control signal terminal CN1 and the ground terminal GND.

The pull-down control module 40 is connected to the first signal INPUT terminal INPUT, the clock signal terminal CK, the pull-down node PD, and the second voltage terminal VSS. The pull-down control module 40 is configured to pull down the potential of the pull-down node PD to the voltage of the second voltage terminal VSS under the control of the first signal INPUT terminal INPUT. Alternatively, the pull-down control module 40 is configured to output the voltage of the clock signal terminal CK to the pull-down node PD under the control of the clock signal terminal CK.

The first pull-down module 50 is connected to the pull-down node PD, the pull-up node PU, the first signal output terminal OUT, and the second voltage terminal VSS. The first pull-down module 50 is configured to pull down the potentials of the pull-up node PU and the first signal output terminal OUT to the potential of the second voltage terminal VSS respectively under the control of the pull-down node PD.

The second pull-down module 60 is connected to the second control signal terminal CN2, the second voltage terminal VSS and the second signal OUTPUT terminal OUTPUT. The second pull-down module 60 is configured to pull down the potential of the second signal OUTPUT terminal OUTPUT to the potential of the second voltage terminal under the control of the second control signal terminal CN 2.

In the embodiment of the present invention, the signals output from the first control signal terminal CN1 and the second control signal terminal CN2 are high-low level. In the following embodiments, the first voltage terminal VDD is input with a constant high level, and the second voltage terminal VSS is input with a constant low level or grounded.

As can be seen from the above, under the control of the first control signal CN1, the OUTPUT width control module 30 can intercept a part of the signal OUTPUT from the first signal OUTPUT terminal OUT and OUTPUT the part of the signal to the second signal OUTPUT terminal OUTPUT. Therefore, when the second signal OUTPUT terminal OUTPUT is connected to the gate line, the intercepted signal may be OUTPUT to the gate line connected to the second signal OUTPUT terminal OUTPUT through the second signal OUTPUT terminal OUTPUT, so that the intercepted signal may be used as a gate scanning signal of the gate line to scan the gate line. In this case, when the gate driving circuit is configured by using the shift register units described above, the width of the signal INPUT to the first signal INPUT terminal INPUT of the first stage shift register unit, i.e., the start signal STV, may be adjusted in order to reduce the resolution so that the signals output from the first signal output terminals INPUT of the plurality of shift registers arranged in sequence have overlap. On this basis, the same clock signal may be input to the first control signal terminals CN1 of the plurality of shift registers arranged in sequence, so that the second signal OUTPUT terminals OUTPUT of the plurality of shift registers arranged in sequence all OUTPUT the signal of the overlapped part under the control of the first control signal terminals CN 1. In this way, the signals OUTPUT by the second signal OUTPUT terminals OUTPUT of the plurality of shift registers are the same, so that the gate lines connected with the plurality of shift register units are simultaneously turned on, and the purpose of reducing the resolution is achieved. In addition, the second control signal terminal CN2 can pull down the potential of the first signal OUTPUT terminal OUTPUT to the potential of the second voltage terminal VSS when the gate line does not need to receive the gate scan signal, so as to avoid the occurrence of the phenomenon of gate line erroneous OUTPUT in the non-scanning stage.

Hereinafter, a specific configuration of each block in the shift register unit will be described in detail.

Alternatively, as shown in fig. 2, the pull-up control module 10 may include: a first transistor M1 and a first capacitor C1.

The gate of the first transistor M1 is connected to the clock signal terminal CK, the first pole is connected to the first signal INPUT terminal INPUT, and the second pole is connected to the pull-up node PU.

One end of the first capacitor C1 is connected to the second signal input terminal BOOT, and the other end is connected to the pull-up node PU.

In addition, the pull-up module 20 includes a second transistor M2 having a gate connected to the pull-up node PU, a first pole connected to the first voltage terminal VDD, and a second pole connected to the first signal output terminal OUT.

The output width control module 30 includes: a third transistor M3 and a second capacitor C2.

The gate of the third transistor M3 is connected to the first control signal terminal CN1, the first pole is connected to the second signal OUTPUT terminal OUTPUT, and the second pole is connected to the first signal OUTPUT terminal OUT.

One end of the second capacitor C2 is connected to the first signal output terminal OUT, and the second pole is connected to the ground terminal GND.

The pull-down control module 40 includes: a fourth transistor N4 and a fifth transistor M5.

The gate and the first pole of the fourth transistor M4 are connected to the clock signal terminal CK, and the second pole is connected to the pull-down node PD.

The gate of the fifth transistor M5 is connected to the first signal INPUT terminal INPUT, the first pole is connected to the pull-down node PD, and the second pole is connected to the second voltage terminal VSS.

The first pull-down module 50 includes: a sixth transistor M6 and a seventh transistor M7;

the gate of the sixth transistor M6 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the second voltage terminal VSS.

The seventh transistor M7 has a gate connected to the pull-down node PD, a first pole connected to the first signal output terminal OUT, and a second pole connected to the second voltage terminal VSS.

The second pull-down module 60 includes an eighth transistor M8, a gate of the eighth transistor M8 is connected to the second control signal terminal CN2, a first pole of the eighth transistor is connected to the second signal OUTPUT terminal OUTPUT, and a second pole of the eighth transistor is connected to the second voltage terminal VSS.

In the present invention, the types of the transistors are not limited, and all of the transistors may be N-type transistors or all of the transistors may be P-type transistors. In addition, the first electrode of the transistor can be a source electrode, and the second electrode of the transistor can be a drain electrode; alternatively, the first pole is a drain and the second pole is a source.

Hereinafter, a method for driving the shift register unit shown in fig. 2 in one image frame will be described in detail with reference to the signal timing diagram shown in fig. 3 by taking the above transistors as N-type transistors as an example.

As shown in fig. 3, in the first phase P1 of an image frame, CK is 0, INPUT is 1, BOOT is 0, CN1 is 1, CN2 is 0, OUT is 0, and OUTPUT is 0; where "0" represents a low level and "1" represents a high level.

In this case, the clock signal terminal CK inputs a low level, and the first transistor M1 and the fourth transistor M4 are turned off. The second signal input terminal BOOT inputs a low level. At this time, the pull-up node PU is at a low level, the second transistor M2 is turned off, and the first signal output terminal OUT outputs a low level. In this case, the first control signal terminal CN1 inputs a high level, the third transistor M3 is turned on, a part of the signal OUTPUT from the first signal OUTPUT terminal OUT captured by the third transistor M3 is at a low level, and the low level is OUTPUT from the second signal OUTPUT terminal OUTPUT. As can be seen from the above description, in the first phase P1, the first signal OUTPUT terminal OUT and the second signal OUTPUT terminal OUTPUT both OUTPUT a low level, and the shift register unit does not OUTPUT the gate scan signal to the gate line connected thereto, so that the shift register unit is in the non-OUTPUT phase.

In addition, the high level of the first signal INPUT terminal INPUT turns on the fifth transistor M5, and the potential of the pull-down node PD is pulled down to the potential of the second voltage terminal VSS by the fifth transistor M5. At this time, the sixth transistor M6 and the seventh transistor M7 are turned off. The second control signal terminal CN2 is inputted with a low level, and the eighth transistor M8 is turned off.

In the second phase P2 of an image frame, CK is 1, INPUT is 1, BOOT is 0, CN1 is 0, CN2 is 1, OUT is 1, and OUTPUT is 0.

In this case, the clock signal terminal CK inputs a high level, and the first transistor M1 and the fourth transistor M4 are turned on. The first signal INPUT terminal INPUT INPUTs a high level and the fifth transistor M5 is turned on. At this time, the high level of the first signal INPUT terminal INPUT is output to the pull-up node PU through the first transistor M1, and the second transistor M2 is turned on under the control of the pull-up node PU, so that the high level of the first voltage terminal VDD INPUT is output to the first signal output terminal OUT through the second transistor M2. Based on this, since the first control signal terminal CN1 inputs a low level, the third transistor M3 is turned off, so that a part of the signal at the first signal OUTPUT terminal OUT is not intercepted and outputted through the second signal OUTPUT terminal OUTPUT at this stage, and thus the shift register unit is in the non-OUTPUT stage.

On this basis, the second control signal terminal CN2 inputs a high level to turn on the eighth transistor M8, and the eighth transistor M8 pulls down the potential of the second signal OUTPUT terminal OUTPUT to a low level of the second voltage terminal VSS, so as to avoid the occurrence of the phenomenon that the second signal OUTPUT terminal OUTPUT erroneously OUTPUTs the gate scan signal in the non-OUTPUT stage of the shift register unit.

Further, the fourth transistor M4 is turned on, thereby outputting the high level input from the clock signal terminal CK to the pull-down node PD. But since the fifth transistor M5 is turned on, the potential of the pull-down node PD is pulled down to the low level of the second voltage terminal VSS again. In this case, the sixth transistor M6 and the seventh transistor M7 are turned off.

In the third stage P3 of an image frame, CK is 0, INPUT is 1, BOOT is 1, CN1 is 0, CN2 is 1, OUT is 1, and OUTPUT is 0.

On this basis, the clock signal terminal CK inputs a low level, and the first transistor M1 and the fourth transistor M4 are turned off. The second signal input terminal BOOT inputs a high level, and the potential of the pull-up node PU is further increased under the self-coupling effect of the first capacitor C1. The second transistor M2 is turned on, and the high level of the first voltage terminal VDD is output to the first signal output terminal OUT. However, since the first control signal terminal CN1 is still at the low level and the second control signal terminal CN2 is still at the high level at this stage, the potential of the second signal OUTPUT terminal OUTPUT is pulled down to the low level of the second voltage terminal VSS. The phase shift register cell is still in the non-scanning phase.

In addition, as in the first phase P1, the fifth transistor M5 is turned on, and the potential of the pull-down node PD is pulled down to the potential of the second voltage terminal VSS. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are turned off.

In the fourth phase P4 of an image frame, CK is 1, INPUT is 1, BOOT is 1, CN1 is 1, CN2 is 0, OUT is 1, and OUTPUT is 1.

In this case, as in the second stage P2, the first transistor M1 is turned on, and the high level of the first signal INPUT terminal INPUT is output to the pull-up node PU, and at this time, the potential of the pull-up node PU is further increased because the high level is also INPUT to the second signal INPUT terminal BOOT. At this time, the second transistor M2 is turned on, and the high level of the first voltage terminal VDD is output to the first signal output terminal OUT. Based on this, since the first control signal terminal CN1 inputs a high level at this stage, the third transistor M3 is turned on, so that the signal OUTPUT from the first signal OUTPUT terminal OUT at the fourth stage P4 can be intercepted and transmitted to the second signal OUTPUT terminal OUTPUT, so that the second signal OUTPUT terminal OUTPUT OUTPUTs a high level to scan the gate line connected to the second signal OUTPUT terminal OUTPUT. The second capacitor C2 may enable the signal intercepted by the first signal OUTPUT terminal OUT to be continuously OUTPUT to the second signal OUTPUT terminal OUTPUT.

In summary, the second signal OUTPUT terminal OUTPUT OUTPUTs the gate scan signal at this stage, so the fourth stage is the scan stage of the shift register unit.

On this basis, the second control signal terminal CN2 is inputted with a low level, and the eighth transistor M8 is turned off. In addition, in the second phase P2, the fourth transistor M4 and the fifth transistor M5 are turned on, and the potential of the pull-down node PD is pulled down to the low level of the second voltage terminal VSS. The sixth transistor M6 and the seventh transistor M7 are turned off.

In the fifth phase P5 of an image frame, CK is 0, INPUT is 0, BOOT is 1, CN1 is 1, CN2 is 0, OUT is 1, and OUTPUT is 1.

In this case, the first transistor M1 and the fourth transistor M4 are turned off, like the third stage P3. Since the second signal input terminal BOOT inputs a high level, the pull-up node PU maintains a high level. At this time, the second transistor M2 is turned on, and the first signal output terminal OUT outputs a high level. And the first control signal terminal CN1 controls the third transistor M3 to be turned on. Therefore, the signal OUTPUT from the first signal OUTPUT terminal OUT in the fifth phase P5 can still be intercepted and transmitted to the second signal OUTPUT terminal OUTPUT, so that the second signal OUTPUT terminal OUTPUT OUTPUTs a high level to scan the gate line connected to the second signal OUTPUT terminal OUTPUT. In this stage, the second signal OUTPUT terminal OUTPUT OUTPUTs the gate scan signal, so the fifth stage is the scan stage of the shift register unit.

In addition, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all turned off.

In the sixth phase P6 of an image frame, CK is 1, INPUT is 0, BOOT is 1, CN1 is 0, CN2 is 1, OUT is 0, and OUTPUT is 0.

In this case, the first transistor M1 and the fourth transistor M4 are turned on, and the fifth transistor M5 is turned off. The high level input from the clock signal terminal CK is output to the pull-down node PD through the fourth transistor M4. Under the control of the pull-down node PD, the sixth transistor M6 is turned on to pull down the potential of the pull-up node PU to the low level of the second voltage terminal VSS. In addition, the seventh transistor M7 is turned on to pull the potential of the first signal output terminal OUT to the low level of the second voltage terminal VSS. At this time, the second signal OUTPUT terminal OUTPUT also OUTPUTs a low level, so that the stage is a non-scanning stage of the shift register unit.

In the seventh phase P7 of an image frame, CK is 0, INPUT is 0, BOOT is 0, CN1 is 0, CN2 is 1, OUT is 0, and OUTPUT is 0.

In this case, the second signal input terminal BOOT inputs a low level, so that the pull-up node PU is a low level and the second transistor M2 is turned off. The first signal OUTPUT terminal OUT maintains a low level OUTPUT, and the second signal OUTPUT terminal OUTPUT OUTPUTs a low level.

It should be noted that the first signal OUTPUT terminal OUT and the second signal OUTPUT terminal OUTPUT always OUTPUT a low level before the next image frame, i.e., before the first signal INPUT terminal INPUT OUTPUTs a high level again.

In summary, the first signal output terminal OUT of the shift register unit outputs high level during the second phase P2 to the fifth phase P5 of a frame. Under the control of the first control signal terminal CN1, the first signal OUTPUT terminal OUT may be cut off at the high levels of the fourth and fifth stages P4 and P5, and OUTPUT to the gate line connected to the shift register unit through the second signal OUTPUT terminal OUTPUT, so as to scan the gate line.

Based on the above description, embodiments of the present invention provide a gate driving circuit for outputting a scan signal to a gate line. As shown in fig. 4, the gate driver circuit includes a plurality of cascade-connected shift register units (SR1, SR2, sr3.. sr12..) of any of the types described above.

The first signal INPUT terminal INPUT of the first stage shift register SR1 is connected to the start signal terminal STV.

Except for the first stage of shift register unit SR1, the first signal INPUT terminal INPUT of the remaining shift register units is connected to the first signal output terminal OUT of the first stage of shift register unit.

And a second signal input end BOOT of the last stage of shift register unit is connected with a starting signal end STV.

Except the last stage of shift register unit, the second signal input ends BOOT of the rest shift register units are connected with the first signal output end OUT of the next stage of shift register unit. And the second signal OUTPUT terminal OUTPUT of each stage of the shift register unit is connected to one gate line (G1, G2, G3... G12.).

In addition, twelve shift register units which are cascaded in sequence form one driving group 01.

The driving group 01 includes a first shift register unit, a second shift register unit, a third shift register unit, a fourth shift register unit, a fifth shift register unit, a sixth shift register unit, a seventh shift register unit, an eighth shift register unit, a ninth shift register unit, a tenth shift register unit, an eleventh shift register unit and a twelfth shift register unit, which are sequentially cascaded.

Taking the driving group 01 composed of the first stage shift register unit SR1 to the twelfth stage shift register unit SR12 as an example, the first shift register unit is the first stage shift register unit SR1, the second shift register unit is the second stage shift register unit SR2, the third shift register unit is the third stage shift register unit SR3, the fourth shift register unit is the fourth stage shift register unit SR4, the fifth shift register unit is the fifth stage shift register unit SR5, the sixth shift register unit is the sixth stage shift register unit SR6, the seventh shift register unit is the seventh stage shift register unit SR7, the eighth shift register unit is the eighth stage shift register unit SR8, the ninth shift register unit is the ninth stage shift register unit SR9, the tenth shift register unit is the tenth stage shift register unit SR10, the eleventh shift register unit is an eleventh-stage shift register unit SR11, and the twelfth shift register unit is a twelfth-stage shift register unit SR12.

In this case, the first and second control signal terminals CN1 and CN2 of the first shift register unit SR1 are connected to the first and seventh system clock signal terminals CLK1 and CLK7, respectively.

The first and second control signal terminals CN1 and CN2 of the second shift register unit SR2 are connected to the second and eighth system clock signal terminals CLK2 and CLK8, respectively.

The first and second control signal terminals CN1 and CN2 of the third shift register unit SR3 are connected to the third and ninth system clock signal terminals CLK3 and CLK9, respectively.

The first and second control signal terminals CN1 and CN2 of the fourth shift register unit SR4 are connected to the fourth and tenth system clock signal terminals CLK4 and CLK10, respectively.

The first and second control signal terminals CN1 and CN2 of the fifth shift register unit SR5 are connected to the fifth and eleventh system clock signal terminals CLK5 and CLK11, respectively.

The first and second control signal terminals CN1 and CN2 of the sixth shift register unit SR6 are connected to the sixth and twelfth system clock signal terminals CLK6 and CLK12, respectively.

The first and second control signal terminals CN1 and CN2 of the seventh shift register unit SR7 are respectively connected to the seventh and first system clock signal terminals CLK7 and CLK 1.

The first and second control signal terminals CN1 and CN2 of the eighth shift register unit SR8 are connected to the eighth and second system clock signal terminals CLK8 and CLK2, respectively.

The first and second control signal terminals CN1 and CN2 of the ninth shift register unit SR9 are connected to the ninth and third system clock signal terminals CLK9 and CLK3, respectively.

The first and second control signal terminals CN1 and CN2 of the tenth shift register unit SR10 are connected to the tenth and fourth system clock signal terminals CLK10 and CLK4, respectively.

The first and second control signal terminals CN1 and CN2 of the eleventh shift register unit SR11 are connected to the eleventh and fifth system clock signal terminals CLK11 and CLK5, respectively.

The first and second control signal terminals CN1 and CN2 of the twelfth shift register unit SR12 are connected to the twelfth and sixth system clock signal terminals CLK12 and CLK6, respectively.

In this case, the width of the start signal STV INPUT to the first signal INPUT terminal INPUT of the first shift register unit in one drive group 01, for example, the first stage shift register unit SR1, may be adjusted so that the signals output from the first signal output terminals OUT of the plurality of shift register units located in one drive group 01 have an overlapping portion.

Based on this, when the signals input by the first control signal terminals CN1 of the plurality of shift register units are the same, the overlapping portion can be intercepted and OUTPUT through the second signal OUTPUT terminals OUTPUT of the shift register units, so that the scan signals received by the gate lines connected to the plurality of shift register units are the same, and are simultaneously turned on, thereby achieving the purpose of reducing resolution.

Hereinafter, a method of driving the gate driving circuit when the resolution of a screen to be displayed is equal to or less than the intrinsic resolution of the display device will be described in detail, taking the intrinsic resolution of the display device having the gate driving circuit as an example of 8K.

For example, when the display device performs display with the intrinsic resolution 8, the method of driving the gate driving circuit includes, as shown in fig. 5, that signals input to any two system clock signal terminals connected to the same driving group 01 are different. That is, the signals inputted to any two system clock signal terminals among the first system clock signal terminal CLK1 through the twelfth system clock signal terminal CLK12 are different. As shown in fig. 5, the signals outputted from the first system clock signal terminal CLK1 to the twelfth system clock signal terminal CLK12 have a certain phase difference in sequence.

In this way, the first control signal terminal CN1 of each shift register unit can always OUTPUT high level, so that the signals OUTPUT by the second signal OUTPUT terminal OUTPUT and the first signal OUTPUT terminal OUT of each shift register unit are the same. Since the signals OUTPUT by the first signal OUTPUT terminals OUT of the plurality of shift register units arranged in sequence have the phase difference in sequence, the signals OUTPUT by the second signal OUTPUT terminals OUTPUT of the plurality of shift register units arranged in sequence also have the phase difference, so that all the gate lines can be scanned line by line.

It should be noted that the phase difference may be set according to the needs of the user, for example, in fig. 5, when the high level duration of the start signal terminal STV is 4H, the time difference between the signals output by two adjacent system clock signal terminals may be 1H. Where H may be a scanning time of one row of pixels, i.e. a ratio of the scanning time of one image frame to the total number of gate lines.

In addition, the signals inputted from the first system clock signal terminal CLK1 to the twelfth system clock signal terminal CLK12 are square wave signals whose high and low levels are sequentially overlapped. In the drawings, in order to more clearly show that signals output by different system clock signal terminals are the same or have phase differences, only part of square waves are drawn in the signals, and the rest of square waves are omitted.

Alternatively, for another example, when the display resolution of the display device is switched from 8K to 4K, the method for driving the gate driving circuit includes: the width of the signal output end of the start signal end STV is adjusted, as shown in fig. 6, the width of the signal output end of the start signal end STV is 4H, and at this time, the signal output by the first signal output end OUT of the shift register unit connected to two rows of gate lines adjacent in sequence has an overlapping portion.

For example, the first signal output terminal OUT1 of the first shift register unit SR1 has an overlapping portion with the signal output from the first signal output terminal OUT2 of the first shift register unit SR 2; the first signal output terminal OUT3 of the third shift register unit SR3 has an overlapping portion with the signal output from the first signal output terminal OUT4 of the fourth shift register unit SR 4. The signals output by the first signal output ends OUT of the rest of the driving groups 01 or the sequentially adjacent shift register units in the rest of the driving groups 01 are the same as those described above, and are not repeated herein.

In this case, the first system clock signal terminal CLK1 and the second system clock signal terminal CLK2 input the same signal; the third system clock signal terminal CLK3 and the fourth system clock signal terminal CLK4 input the same signal; the fifth system clock signal terminal CLK5 and the sixth system clock signal terminal CLK6 input the same signal; the seventh system clock signal terminal CLK7 and the eighth system clock signal terminal CLK8 input the same signal; the ninth system clock signal terminal CLK9 and the tenth system clock signal terminal CLK10 input the same signal; the eleventh and twelfth system clock signal terminals CLK11 and CLK12 receive the same signal.

So that the signals inputted from the first control signal terminals CN1 of two shift register units located in the same driving group 01 and adjacent to each other are the same. For example, the signals input to the first control signal terminal CN1 of the first shift register unit SR1 and the second shift register unit SR2 are the same; the signals input to the first control signal terminal CN1 of the third shift register unit SR3 and the fourth shift register unit SR4 are the same. The signals input by the first control signal terminals CN1 of the two shift register units sequentially adjacent to each other in the remaining driving group 01 or the remaining driving group 01 are the same as those described above, and are not repeated herein.

In this case, the overlapped part can be intercepted by the first control signal terminal CN1 and OUTPUT through the second signal OUTPUT terminals OUTPUT of the respective shift register units, so that the signals input by the second signal OUTPUT terminals OUTPUT of two shift register units adjacent in sequence in the same driving group 01 are the same. For example, the signals input from the second signal OUTPUT terminal OUTPUT1 of the first shift register unit SR1 and the second signal OUTPUT terminal OUTPUT2 of the second shift register unit SR2 are the same; the signals input from the second signal OUTPUT terminal OUTPUT3 of the third shift register unit SR3 and the second signal OUTPUT terminal OUTPUT4 of the fourth shift register unit SR4 are the same. Signals input by the second signal OUTPUT terminals OUTPUT of the other two sequentially adjacent shift register units are the same as those described above, and are not described in detail herein.

Based on this, taking the driving group 01 connected to the gate lines (G1-G12) as an example, the gate lines G1 and G2 receive the gate scan signal at the same time; g3 and G4 receive the grid scanning signal at the same time; g5 and G6 receive the grid scanning signal at the same time; g7 and G8 receive the grid scanning signal at the same time; g9 and G10 receive the grid scanning signal at the same time; the gate scan signals are received at the same time by G11 and G12. Similarly, for the whole array substrate, when the forward scanning is adopted, two rows of sub-pixels sequentially arranged from top to bottom are simultaneously started, and at the moment, the data signals received by two sub-pixels positioned in the same column in the two rows of sub-pixels are the same, so that the same gray scale is displayed. Thus, the display device having the gate driver circuit has a resolution of 4K, which is one half of the intrinsic resolution 8K.

Alternatively, for another example, in order to further reduce the resolution, when the resolution displayed by the display device is switched from 4K to 2K, the method for driving the gate driving circuit includes: the width of the signal output end of the start signal end STV is adjusted, as shown in fig. 7, the width of the signal output end of the start signal end STV is 8H, and at this time, signals output by the first signal output ends OUT of the shift register units connected to four rows of gate lines adjacent in sequence have an overlapping portion.

For example, the signals output by the first signal output terminal OUT1 of the first shift register unit SR1, the first signal output terminal OUT2 of the first shift register unit SR2, the first signal output terminal OUT3 of the third shift register unit SR3, and the first signal output terminal OUT4 of the fourth shift register unit SR4 have overlapping portions. The signals output by the first signal output terminal OUT5 of the fifth shift register unit SR5, the first signal output terminal OUT6 of the sixth shift register unit SR6, the first signal output terminal OUT7 of the seventh shift register unit SR7, and the first signal output terminal OUT8 of the eighth shift register unit SR8 have overlapping portions. The signals output by the first signal output ends OUT of the rest of the driving groups 01 or the sequentially adjacent shift register units in the rest of the driving groups 01 are the same as those described above, and are not repeated herein.

In this case, the first system clock signal terminal CLK1, the second system clock signal terminal CLK2, the third system clock signal terminal CLK3, the fourth system clock signal terminal CLK4 input the same signal; the fifth system clock signal terminal CLK5, the sixth system clock signal terminal CLK6, the seventh system clock signal terminal CLK7, and the eighth system clock signal terminal CLK8 input the same signals; the ninth system clock signal terminal CLK9, the tenth system clock signal terminal CLK10, the eleventh system clock signal terminal CLK11, and the twelfth system clock signal terminal CLK12 input the same signals.

In this case, the overlapped part can be intercepted by the first control signal terminal CN1 and OUTPUT through the second signal OUTPUT terminals OUTPUT of the respective shift register units, so that the signals input by the second signal OUTPUT terminals OUTPUT of four shift register units adjacent in sequence in the same driving group 01 are the same. For example, the signals input from the second signal OUTPUT terminal OUTPUT1 of the first shift register unit SR1, the second signal OUTPUT terminal OUTPUT2 of the second shift register unit SR2, the second signal OUTPUT terminal OUTPUT3 of the third shift register unit SR3 and the second signal OUTPUT terminal OUTPUT4 of the fourth shift register unit SR4 are the same. The signals input from the second signal OUTPUT terminal OUTPUT5 of the fifth shift register unit SR5, the second signal OUTPUT terminal OUTPUT6 of the sixth shift register unit SR6, the second signal OUTPUT terminal OUTPUT7 of the seventh shift register unit SR7, and the second signal OUTPUT terminal OUTPUT8 of the eighth shift register unit SR8 are the same. The signals input by the second signal OUTPUT terminals OUTPUT of the other driving groups 01 or the sequentially adjacent four shift register units in the other driving groups 01 are the same as those described above, and are not repeated herein.

In this case, taking the driving group 01 connected to the gate lines (G1-G12) as an example, the gate lines G1, G2, G3, and G4 receive the gate scan signals at the same time; the gate scanning signals are received by G5, G6, G7 and G8 at the same time; the gate scan signals are received at the same time by G9, G10, G11, and G12. Similarly, for the whole array substrate, when the forward scanning is adopted, four rows of sub-pixels sequentially arranged from top to bottom are simultaneously turned on, and at the moment, data signals received by four sub-pixels positioned in the same column in the four rows of sub-pixels are the same, so that the same gray scale is displayed. Thus, the display device having the gate driver circuit has a resolution of 2K, which is a quarter of the intrinsic resolution 8K.

Alternatively, for example, to further reduce the resolution, when the resolution displayed by the display device is switched from 2K to HD, the method for driving the gate driving circuit includes: the width of the signal output end of the start signal end STV is adjusted, as shown in fig. 8, the width of the signal output end of the start signal end STV is 12H, and at this time, signals output by the first signal output ends OUT of the shift register units connected to six rows of gate lines adjacent in sequence have an overlapping portion.

For example, signals output by the first signal output terminal OUT1 of the first shift register unit SR1, the first signal output terminal OUT2 of the first shift register unit SR2, the first signal output terminal OUT3 of the third shift register unit SR3, the fourth shift register unit SR4, the first signal output terminal OUT5 of the fifth shift register unit SR5, and the first signal output terminal OUT6 of the sixth shift register unit SR6 have overlapping portions. Signals output by the first signal output terminal OUT7 of the seventh shift register unit SR7, the first signal output terminal OUT8 of the eighth shift register unit SR8, the first signal output terminal OUT9 of the ninth shift register unit SR9, the first signal output terminal OUT10 of the tenth shift register unit SR10, the first signal output terminal OUT11 of the eleventh shift register unit SR11, and the first signal output terminal OUT12 of the twelfth shift register unit SR12 have overlapping portions. The signals output by the first signal output ends OUT of the sequentially adjacent shift register units in the remaining drive groups 01 are the same as those described above, and are not described in detail herein.

In this case, the first system clock signal terminal CLK1, the second system clock signal terminal CLK2, the third system clock signal terminal CLK3, the fourth system clock signal terminal CLK4, the fifth system clock signal terminal CLK5, and the sixth system clock signal terminal CLK6 input the same signal; the seventh system clock signal terminal CLK7, the eighth system clock signal terminal CLK8, the ninth system clock signal terminal CLK9, the tenth system clock signal terminal CLK10, the eleventh system clock signal terminal CLK11, and the twelfth system clock signal terminal CLK12 input the same signals.

In this case, the overlapped part can be intercepted by the first control signal terminal CN1 and OUTPUT through the second signal OUTPUT terminals OUTPUT of the respective shift register units, so that the signals input by the second signal OUTPUT terminals OUTPUT of the six shift register units sequentially adjacent to each other in the same driving group 01 are the same. For example, the signals input by the second signal OUTPUT terminal OUTPUT1 of the first shift register unit SR1, the second signal OUTPUT terminal OUTPUT2 of the second shift register unit SR2, the second signal OUTPUT terminal OUTPUT3 of the third shift register unit SR3, the second signal OUTPUT terminal OUTPUT4 of the fourth shift register unit SR4, the second signal OUTPUT terminal OUTPUT5 of the fifth shift register unit SR5, and the second signal OUTPUT terminal OUTPUT6 of the sixth shift register unit SR6 are the same. The signals input by the second signal OUTPUT terminal OUTPUT7 of the seventh shift register unit SR7, the second signal OUTPUT terminal OUTPUT8 of the eighth shift register unit SR8, the second signal OUTPUT terminal OUTPUT9 of the ninth shift register unit SR9, the second signal OUTPUT terminal OUTPUT10 of the tenth shift register unit SR10, the second signal OUTPUT terminal OUTPUT11 of the eleventh shift register unit SR11, and the second signal OUTPUT terminal OUTPUT12 of the twelfth shift register unit SR12 are the same. The signals input by the second signal OUTPUT terminals OUTPUT of the four sequentially adjacent shift register units in the remaining driving group 01 are the same as those described above, and are not described again.

In this case, taking the driving group 01 connected to the gate lines (G1-G12) as an example, the gate lines G1, G2, G3, G4, G5, and G6 receive the gate scan signals at the same time; the gate scan signals are simultaneously received by G7, G8, G9, G10, G11, and G12. Similarly, for the whole array substrate, when the forward scanning is adopted, six rows of sub-pixels sequentially arranged from top to bottom are simultaneously turned on, and at the moment, the data signals received by six sub-pixels positioned in the same column in the six rows of sub-pixels are the same, so that the same gray scale is displayed. Thus, the display device with the gate driving circuit has HD resolution.

An embodiment of the invention provides a display device, which includes the gate driving circuit. The display device has the same structure and beneficial effects as the gate driving circuit provided by the previous embodiment. Since the foregoing embodiments describe the structure and beneficial effects of the gate driving circuit in detail, no further description is provided herein.

It should be noted that, in the embodiment of the present invention, the display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device, and for example, the display device may be any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A shift register unit is characterized by comprising a pull-up control module, a pull-up module, an output width control module, a pull-down control module, a first pull-down module and a second pull-down module;

the pull-up control module is connected with a clock signal end, a first signal input end, a second signal input end and a pull-up node; the pull-up control module is used for outputting signals of the first signal input end and the second signal input end to the pull-up node under the control of the clock signal end;

the pull-up module is connected with the pull-up node, the first voltage end and the first signal output end; the pull-up module is used for outputting the voltage of the first voltage end to the first signal output end under the control of the pull-up node;

the output width control module is connected with the first signal output end, the first control signal end, the grounding end and the second signal output end; the output width control module is used for intercepting part of signals of the first signal output end and outputting the part of signals to the second signal output end under the control of the first control signal end and the grounding end;

the pull-down control module is connected with the first signal input end, the clock signal end, the pull-down node and the second voltage end, and the pull-down control module is used for pulling down the potential of the pull-down node to the voltage of the second voltage end under the control of the first signal input end, or outputting the voltage of the clock signal end to the pull-down node under the control of the clock signal end;

the first pull-down module is connected with the pull-down node, the pull-up node, the first signal output end and the second voltage end; the first pull-down module is used for respectively pulling down the potentials of the pull-up node and the first signal output end to the potential of the second voltage end under the control of the pull-down node;

the second pull-down module is connected with a second control signal end, a second voltage end and a second signal output end; the second pull-down module is configured to pull down the potential of the second signal output terminal to the potential of the second voltage terminal under the control of the second control signal terminal.

2. The shift register cell of claim 1, wherein the pull-up control module comprises: a first transistor and a first capacitor;

the grid electrode of the first transistor is connected with the clock signal end, the first pole of the first transistor is connected with the first signal input end, and the second pole of the first transistor is connected with the pull-up node;

one end of the first capacitor is connected with the second signal input end, and the other end of the first capacitor is connected with the pull-up node.

3. The shift register cell of claim 1, wherein the pull-up module comprises:

and the grid electrode of the second transistor is connected with the pull-up node, the first pole of the second transistor is connected with the first voltage end, and the second pole of the second transistor is connected with the first signal output end.

4. The shift register cell of claim 1, wherein the output width control module comprises: a third transistor and a second capacitor;

the grid electrode of the third transistor is connected with a first control signal end, the first pole of the third transistor is connected with the second signal output end, and the second pole of the third transistor is connected with the first signal output end;

one end of the second capacitor is connected with the first signal output end, and the second pole of the second capacitor is connected with the grounding end.

5. The shift register cell of claim 1, wherein the pull-down control module comprises: a fourth transistor and a fifth transistor;

the grid electrode and the first electrode of the fourth transistor are connected with the clock signal end, and the second electrode of the fourth transistor is connected with the pull-down node;

the grid electrode of the fifth transistor is connected with the first signal input end, the first pole of the fifth transistor is connected with the pull-down node, and the second pole of the fifth transistor is connected with the second voltage end.

6. The shift register cell of claim 1, wherein the first pull-down module comprises: a sixth transistor and a seventh transistor;

a grid electrode of the sixth transistor is connected with the pull-down node, a first pole of the sixth transistor is connected with the pull-up node, and a second pole of the sixth transistor is connected with the second voltage end;

the gate of the seventh transistor is connected to the pull-down node, the first pole of the seventh transistor is connected to the first signal output terminal, and the second pole of the seventh transistor is connected to the second voltage terminal.

7. The shift register cell of claim 1, wherein the second pull-down module comprises:

and the grid electrode of the eighth transistor is connected with the second control signal end, the first pole of the eighth transistor is connected with the second signal output end, and the second pole of the eighth transistor is connected with the second voltage end.

8. A gate driving circuit for outputting a scan signal to a gate line; a shift register unit according to any one of claims 1 to 7, comprising a plurality of cascaded shift register cells;

a first signal input end of the first-stage shift register unit is connected with an initial signal end; except the first-stage shift register unit, the first signal input ends of the other shift register units are connected with the first signal output end of the first-stage shift register unit; the second signal input end of the last stage of shift register unit is connected with the initial signal end; except the last stage of shift register unit, the second signal input ends of the other shift register units are connected with the first signal output end of the next stage of shift register unit; the second signal output end of each stage of shift register unit is connected with a grid line;

each twelve sequentially cascaded shift register units form a driving group; the driving group comprises a first shift register unit, a second shift register unit, a third shift register unit, a fourth shift register unit, a fifth shift register unit, a sixth shift register unit, a seventh shift register unit, an eighth shift register unit, a ninth shift register unit, a tenth shift register unit, an eleventh shift register unit and a twelfth shift register unit which are sequentially cascaded;

a first control signal end and a second control signal end of the first shift register unit are respectively connected with a first system clock signal end and a seventh system clock signal end;

the first control signal end and the second control signal end of the second shift register unit are respectively connected with the second system clock signal end and the eighth system clock signal end;

the first control signal end and the second control signal end of the third shift register unit are respectively connected with a third system clock signal end and a ninth system clock signal end;

a first control signal end and a second control signal end of the fourth shift register unit are respectively connected with a fourth system clock signal end and a tenth system clock signal end;

a first control signal end and a second control signal end of the fifth shift register unit are respectively connected with a fifth system clock signal end and an eleventh system clock signal end;

a first control signal end and a second control signal end of the sixth shift register unit are respectively connected with a sixth system clock signal end and a twelfth system clock signal end;

a first control signal end and a second control signal end of the seventh shift register unit are respectively connected with a seventh system clock signal end and a first system clock signal end;

a first control signal end and a second control signal end of the eighth shift register unit are respectively connected with an eighth system clock signal end and a second system clock signal end;

a first control signal end and a second control signal end of the ninth shift register unit are respectively connected with a ninth system clock signal end and a third system clock signal end;

a first control signal end and a second control signal end of the tenth shift register unit are respectively connected with a tenth system clock signal end and a fourth system clock signal end;

a first control signal end and a second control signal end of the eleventh shift register unit are respectively connected with an eleventh system clock signal end and a fifth system clock signal end;

and a first control signal end and a second control signal end of the twelfth shift register unit are respectively connected with a twelfth system clock signal end and a sixth system clock signal end.

9. A method for driving the gate drive circuit of claim 8, the method comprising: signals input by any two system clock signal ends connected with the same driving group are different;

or,

when the width of the signal output end of the initial signal end is 4H, the same signal is input into the first system clock signal end and the second system clock signal end; the same signal is input into a third system clock signal end and a fourth system clock signal end; the same signal is input into a fifth system clock signal end and a sixth system clock signal end; the seventh system clock signal end and the eighth system clock signal end input the same signal; the ninth system clock signal end and the tenth system clock signal end input the same signal; the eleventh system clock signal end and the twelfth system clock signal end input the same signal;

or,

when the width of the output signal end of the initial signal end is 8H, the same signal is input into the first system clock signal end, the second system clock signal end, the third system clock signal end and the fourth system clock signal end; inputting the same signals into a fifth system clock signal terminal, a sixth system clock signal terminal, a seventh system clock signal terminal and an eighth system clock signal terminal; the ninth system clock signal end, the tenth system clock signal end, the eleventh system clock signal end and the twelfth system clock signal end input the same signal;

or,

when the width of the signal output end of the initial signal end is 12H, the same signals are input into the first system clock signal end, the second system clock signal end, the third system clock signal end, the fourth system clock signal end, the fifth system clock signal end and the sixth system clock signal end; inputting the same signals into a seventh system clock signal end, an eighth system clock signal end, a ninth system clock signal end, a tenth system clock signal end, an eleventh system clock signal end and a twelfth system clock signal end;

wherein, H is a ratio of the scanning time of one image frame to the total number of the grid lines.

10. A display device comprising the gate driver circuit according to claim 8.