CN106464260B - For generating the circuit of accurate clock phase signal for High Speed Serialized device/deserializer - Google Patents
For generating the circuit of accurate clock phase signal for High Speed Serialized device/deserializer Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Disclose the system and method for generating the clock phase signal with exact timing relationship.For example, the clock signal at four 90 degree of intervals can be generated from difference CML clock signal.Difference CML clock signal is converted into difference cmos clock signal and provides duty cycle correction by CML to CMOS converter.Delay cell generates delayed clock signal from difference cmos clock signal.The difference cmos clock signal and delayed clock signal are logically combined to generate four four points of clock signals of the active time with a quarter clock cycle.Set-reset latch produces four clock signals from Zhu Sifen clock signal.Calibration module control delay cell postpones and controls the duty cycle correction of CML to CMOS converter to adjust the timing relationship of this four clock signals.This four clock signals can be used in such as deserializer.
Description
Background
Field
The present invention relates to electronic circuits, and the electronics of accurate clock phase signal is more particularly, to generated for high speed SERDES
Circuit.
Background technique
Sustainable growth is used to high-speed serial communication link in electronic system.High-speed serial communication link can be according to various
(such as universal serial bus (USB), high-definition media interface (HDMI), serial advanced technology attachment connect (SATA), Yi Jigao to standard
Fast peripheral component interconnection (PCIe) interface) it operates.Serialiser/deserializer (SERDES) be used for from serial communication link into
Row transmission and reception.SERDES generally executes its function using multiple clock signals.Such as interval four can be used in SERDES
Four clock signals of/mono- clock cycle.If clock signal does not have accurate relationship, then the performance of SERDES can
It can be downgraded.For example, the timing of mismatch may cause the mistake in the data received between clock signal.
It summarizes
On the one hand, the circuit for generating four clock signals with exact timing relationship is provided.The circuit
Include: current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter, is configured to believe on CML clock
Number differential pair is converted into cmos clock signal differential pair, and wherein CML to CMOS converter includes duty cycle correction function, the function
Control the duty ratio (score that period signal is the high clock cycle) of cmos clock signal differential pair；Delay phase-locked loop module,
It is configured to from cmos clock signal differential to four clock signals of generation；And calibration module, it is configured to control delay lock
Phase ring moulds block postpones and controls the duty cycle correction of CML to CMOS converter to adjust the timed-shutoff of four clock signals
System.
On the one hand, the method for generating four clock signals with exact timing relationship is provided.This method packet
It includes: by the logic level transition of CML clock signal difference pair at cmos clock signal differential pair, including adjusting cmos clock signal
The duty ratio of differential pair；Postpone each signal of cmos clock signal differential centering to generate delayed clock signal；Combination
Cmos clock signal differential to delayed clock signal to generate four clock signals；And calibration cmos clock signal difference
Point pair duty cycle adjustment and delayed clock signal delay to adjust the timing relationships of four clock signals.
On the one hand, the equipment for generating four clock signals with exact timing relationship is provided.The equipment packet
It includes: for by CML clock signal difference, to the device for being converted into cmos clock signal differential pair, which to include when controlling CMOS
The duty cycle correction function of the duty ratio of clock signal differential pair；For from cmos clock signal differential to generate four clock signals
Device, the generation include postpone the centering of cmos clock signal differential each signal；And for calibrating four clock signals
Timing relationship device, the calibration include control delay the centering of cmos clock signal differential each signal delay and control
Duty cycle correction function processed.
Other features and advantages of the present invention will become from by example being described below for aspects of the present invention of explanation
It is illustrated.
Brief description
Details (for its structurally and operationally the two) of the invention can by studying appended attached drawing come portion collection,
In similar appended drawing reference refer to similar part, and wherein:
Fig. 1 is the functional block diagram of deserializer；
Fig. 2 is the functional block diagram of previous deserializer；
Fig. 3 is the functional block diagram according to the deserializer of presently disclosed embodiment；
Fig. 4 is the delay phase-locked loop mould that can be used to realize the deserializer of Fig. 3 according to presently disclosed embodiment
The functional block diagram of the circuit of block and calibration module；
Fig. 5 is the waveform diagram of the operation of the circuit of key diagram 4；
Fig. 6 is the schematic diagram according to the delay cell of presently disclosed embodiment；
Fig. 7 is the waveform diagram of the operation of the delay cell of key diagram 6；
Fig. 8 is the schematic diagram according to CML to the CMOS converter of presently disclosed embodiment；
Fig. 9 is the schematic diagram according to the comparator of presently disclosed embodiment；And
Figure 10 is according to presently disclosed embodiment for generating four clock signals with exact timing relationship
Process flow chart.
Detailed description
The following detailed description of the drawings is intended as the description to various configurations, and is not intended to indicate to practice this
Only configuration of concept described in text.This detailed description includes detail in order to provide the thorough reason to each conception of species
Solution.However, it will be apparent to those skilled in the art that, these concepts can be practiced without these specific details.?
In some examples, well known structure and component are shown in simplified form to avoid falling into oblivion this genus.
Fig. 1 is the functional block diagram of deserializer (also referred to as clock and data recovery circuit or CDR).The deserializer is " half
Rate " design, wherein the frequency for the clock signal in the deserializer is the half of data transfer rate.It includes data that deserializer, which receives,
The serial data signal RX serially flowed.Each bit in serial data stream crosses over the time zone for being referred to alternatively as bit-time
Between.Deserializer operation for from serial data signal restore data and restore designation date timing clock signal.
Deserializer includes the variable gain amplifier 102 of the amplitude of the adjustable signal received.Variable gain amplification
The output of device 102 is received by balanced device 104, the balanced device 104 can with balanced reception to signal depend on frequency to compensate
Loss.Sampler module 111 to carry out to through amplifying with balanced signal twice (per clock cycle four times) with every bit-time
Sampling.The timing of sampling is based on the clock signal received from phase interpolator 121.
Nominally phase interpolator 121 generates four clock signals at interval 90 degree (a quarter clock cycle).When
Clock signal can be referred to as 0,90,180,270 degree of clock signal according to their relative timing.Phase interpolator 121 by
Clock signal is generated with mutually interpolation is carried out between quadrature clock signal (for example, receiving phase locked loop).Same phase (I) and orthogonal
(Q) clock signal is each differential signal that quadrature clock signal shifts 90 degree from in-phase clock signal.
Deserializer is using loop filter 131 for Timed Recovery.Loop filter 131 provides control phase interpolator
The digital signal of 121 phase.The operation of loop filter 131 is to be placed on the data received for 0 degree and 180 degree clock signal
Bit-time center, and 90 degree and 270 degree of clock signals are placed on to the edge of the bit-time of the data received.
0 degree can be subsequently used to sample the data-signal received to generate the data restored with 180 degree clock signal.90
Degree and 270 degree of clock signals can also be used to sample the data-signal received.All samplings can be by loop
Filter 131 is used for Timed Recovery.
Data sampling from sampler module 111 is converted into parallel lattice from serial form by data deserializer module 141
Formula.For example, the data-signal of 0 degree and 180 degree clock signal samples received can be applied in combination in data deserializer module 241
Five groups of samplings with generate 10 bit parallels output (DATA).
Fig. 2 is the functional block diagram of previous deserializer.The deserializer of Fig. 2 and the deserializer of Fig. 1 are similar, wherein in addition to being retouched
Other than the difference stated, the element of similar label is operated in a similar way.
The deserializer of Fig. 2 includes multiphase filter 220 come when being filtered, and improving to same phase and quadrature clock signal
The relative timing of clock phase.Two phase interpolators 221, signal of 222 interpolations from multiphase filter.Phase interpolator interpolation
It 90 degree of phase and is controlled at interval by digital loop filters 231.Each phase interpolator generates an output signal difference
It is right.Output signal differential pair from first phase interpolater 221 is used to generate 0 degree and 180 degree clock signal.From second
The output signal differential pair of phase interpolator 222 is used to generate 90 degree and 270 degree of clock signals.231 sum number of loop filter
Loop filter 131 can be similar to according to deserializer module 241 and data deserializer module 141 is operated.
Multiphase filter and phase interpolator use current mode logic (CML).Each phase interpolator is followed by the future
CML to the CMOS converter 225,226 of cmos clock signal is converted into from the CML clock signal of phase interpolator.CML signal is
Differential signal with the voltage swing for being less than associated supply voltage.Cmos signal generally has equal to associated power supply
The voltage swing (also referred to as track to track) of voltage.Cmos clock signal is used in sampler module 211 with to receiving
Data-signal is sampled.
The source of phase error between cmos clock signal includes mismatch in two phase interpolators, with mutually and orthogonal
Mismatch (this can substantially be reduced by multiphase filter, but only in narrow-band) and CML to CMOS in clock signal
Mismatch and deflection in converter.Additionally, phase interpolator and CML to CMOS converter can take up a large amount of integrated circuit faces
It accumulates and there is high power consumption.Multiphase filter can aggravate this problem by decaying with phase and quadrature clock signal.
Fig. 3 is the functional block diagram according to the deserializer of presently disclosed embodiment.The deserializer of Fig. 3 and unstringing for Fig. 1
Device is similar, wherein the element of similar label is operated in a similar way other than described difference.With the solution of Fig. 2
Device go here and there on the contrary, the deserializer of Fig. 3 executes clock phase signal without using multiphase filter and generates, and a phase interpolation is used only
Device (and CML to a CMOS converter is used only).
Deserializer generates the CML clock letter come from same phase and quadrature clock signal interpolation using phase interpolator 321
Number differential pair.The component signal of signal differential pair can be referred to as positive signal and negative signal.In the fig. 3 embodiment, in same phase
There is no multiphase filter between quadrature clock signal and phase interpolator, thus deserializer can operate on wide frequency range.
Phase interpolator 321 is based on being inserted into a phase in the phase control signal for carrying out loop filter 331.Phase interpolator 321 connects
It receives and generates CML signal.CML to CMOS converter 325 is by the CML clock signal difference from phase interpolator 321 to conversion
At cmos clock signal differential to (complementation)CML to CMOS converter 325 includes duty cycle correction (DCC)
Function.Duty cycle correction function is used to adjust for cmos clock signal differential pair, so that the edge interval 180 degree of the signal.
From CML to CMOS, converter 325 receives cmos clock signal differential pair to delay phase-locked loop (DLL) module 355, and
0,90,180 and 270 degree of clock signal (Φ 0, Φ 90, Φ 180, Φ 270) is generated using delay cell (or delay line).This
A little 0,90,180 and 270 degree of clock signals are by sampler module 311 for timing.In the data-signal received in sampler mould
By before sampling in block 311, it can be amplified by variable gain amplifier 302 and equilibrium is carried out by balanced device 304.It is receiving
Data-signal sampled after, sampling from serial form can be converted into parallel form by data deserializer module 341.Accordingly
Ground, these 0,90,180 and 270 degree of clock signal can be referred to as sampled clock signal.DLL module 355 also create instruction 0,
90, the error signal (Errors) of the error in the relative timing of 180 and 270 degree of clock signals.
Calibration module 359 receives error signal from DLL module 355.It 359 assessment errors signal of calibration module and is arrived for CML
CMOS converter 325 and for DLL module 355 generate control signal.CML to CMOS converter 325 is gone to from calibration module 359
DCC control signal (DCC_code) be used to adjust duty cycle correction.Go to the delayed control signal of DLL module 355
(Delay_code) it is used to adjust the delay of delay cell.In various embodiments, calibration module 359 can produce multiple
DCC controls signal and can produce multiple delayed control signals.
The deserializer of Fig. 3 can have multiple benefits better than existing deserializer.Calibration module 359 can be used in deserializer
It improves the timing of sampled clock signal and improves the performance of deserializer whereby, such as improve the timing ampleness of deserializer.Calibration
Module 359 can correct the same phase from PLL and the mismatch between quadrature clock signal, correct in the clock signal from PLL
Duty cycle error and correcting circuit mismatch and the variation with technique, voltage and temperature.There is no more in the deserializer of Fig. 3
Phase filter can permit deserializer and be operated on the data transfer rate of wide scope.
Additionally, the deserializer of Fig. 3 also occupies less integrated circuit area than existing deserializer and consumes less function
Rate.Further, calibration module 359 is digitally operated and deserializer is allowed to have less critical analog circuit, this
It can improve to manufacture and simplify and design is transferred to novel technique.Additionally, calibration module 359 can be by saving number
Word controlling value and on startup these heavily loaded values provide quick start.
Fig. 4 is the DLL module and calibration that can be used to realize the deserializer of Fig. 3 according to presently disclosed embodiment
The functional block diagram of the circuit of module.From CML to CMOS, converter 325 receives difference cmos clock signal to (positive clock is believed to circuit
Number " Clock " and negative clock signal " Clockb ").Positive clock signals are postponed delayed to generate by the first delay cell 411
Positive clock signals " Clock_del ".Negative clock signal is postponed by the second delay cell 412 to generate delayed negative clock signal
"Clockb_del".The delay of delay cell is adjusted by calibration module with the delay with a quarter clock cycle.
420 logical combination positive clock signals of logic circuitry, negative clock signal, delayed positive clock signals and through prolonging
Slow negative clock signal is to generate four four points of clock signals.Positive clock signals pass through first and door 421 and delayed timing
Clock signal covers capable and operation to generate the one or four point of clock signal " Q1 ".Delayed positive clock signals pass through second and door
422 cover capable and operation with negative clock signal to generate the two or four point of clock signal " Q2 ".Negative clock signal by third with
Door 423 covers capable and operation with delayed negative clock signal to generate the three or four point of clock signal " Q3 ".Delayed is negative
Clock signal covers capable and operation with door 424 and positive clock signals by the 4th to generate the four or four point of clock signal " Q4 ".
Four points of clock signals are high (active) for a quarter clock cycle, and are for the remaining clock cycle
It is low.One or four point of clock signal is height for the first a quarter clock cycle.Two or four point of clock signal is from the one or four timesharing
Clock signal delay reaches a quarter clock cycle.Three or four point of clock signal from the two or four point of clock signal delay up to four/
One clock cycle.Four or four point of clock signal reaches a quarter clock cycle from the three or four point of clock signal delay.These
After timing relationship is calibration, and there may be small error (for example, 1%) in timing relationship.
Two set-reset latch are based on Zhu Sifen clock signal and produce 0,90,180 and 270 degree of clock signal.The
One set-reset latch 461 has the set input (S) for being connected to the one or four point of clock signal, and by the one or four point
Clock signal set, and (R) is inputted with the reset for being connected to the three or four point of clock signal, and by the three or four timesharing clock
Signal resets.The true output (Q) of first set-reset latch 461 provides 0 degree of clock signal, and mends outputIt mentions
180 degree clock signal is supplied.Second set-reset latch 462 has the set input for being connected to the two or four point of clock signal
(S), and by the two or four timesharing clock home position signal, and there is the reset input (R) for being connected to the four or four point of clock signal,
And it is resetted by the four or four point of clock signal.The true output (Q) of second set-reset latch 462 provides 90 degree of clocks
Signal, and mend outputProvide 270 degree of clock signals.Set-reset latch has small delay, and in delay
Mismatch also can be small.The calibration of four points of clock signals will will lead to the accurate school of 0,90,180,270 degree of clock signal as a result,
It is quasi-.
Fig. 5 is the waveform diagram of the operation of the circuit of key diagram 4.At the time 501, positive clock signals rise, and negative clock
Signal decline.After the time 501 soon, the one or four point of clock signal rises and the four or four point of clock signal declines.Herein it
Afterwards soon, based on the first set-reset latch 461 by the one or four timesharing clock home position signal, 0 degree of clock signal rising and 180
Spend clock signal decline.From the transformations for being converted to the one or four point of clock signal and the two or four point of clock signal of positive clock signals
Delay is used for the switching of logic circuitry 420.From 0 degree and the 180 degree clock signal of being converted to of the one or four point of clock signal
The delay of transformation is used for the switching of the first set-reset latch 461.
At the time 502, delayed negative clock signal decline.The decline of negative clock signal and delayed negative clock are believed
Number decline between delay be the second delay cell 412 delay.Because the decline of delayed negative clock signal does not cause
0, the transformation of 90,180 or 270 degree of clock signals, so the delay is not crucial for the performance of circuit.
At the time 503, delayed positive clock signals rise.The rising of positive clock signals and delayed positive clock are believed
Number rising between delay be the first delay cell 411 controlled delay.After the time 503 soon, the one or four timesharing clock
Signal decline and the four or four point of clock signal rising.After this soon, based on the first set-reset latch 462 by first
Four timesharing clock home position signals, 90 degree of clock signals rise and 270 degree of clock signal declines.From the transformation of delayed positive clock signals
The switching of logic circuitry 420 is used for the delay of the transformation of the one or four point of clock signal and the two or four point of clock signal.From
The delay of the transformation for being converted to 90 degree and 270 degree clock signals of two or four point of clock signal is used for the second set-reset latch
The switching of device 462.
At the time 505, positive clock signals decline, and negative clock signal rises.After the time 505 soon, the 2nd 4
Divide clock signal decline and the three or four point of clock signal rises.After this soon, it is based on the first set-reset latch 461
It is resetted by the three or four point of clock signal, 0 degree of clock signal decline and the rising of 180 degree clock signal.From the transformation of negative clock signal
The switching of logic circuitry 420 is used for the delay of the transformation of the two or four point of clock signal and the three or four point of clock signal.From
The delay of the transformation for being converted to 0 degree and 180 degree clock signal of three or four point of clock signal is used for the first set-reset latch
461 switching.
At the time 506, delayed positive clock signals decline.The decline of positive clock signals and delayed positive clock are believed
Number decline between delay be the first delay cell 411 delay.Because the decline of delayed positive clock signals does not cause
0, the transformation of 90,180 or 270 degree of clock signals, so the delay is not crucial for the performance of circuit.
At the time 507, delayed negative clock signal rises.The rising of negative clock signal and delayed negative clock are believed
Number rising between delay be the second delay cell 412 controlled delay.After the time 507 soon, the three or four timesharing clock
Signal decline and the four or four point of clock signal rising.After this soon, based on the second set-reset latch 462 by the 4th
Four points of clock signals reset, 90 degree of clock signal declines and 270 degree of clock signals risings.From the transformation of delayed negative clock signal
The switching of logic circuitry 420 is used for the delay of the transformation of the three or four point of clock signal and the four or four point of clock signal.From
The delay of the transformation for being converted to 90 degree and 270 degree clock signals of four or four point of clock signal is used for the second set-reset latch
The switching of device 462.
At the time 509, positive clock signals rise again, and negative clock signal declines again.Another clock cycle starts
And it repeats for the described transformation of time 501.
It is referred to as distance A (TA) from 0 degree of clock signal to the time delay of 90 degree of clock signals；From 90 degree of clock signals to
The time delay of 180 degree clock signal is referred to as distance B (TB)；Time from 180 degree clock signal to 270 degree of clock signals prolongs
It is referred to as distance C (TC) late；And from 270 degree of clock signals to the time delay of (following clock cycle) 0 degree of clock signal
Referred to as distance D (TD).
Fig. 4 is returned, provides clock phase signal using three control loops of three comparators and three integrators
Calibration.These control loops use four points of clock signals of low-pass filtered version.First low-pass filter 431 is by the one or four point
Clock signal filtering；Second low-pass filter 432 filters the two or four point of clock signal；Third low-pass filter 433 is by third
Four points of clock signal filtering；And the 4th low-pass filter 434 the four or four point of clock signal is filtered.In the embodiment of Fig. 4
Low-pass filter uses resistor-capacitor circuit (RC) filter.Four points of low-pass filtered clock signals will be supply voltage
About a quarter；For example, low-pass filtered signal will be about 250mV when with 1V power supply.
First control loop adjusts the delay of the first delay cell 411.First control loop includes 441 He of first comparator
First integrator 451.More low-pass filtered the one or the four point of clock signal and low-pass filtered second of first comparator 441
Four points of clock signals.The one or four point of low-pass filtered clock signal is proportional to timing distance A (TA in Fig. 5).Through low pass
Two or four point of clock signal of filtering is proportional to timing distance B (TB in Fig. 5).Result from first comparator 441 refers to
Show whether the one or four point of low-pass filtered clock signal is greater than the two or four point of low-pass filtered clock signal, this indicates
Whether timing distance A is greater than timing distance B.
Comparison signal from first comparator 441 is interpreted as the error signal (example of symbol by first integrator 451
Such as ,+1, -1) and integral is carried out to error signal and thinks that the first delay cell 411 generates delay control Delay_code_1.Cause
Pass through first comparator when the one or four timesharing clock signal terminates and the two or four point of clock signal starts for the first delay cell 411
441, first integrator 451 adjusts the first control loop, and the first delay cell 411 adjusts delay so that timing distance A
It is equal with timing distance B.
Second control loop adjusts the delay of the second delay cell 412.Second control loop includes 442 He of the second comparator
Second integral device 452.More low-pass filtered the three or the four point of clock signal and the low-pass filtered the 4th of second comparator 442
Four points of clock signals.The three or four point of low-pass filtered clock signal is proportional to timing distance C (TC in Fig. 5).Through low pass
Four or four point of clock signal of filtering is proportional to timing distance D (TD in Fig. 5).Result from the second comparator 442 refers to
Show whether the three or four point of low-pass filtered clock signal is greater than the four or four point of low-pass filtered clock signal, this indicates
Whether timing distance C is greater than timing distance D.
Second integral device 452 by the comparison signal from the second comparator 442 be interpreted as symbol error signal and
Integral is carried out to error signal and thinks that the second delay cell 412 generates delay control Delay_code_2.Because the second delay is single
Member 412 passes through the second comparator 442, second integral when the three or four timesharing clock signal terminates and the four or four point of clock signal starts
Device 452 adjusts the second control loop, and the second delay cell 412 adjusts delay so that timing distance C and timing distance D phase
Deng.
The DCC of third control loop adjusting CML to CMOS converter 325.Third control loop includes third comparator 443
With third integral device 453.The two or four point of more low-pass filtered clock signal of third comparator 443 and low-pass filtered
Four or four points of clock signals.The two or four point of low-pass filtered clock signal is proportional to timing distance B (TB in Fig. 5).Through low
Four or four point of clock signal of pass filter is proportional to timing distance D (TD in Fig. 5).Result from third comparator 443
Indicate whether the two or four point of low-pass filtered clock signal is greater than the four or four point of low-pass filtered clock signal, this instruction
Whether timing distance B is greater than timing distance D.
Comparison signal from third comparator is interpreted as the error signal of symbol by third integral device 453, and right
Error signal is integrated to generate DCC control signal (DCC_code), to adjust from CML to CMOS converter 325
Duty ratio of the cmos clock signal differential to (Clock, Clockb).Because the DCC control of CML to CMOS converter 325 is the
When three or four points of clock signals start (when the two or four timesharing clock signal terminates) and start in the one or four point of clock signal (when the four or four
At the end of timesharing clock signal) when third control loop adjusted by third comparator 443, third integral device 453, and CML is arrived
CMOS converter 325 adjusts duty ratio so that timing distance B is equal with timing distance D.
First control loop operates such that timing distance A is equal to timing distance B；Second control loop operates such that fixed
When distance C be equal to timing distance D；And third control loop operates such that timing distance B is equal to timing distance D.By passing
It combines Deng, control loop so that all timings are equidistant.Because the summation of four timing distances is equal to a clock week
Phase, so each timing distance is equal to a quarter clock cycle.This four clock signals can have 90 degree opposite as a result,
Phase.
Comparator 431,432,433 carries out clock timing by calibration clock signal Cal_clock.Comparator is in calibration
More their own input signal in each circulation of clock signal.Integrator 451,452,453 also by calibration clock signal into
Row clock timing.Integrator integrate to the error signal from comparator and can be in each circulation of calibration clock signal
It is upper to update their own control output.In the deserializer for receiving 10GHz data transfer rate, calibration control signal be can be for example
19.2MHz signal.Other frequencies can also be used.Because calibration is held with tracking the effect slowly changed (such as, temperature)
The rate of row calibration does not need very high.Additionally, calibration clock signal can with CML clock signal difference to (and other when
Clock signal) it is asynchronous.
CML to CMOS converter 325 and DLL provided by the circuit of Fig. 4 and digital calibration loop module can be from inputs
Clock signal difference has four clock phase signals of exact timing relationship to generating.Other than the use in deserializer,
Same or similar circuit can be used in other application, such as in serialiser or time-interleaved analog-digital converter.
Fig. 6 is the schematic diagram according to the delay cell of presently disclosed embodiment.Delay cell is used as Fig. 4's
The delay cell 411,412 of circuit.Delay cell is charged and discharged using the single delay-level of controlled capacitors prolongs to generate it
Late.Delay-level includes the phase inverter 631 for driving the output Clock_del of delay cell.
The input Clock_in of delay cell is connected to the grid of p-channel transistor 611.P-channel transistor 611 can fill
When switch and switch can be referred to as.The source electrode of p-channel transistor 611 is connected to supply voltage, and p-channel transistor 611
Drain electrode be connected to the midpoint Mid of delay cell.Midpoint is connected to the input of phase inverter 631.Current-mode digital analog converter 621
Electric current is drawn from the midpoint of delay cell.Capacitor 625 also is included in delay cell.In some embodiments, capacitor
Device is provided by the capacitor (can be referred to as parasitic capacitance) of the other elements of delay cell (for example, the input electricity of phase inverter 631
The capacitor of the cable of appearance, the source capacitance of p-channel transistor 611, the output capacitance of current-mode DAC 621 and midpoint node).
Fig. 7 is the waveform diagram of the operation of the delay cell of key diagram 6.When the input for delay cell is switched to high
It is low that (time 701), the cut-off of p-channel transistor 611 and current-mode DAC 621, which draw midpoint,.When midpoint discharges into phase inverter
When below 631 threshold value (time 702), output is switched to height.
The capacitor for postponing to depend on the electric current and midpoint that current-mode DAC 621 is drawn of midpoint electric discharge is changed.
For the correspondingly proportional to the electric current drawn by DAC by the delay of delay cell of low to high transformation.Current-mode DAC
621 electric current is arranged by delayed control signal DAC_code.Current-mode DAC 621, which is also received, provides reference current or voltage
Bias current signal (Bias).In the DLL module of Fig. 4, the DAC current of the first delay cell 411 is by coming from first integral
The delayed control signal of device 451 is arranged, and the DAC current of the second delay cell 412 is by the delay control from second integral device 452
Signal setting processed.In with the deserializer of 10Gbps data rate operations, DAC current be can be disposed so that in delayed control signal
One LSB changes the change for causing about 1ps in delay.
When the input for delay cell is switched to low (time 703), p-channel transistor 611 is connected and draws midpoint
For height.Due to the electric current from p-channel transistor 611, midpoint can be switched to rapidly height.Midpoint is switched to height and makes phase inverter
631 the output of delay cell is switched to it is low.It, can be correspondingly small by the delay of delay cell for high to Low transformation.
For rising transition and decline transformation, the delay cell of Fig. 6 can have the delay of asymmetric (unequal).Especially
Ground, the delay for declining transformation are heavily dependent on the electric current of p-channel transistor 611, and the delay of rising transition very great Cheng
The electric current of current-mode DAC 621 is depended on degree.In the circuit of Fig. 4, for the delay cell 411,412 for declining transformation
Delay is not crucial.Delay (it is controlled by DAC current) for the delay cell of rising transition is for adjusting clock
The delay of the timing of phase signal.
Fig. 8 is the schematic diagram according to CML to the CMOS converter of presently disclosed embodiment.CML to CMOS converter
It may be used as CML to the CMOS converter 325 in the deserializer of Fig. 3.CML to the CMOS converter of Fig. 8 includes duty cycle correction
Function.The duty cycle correction function is by DCC control signal control.DCC control signal in CML to the CMOS converter of Fig. 8 makes
With there is the amplitude of symbol to indicate.The direction of DCC mark signal (DCC_sign and its benefit DCC_sign_b) control duty cycle correction,
And the amount of DCC amplitude signal DCC_code control duty cycle correction.DCC amplitude signal can be the calibration module from Fig. 4
Third integral device 453 integrated error signal, wherein DCC mark signal is the symbol of integrated error signal.Class
As, when CML to the CMOS converter 325 in deserializer of CML to the CMOS of Fig. 8 converter as Fig. 3, DCC control letter
It number is DCC control signal (DCC_code).
CML to CMOS converter receives a differential CML input signals to (positive input signal INp and negative input signal INm).
When CML to the CMOS converter 325 in deserializer of CML to the CMOS of Fig. 8 converter as Fig. 3, differential CML input signals
Received from phase interpolator 321.Input signal can be amplified in preamplifier 821.The output of preamplifier 821 by
Capacitor 831,851 is capacitively coupled (AC coupling) to self biased amplifier 830,850.Self biased amplifier 830,850 has
There is adjustable DC point.The DC point for adjusting self biased amplifier 830,850 effectively changes threshold level and changes whereby
The duty ratio of CML to CMOS converter.
The output of self biased amplifier 830,850 is buffered the output signal to drive CML to CMOS converter by phase inverter
(cmos clock signal differential is to Clock, Clockb).When in the deserializer that CML to the CMOS converter of Fig. 8 is used as Fig. 3
When CML to CMOS converter 325, output signal is cmos clock signal differential pairIt is supplied to DLL mould
Block 355.Phase inverter 841 drives the positive signal of the cmos clock signal differential pair of the output from the first self biased amplifier 830.
Phase inverter 842 drives the negative signal of the cmos clock signal differential pair of the output from the second self biased amplifier 850.CML is arrived
CMOS converter may include cross-linked 845 He of phase inverter between the positive signal and sub signal of cmos clock signal differential pair
Phase inverter 846.
First self biased amplifier 830 includes the first phase inverter 835；Second self biased amplifier 850 includes the second reverse phase
Device 855.Two resistors in series 833,834 are from the input coupling of the first phase inverter 835 to the output of the first phase inverter 835, and two
A resistors in series 853,854 is from the input coupling of the second phase inverter 855 to the output of the second phase inverter 855.Electric current is supplied
Electric current is drawn to adjust DC point and threshold level in midpoint to resistors in series or the midpoint from resistors in series.
The threshold level of the adjusting self biased amplifier 830,850 of biasing module 810.Biasing module 810 includes being capable of providing
Two current-mode DAC 811,812 of electric current.Biasing module 810 includes the two current-mode DAC that can draw electric current
813,814.Alternatively, single DAC or combination DAC with multiple outputs can be used.
In the embodiment explained, current-mode DAC 811,812 is biased by p offset signal BIASp, and current-mode
DAC13,814 are biased by n offset signal BIASn.Offset signal can be voltage or current reference.It is provided or is drawn by DAC
The level of electric current is controlled by DCC amplitude signal.
Biasing module 810 include four switch with selectively by current-mode DAC be coupled to self biased amplifier 830,
850.When DCC mark signal is timing, current-mode DAC 811 is coupled to the first self biased amplifier by first switch 815
830；When DCC mark signal is negative, current-mode DAC 812 is coupled to the second self biased amplifier by second switch 816
850；When DCC mark signal is negative, current-mode DAC 813 is coupled to the first self biased amplifier by third switch 817
830；And when DCC mark signal is timing, current-mode DAC 814 is coupled to the second automatic biasing and amplified by the 4th switch 818
Device 850.First switch 815 and second switch 816 can be for example realized with p-channel transistor；It can be for example with n-channel crystal
Pipe realizes third switch 817 and the 4th switch 818.
When electric current is supplied to the first self biased amplifier 830 to increase its threshold value by biasing module 810, biasing module
810 also draw electric current from the second self biased amplifier 850 to reduce its threshold value.Which increase the outputs of CML to CMOS converter
The duty ratio of signal.When biasing module 810 draws electric current from the first self biased amplifier 830 to reduce its threshold value, mould is biased
Electric current is also supplied to the second self biased amplifier 850 to increase its threshold value by block 810.This reduce CML to CMOS converters
The duty ratio of output signal.
Fig. 9 is the schematic diagram according to the comparator of presently disclosed embodiment.Comparator is used as the circuit of Fig. 4
In comparator 441,442,443.The comparator of Fig. 9 is the switching capacity type comparator with automatic zero set.It can also be used
Other types of comparator.Comparator receives its two input signals In1 and In2 comparing.Comparator generates instruction, and which is defeated
Enter the bigger output signal Out of signal.Comparator carries out clock timing by two phase signals CK1, CK2.The two clocks
Phase signal is non-overlap.Comparator increases its gain using cascade inverter stage.
During reseting stage, outputting and inputting for the first phase inverter 923 is connected by switch 925, and the second phase inverter
933 output and input is connected by switch 935.Additionally, the first input signal is connected to first capacitor device 921 by switch 911
First terminal, the Second terminal of the first capacitor device 921 is connected to the input of the first phase inverter 923.Second capacitor 931 connects
It connects between the output of the first phase inverter 923 and the input of the second phase inverter 933.Reseting stage is by first capacitor device 921 and
Two capacitors 931 are charged to zero-drift error voltage.
During comparison phase, switch 925, switch 935 and switch 911 are disabled, and switch 912 connects the second input
It is connected to the first terminal of first capacitor device 921.When the second input signal is greater than the first input signal, first capacitor device 921
Voltage on first node will increase during comparison phase.This causes first be amplified by first capacitor device 921
Voltage in the increase and the output of caused first phase inverter 923 of voltage in the input of phase inverter 923 is by a larger margin
Reduction.This by the second capacitor 931 cause the voltage in the input for the second phase inverter 933 being amplified reduction and
The increase still by a larger margin of voltage in the output (output of comparator) of caused second phase inverter 933.When second defeated
When entering signal less than the first input signal, similar still complementary operation has occurred.
Switch 911,912,925,935 can be realized with such as n-channel transistor.These switches can also be brilliant with p-channel
Body pipe or complementary transistor are to realizing.
The comparator of Fig. 9 can realize good accuracy with small integrated circuit area and low-power consumption.For example, comparator
The susceptibility of about 2.5mV may be implemented.For 10GHz deserializer, 2.5mV corresponds to about 1ps variation in clock signal.
Figure 10 is according to presently disclosed embodiment for generating four clock signals with exact timing relationship
Process flow chart.The process can for example using the deserializer of Fig. 3, the circuit of Fig. 4, the delay cell of Fig. 6, Fig. 8 CML
It is realized to the comparator of CMOS converter and Fig. 9.
In step 1010, which converts the logic level of input clock signal, while adjusting converted clock signal
Duty ratio.CML to the CMOS converter of Fig. 8 can for example be used for step 1010 with by CML clock signal difference to being converted into
Cmos clock signal differential pair with calibrated duty ratio.
In step 1020, the converted clock signal of the process lag is to generate delayed clock signal.The two of Fig. 6
A delay cell can be used to for example execute step 1020.
In step 1030, which generates four clock letters based on converted clock signal and delayed clock signal
Number.The logic circuitry 420 and set-reset latch 461,462 of Fig. 4 can for example be used to be based on cmos clock signal
Differential pair and delayed positive and negative clock signal generate four points of clock signals, and are then based on these four points of clock signals
To generate 0,90,180 and 270 degree of clock signal.
In step 1040, which has calibrated four by the delay of the duty ratio and step 1030 of regulating step 1020
The timing relationship of clock signal.Three control loops of Fig. 4 can for example be used to control the first delay cell 411 delay,
The delay of second delay cell 412 and the DCC of CML to CMOS converter 325.
The process of Figure 10 can be for example modified by adding or changing step.For example, interpolations steps can be with interpolation from same
The input clock signal of phase and quadrature clock signal.In addition, all steps can be performed concurrently.
Although the embodiment of the present invention is being described for specific embodiment above, many modifications of the invention
Be it is possible, including the modification for example with unlike signal polarity and transistor types.Additionally, it can be used different from CML
With the technology and signal level of CMOS.Some functions can be deleted；For example, CML to CMOS converter is in one embodiment
Duty ratio can only be adjusted and without level conversion.In addition, being described as the function mobile executed by a module to separately
One module or cross-module distribution.Other variations can produce different number of clock signal, such as eight of 45 degree of interval
Clock signal.In addition, the feature of each embodiment can from be combined in different combination described above.
There is provided front can be made or make to make any person skilled in the art all to the description of the disclosed embodiments
With the present invention.The various modifications of these embodiments will be apparent for a person skilled in the art, and retouched herein
The General Principle stated can be applied to other embodiments without departing from the spirit or scope of the present invention.Therefore, it will be understood that giving herein
Description and attached drawing out indicates currently preferred embodiment of the invention and represents the theme that the present invention widely conceives.It will be into
One step understands that the scope of the present invention is fully contemplated by the other embodiments that can be will be apparent to those skilled in the art, and the present invention
Range it is correspondingly unrestricted except as by the appended claims.
Claims (30)
1. a kind of for generating the circuit of four clock signals with exact timing relationship, the circuit includes:
Current mode logic CML to CMOS converter is configured to CML clock signal difference to being converted into cmos clock signal
Differential pair, wherein CML to the CMOS converter includes the duty ratio for controlling the duty ratio of the cmos clock signal differential pair
Calibration function；
Delay phase-locked loop module is configured to from the cmos clock signal differential to generation four clock signals；And
Calibration module is configured to control the delay of the delay phase-locked loop module and control CML to the CMOS converter
The duty cycle correction to adjust the timing relationships of four clock signals.
2. circuit as described in claim 1, which is characterized in that the delay phase-locked loop module includes:
First delay cell is configured to generate delayed positive clock letter from the positive signal of the cmos clock signal differential pair
Number；
Second delay cell is configured to generate delayed negative clock letter from the negative signal of the cmos clock signal differential pair
Number；
Logic circuitry, be configured to combine the cmos clock signal differential to delayed clock signal to generate tool
There are four four points of clock signals of the active time of a quarter clock cycle；And
Set-reset latch is configured to generate four clock signals from four points of clock signals.
3. circuit as claimed in claim 2, which is characterized in that the logic circuitry includes:
First and door, the positive signal of input coupling to the cmos clock signal differential pair and it is described it is delayed just
The benefit of clock signal, output coupling to the one or four point of clock signal in four points of clock signals；
Second and door, the benefit of the negative signal of input coupling to the cmos clock signal differential pair and described delayed
Positive clock signals, output coupling to the two or four point of clock signal in four points of clock signals；
Third and door, the negative signal of input coupling to the cmos clock signal differential pair and the delayed negative clock
The benefit of signal, output coupling to the three or four sub-signal in four points of clock signals；And
4th and door, the benefit of the positive signal of input coupling to the cmos clock signal differential pair and described delayed
Negative clock signal, output coupling to the four or four point of clock signal in four points of clock signals.
4. circuit as claimed in claim 3, which is characterized in that the set-reset latch includes:
First set-reset latch, set input coupling is to the one or the four point of clock signal, and it resets input coupling
Close the three or the four point of clock signal, and its true output coupling is to the first clock signal in four clock signals,
It mends output coupling to the third clock signal in four clock signals；And
Second set-reset latch, set input coupling is to the three or the four point of clock signal, and it resets input coupling
The four or the four point of clock signal is closed, and the second clock signal in four clock signals is mended in its true output
Output coupling is to the 4th clock signal in four clock signals.
5. circuit as claimed in claim 2, which is characterized in that for raising and lowering change, first delay cell and
Second delay cell has asymmetrical delay.
6. circuit as claimed in claim 2, which is characterized in that each delay cell includes single delay-level.
7. circuit as claimed in claim 6, which is characterized in that the delay-level includes:
P-channel transistor, grid are coupled to a signal of the cmos clock signal differential pair, and source electrode is coupled to power supply electricity
Pressure, and drain and be coupled to the midpoint of the delay-level；
Current-mode digital analog converter is coupled to the midpoint of the delay-level, wherein the current-mode digital-to-analogue conversion
The delay of delay-level described in the current control of device；
Phase inverter, the midpoint of input coupling to the delay-level, and output coupling are to delayed clock signal
Corresponding one.
8. circuit as claimed in claim 2, which is characterized in that the calibration module includes:
Low-pass filter is configured to each of four points of clock signals is filtered and generated four points through filtering
Clock signal；
Comparator is configured to compare four points of clock signals pair through filtering and generates error signal；And
Integrator, is configured to integrate the error signal from the comparator and is controlled with generating control signal
The duty ratio of the delay of first delay cell and second delay cell and CML to the CMOS converter.
9. circuit as claimed in claim 8, which is characterized in that each low-pass filter includes resistor-capacitor circuit filter
Wave device.
10. circuit as claimed in claim 8, it is characterised in that:
First comparator in the comparator connects the first four timesharing through filtering in four through the filtering point clock signal
Clock signal and second four points of clock signals through filtering, and generate the first error signal in the error signal；
First integrator in the integrator receives the first error signal and generates for first delay cell
Delay control；
The second comparator in the comparator receives four points of the third in four through the filtering point clock signal through filtering
Clock signal and the 4th four points of clock signals through filtering, and generate the second error signal in the error signal；
Second integral device in the integrator receives second error signal and generates for second delay cell
Delay control；
Third comparator in the comparator receives the second four points through filtering in four through the filtering point clock signal
Clock signal and the 4th four points of clock signals through filtering, and generate the third error signal in the error signal；
Third integral device in the integrator receives the third error signal and generates and CML to the CMOS is converted
The control of the duty cycle correction function of device.
11. circuit as claimed in claim 8, which is characterized in that the comparator and the integrator are by calibration clock signal
Carry out clock timing, the calibration clock signal and the CML clock signal difference are to being asynchronous.
12. circuit as claimed in claim 8, which is characterized in that the comparator is switched capacitor comparator.
13. circuit as described in claim 1, which is characterized in that CML to the CMOS converter includes:
Self biased amplifier is coupled to input capacitance the CML clock signal difference pair, and its output coupling is described in
Cmos clock signal differential pair,
The wherein threshold level of self biased amplifier described in the duty cycle correction function control.
14. circuit as claimed in claim 13, which is characterized in that each self biased amplifier includes phase inverter, and
The resistors in series being connected between the input of the phase inverter and the output of the phase inverter, and
Wherein the duty cycle correction function is by providing electric current to the midpoint of the resistors in series or from the series resistance
Electric current is drawn to control the threshold level of the self biased amplifier in the midpoint of device.
15. circuit as claimed in claim 14, which is characterized in that further comprise biasing module, the biasing module includes
It is coupled to multiple current-mode digital analog converters at the midpoint of the resistors in series by multiple switch.
16. circuit as claimed in claim 13, which is characterized in that the input of the self biased amplifier passes through preamplifier
It is capacitively coupled to the CML clock signal difference pair.
17. circuit as described in claim 1, which is characterized in that further comprise phase interpolator, be configured to based on phase
It controls signal and generates the CML clock signal difference pair from multiple input clock signals.
18. a kind of deserializer, comprising:
Circuit as claimed in claim 17；
Sampler module is configured to sample serial data signal on the edge of four clock signals；
Loop filter is configured to be described in the phase interpolator generates based on the sampled value from the sampler module
Phase control signal.
19. a kind of method for generating four clock signals with exact timing relationship, which comprises
By the logic level transition of CML clock signal difference pair at cmos clock signal differential pair, including when the adjusting CMOS
The duty ratio of clock signal differential pair；
Postpone each signal of the cmos clock signal differential centering to generate delayed clock signal；Combine the CMOS
Clock signal difference to the delayed clock signal to generate four clock signals；And
Calibrate the duty ratio of the cmos clock signal differential pair adjusting and the delayed clock signal delay with
Adjust the timing relationship of four clock signals.
20. method as claimed in claim 19, it is characterised in that combine the cmos clock signal differential to described through prolonging
Slow clock signal includes: to generate four clock signals
Logically combine the cmos clock signal differential to the delayed clock signal to generate with a quarter
Four four points of clock signals of the active time of a clock cycle；And
Set and reset latch are to generate four clock signals based on four points of clock signals.
21. method as claimed in claim 20, which is characterized in that postpone each letter of the cmos clock signal differential centering
It number include for raising and lowering transformation using asymmetric delays to generate delayed clock signal.
22. method as claimed in claim 20, which is characterized in that calibrate the duty of the cmos clock signal differential pair
The adjusting of ratio and the delay of the delayed clock signal include:
Low-pass filtering is carried out to each of four points of clock signals and generates four points of clock signals through filtering；
Compare four through filtering points of clock signals pair and generates error signal；And
The error signal is integrated；And
The duty ratio of the cmos clock signal differential pair and described delayed is controlled based on integrated error signal
Clock signal delay.
23. a kind of equipment for generating four clock signals with exact timing relationship, the equipment include:
For by CML clock signal difference, to the device for being converted into cmos clock signal differential pair, which to include described in control
The duty cycle correction function of the duty ratio of cmos clock signal differential pair；
For from the cmos clock signal differential, to the device for generating four clock signals, which to include described in delay
Each signal of cmos clock signal differential centering；And
For calibrating the device of the timing relationship of four clock signals, which includes that control postpones the cmos clock letter
The delay and the control duty cycle correction function of each signal in number differential pair.
24. equipment as claimed in claim 23, which is characterized in that the device for generating four clock signals includes:
First delay cell is configured to generate delayed positive clock letter from the positive signal of the cmos clock signal differential pair
Number；
Second delay cell is configured to generate delayed negative clock letter from the negative signal of the cmos clock signal differential pair
Number；
Logic circuitry, be configured to combine the cmos clock signal differential to delayed clock signal to generate tool
There are four four points of clock signals of the active time of a quarter clock cycle；And
Set-reset latch is configured to generate four clock signals from four points of clock signals.
25. equipment as claimed in claim 24, which is characterized in that change for raising and lowering, first delay cell
There are asymmetric delays with second delay cell.
26. equipment as claimed in claim 24, which is characterized in that each delay cell includes single delay-level.
27. equipment as claimed in claim 24, which is characterized in that the device for calibration includes: low-pass filter,
It is configured to each of four points of clock signals is filtered and generated four points of clock signals through filtering；
Comparator is configured to compare four points of clock signals pair through filtering and generates error signal；And
Integrator is configured to integrate the error signal from the comparator described to control to generate control
The delay of delay cell and the duty cycle correction function.
28. equipment as claimed in claim 23, which is characterized in that it is described for by CML clock signal difference to being converted into
The device of cmos clock signal differential pair includes:
Self biased amplifier is coupled to input capacitance the CML clock signal difference pair, and its output coupling is described in
Cmos clock signal differential pair,
The wherein threshold level of self biased amplifier described in the duty cycle correction function control.
29. equipment as claimed in claim 28, which is characterized in that each self biased amplifier includes phase inverter, and
The resistors in series being connected between the input of the phase inverter and the output of the phase inverter, and
Wherein the duty cycle correction function is by providing electric current to the midpoint of the resistors in series or from the series resistance
Electric current is drawn to control the threshold level of the self biased amplifier in the midpoint of device.
30. equipment as claimed in claim 23, which is characterized in that further comprise for based on phase control signal from multiple
Input clock signal interpolation is to generate the device of the CML clock signal difference pair.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/257,913 | 2014-04-21 | ||
| US14/257,913 US9225324B2 (en) | 2014-04-21 | 2014-04-21 | Circuit for generating accurate clock phase signals for high-speed SERDES |
| PCT/US2015/019970 WO2015163988A1 (en) | 2014-04-21 | 2015-03-11 | Circuit for generating accurate clock phase dignals for a high-speed serializer/deserializere |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106464260A CN106464260A (en) | 2017-02-22 |
| CN106464260B true CN106464260B (en) | 2019-04-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580020616.8A Active CN106464260B (en) | 2014-04-21 | 2015-03-11 | For generating the circuit of accurate clock phase signal for High Speed Serialized device/deserializer |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US9225324B2 (en) |
| EP (1) | EP3134973B1 (en) |
| JP (1) | JP6133523B1 (en) |
| KR (1) | KR101694926B1 (en) |
| CN (1) | CN106464260B (en) |
| BR (1) | BR112016024426A2 (en) |
| ES (1) | ES2646551T3 (en) |
| HU (1) | HUE033627T2 (en) |
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| WO (1) | WO2015163988A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| HUE033627T2 (en) | 2017-12-28 |
| EP3134973B1 (en) | 2017-09-13 |
| CN106464260A (en) | 2017-02-22 |
| KR20160126086A (en) | 2016-11-01 |
| JP6133523B1 (en) | 2017-05-24 |
| BR112016024426A2 (en) | 2017-08-15 |
| US9225324B2 (en) | 2015-12-29 |
| ES2646551T3 (en) | 2017-12-14 |
| EP3134973A1 (en) | 2017-03-01 |
| WO2015163988A9 (en) | 2016-11-24 |
| MX2016013399A (en) | 2017-02-15 |
| US20150303909A1 (en) | 2015-10-22 |
| KR101694926B1 (en) | 2017-01-10 |
| JP2017517937A (en) | 2017-06-29 |
| WO2015163988A1 (en) | 2015-10-29 |
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