CN106463172A - Apparatuses and methods for performing multiple memory operations - Google Patents
Apparatuses and methods for performing multiple memory operations Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Non-Volatile Memory (AREA)
- Memory System (AREA)
Abstract
The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.
Description
Technical field
Embodiments of the invention generally relate to a kind of storage arrangement and the method operating described storage arrangement, and
More particularly, it is related to one kind and has be suitable to receive individual command and causing to memory array in response to described individual command
The storage arrangement of the controller of execution multiple access operation (such as write or read operation), and one kind is using described memory
The method of device.
Background technology
In many non-volatile memory technologies, storage arrangement has controller, and described controller is configured to connect
Receive and specify the life of the memory access operations that memory array is executed (such as read operation, write operation or erasing operation)
Order.Described controller can be configured to cause further to be grasped by the memory access that described order is specified to memory array execution
Make.It will be appreciated that, the total time being associated with execution accessing operation and energy not only comprise execution accessing operation being directly related in itself
Time and energy, but also comprise can be before execution accessing operation and some overhead operations of executing afterwards.Some expenses
Operation executes when controller causes memory access operations and can dramatically increase total time and energy and shorten battery life.
Accordingly, it would be desirable to reduce the total time being associated with execution memory access operations and energy.
Brief description
The latter end of specification particularly points out and clearly advocates advocated subject matter.If however, with reference to
Under describe in detail and combine institute's accompanying drawings and read together, then can be best understood both tissue and/or method of operating and its
Target, feature and/or advantage, in described institute accompanying drawings：
Fig. 1 is the schematic block circuit diagram of the storage arrangement according to an embodiment.
Fig. 2A is the access illustrating the multiple memory access operations specified by the multiple orders being received by controller
Sequential chart.
Fig. 2 B is the multiple storages illustrating according to specified by the individual command that an embodiment is received by controller
The access sequential chart of device accessing operation.
Fig. 3 is the schematic circuit of the storage arrangement comprising phase-changing memory unit according to an embodiment.
Fig. 4 A is the multiple storages illustrating according to specified by the individual command that an embodiment is received by controller
The access sequential chart of device accessing operation.
Fig. 4 B is the multiple storages described according to specified by the individual command that the execution of an embodiment is received by controller
The flow chart of the method for device accessing operation.
Fig. 5 is the schematic block diagram of the storage arrangement comprising NAND memory array according to an embodiment.
Fig. 6 A is the access illustrating the multiple memory access operations specified by the multiple orders being received by controller
Sequential chart.
Fig. 6 B is the multiple storages illustrating according to specified by the individual command that an embodiment is received by controller
The access sequential chart of device accessing operation.
Specific embodiment
In some non-volatile memory technologies, storage arrangement has controller, and described controller is configured to connect
Receive and specify the life of the memory access operations that memory array is executed (such as read operation, write operation or erasing operation)
Order.Described controller can be configured to cause further to be grasped by the memory access that described order is specified to memory array execution
Make.It will be appreciated that, the time being associated with execution accessing operation and/or energy not only comprise (for example) by accessing pulse
(such as programming pulse or reading pulse) puts on and executes time and the energy that actual accessing operation is related on memory cell,
But also comprise to execute time and the energy that some overhead operations are related to.Described overhead operations can comprise (for example) and apply
To some row and/or arrange into line precharge before access pulse, and/or by some row and/or row after applying access pulse
Electric discharge.In some technology, these overhead operations (such as be pre-charged and discharge) are whenever causing execution memory to be deposited by controller
Execute during extract operation, and the total time of storage arrangement and/or energy efficiency can be made to degrade.For example, although changing storage
The time that the state of device unit (such as phase-changing memory unit) is spent from several nanoseconds to several delicate, but can apply programming arteries and veins
What before punching, some rows and columns were entered with line precharge spent can dramatically increase overhead time and/or energy total time.When extra
Between and/or energy may depend on (for example) can apply access pulse before enter line precharge row and row resistance and electricity
Hold.By executing multiple access operation it may be advantageous to reduce total access time and energy for one group of given overhead functions.
Hereinafter, disclose the storage arrangement of the multiple memory cells comprising in memory array.Described memory
Device comprises Memory Controller, and it is specified multiple by execute to memory array that described Memory Controller is configured to reception
Each of designated multiple memory access operations of the individual command of memory access operations, wherein individual command include
One of write operation, erasing operation or read operation.Described Memory Controller is configured to respond to described further
Individual command and cause to memory array execute designated multiple memory access operations.In operation, storage arrangement can
Reduced by being not for each of designated accessing operation and repeating some overhead functions and execute designated accessing operation
Each of associated time and/or energy.
Fig. 1 schematically illustrates the circuit block diagram of the storage arrangement 2 according to some embodiments.Storage arrangement 2
Comprise the memory array 10 including multiple row 20 and multiple row 22.Memory array 10 is extraly included between row 20 and row 22
Each intersection multiple memory cells 14.In some embodiments, row 20 may be additionally referred to as bit line or digital line,
And row 22 may be additionally referred to as wordline.Any suitable telecommunications of (for example) voltage, electric current or electric field etc. can be comprised by applying
Number and access at least some of memory cell 14 memory cell.Each of memory cell 14 can have by coupling
The address defined to row 22 and the row 20 of memory cell 14.
According to some embodiments, storage arrangement 2 extraly comprises column decoder 44 and the electrical connection being electrically connected to row 20
Row decoder 40 to row 22.In operation, the physical address of memory cell 14 to be accessed can be by memory cell address
Specify, described memory cell address may be included in memory access commands.Memory cell address can comprise corresponding to treating
The column address of the row of activation and row and/or row address, so that access target memory cell.Receiving memory cell address
Afterwards, column decoder 44 is configured to column address and selects row to be activated, and row decoder 40 is similarly configured to solve
Code row address simultaneously selects row to be activated.
Storage arrangement 2 extraly comprises the line driver 32 (it can be word line driver) being electrically connected to row 22, and
It is electrically connected to the sensing amplifier 36 of row 20.During accessing operation, activate in the row 22 specified by the address in order
One or more of person and row 20.
Again referring to Fig. 1, in certain embodiments, memory array 10 is connected further to Memory Controller 50, described
Memory Controller is configured to control the various accessing operations to memory array 10, comprises write, erasing and reads.In behaviour
In work, Memory Controller 50 is configured to receive one or more memory cells access memory array 10 from processor
14 signal.Controller 50 is configured to column decoder 44 again and control signal is transmitted into memory array by row decoder 40
Row 10.In certain embodiments, Memory Controller 50 is integrated in solid-state integrated circuit as a part for storage arrangement 2
In.In other embodiments, Memory Controller 50 can be a part for host apparatus.
Memory array 10 includes nonvolatile memory (NVM) unit 14.In certain embodiments, NVM cell 14 wraps
Contain and be electrically coupled or be connected to memory element each other and selector element.In certain embodiments, NVM cell 14 can comprise thermocouple
Close the selector element of memory element.As used herein, memory element refers to the kept physical state of NVM cell 14
The element reaching prolonging period (for example, more than 1 year) and no refreshing or rewrite.As used herein, selector element is
Refer to NVM cell 14 permit under given conditions (for example, when voltage exceedes threshold voltage) access be connected to selection
The element of the memory element of device element.
Floating grid that the example of memory element comprises double gate transistor, phase change memory device, resistance change to be deposited at random
Access to memory (RRAM), conducting bridge random access memory (CBRAM) and/or spin transfer torque random access memory
, and other types of memory element (STT-RAM).The example of selector element comprises two-terminal selector installation, and such as two
Pole pipe, ovonic threshold switch (OTS) (OTS), tunnel junctions, or hybrid ionic-electronic conductor (MIEC), and other two-terminal selector
Device.Alternatively, selector node can comprise three arrangements of terminals, such as field-effect transistor (FET) or bipolar junction transistor
, and other switch element (BJT).
Again referring to Fig. 1, it is electrically coupled to row 20 and the NVM cell 14 of row 22 can be accessed by accessing operation.As herein
Used, accessing operation can refer to write accessing operation, erasing accessing operation, or reads accessing operation.
In certain embodiments, NVM cell 14 comprises flash memory cells.In these embodiments, write access behaviour
Work can comprise to increase electronics soon from the floating grid tunnelling of channel region to memory flash cells by (for example)
The threshold voltage of flash memory cell.On the other hand, erasing accessing operation can comprise by (for example) by electronics from storage
The floating grid of device flash cells to reduce the threshold voltage of flash memory cells to channel region tunnelling.Read accessing operation
Can comprise to detect driving current under read voltage for the flash transistor and determine flash memory cells whether be written into or
Erasing.
In certain embodiments, NVM cell 14 comprises phase transition storage (PCM) unit.As used herein, PCM is mono-
Unit refers to comprise the NVM cell of memory element, described memory element may depend on the material that described memory element comprises one or
Multiple phases and show different resistance.In these embodiments, the write that may be additionally referred to as reset operation for PCM cell is deposited
The resistance states of memory cell can be changed into high resistance state (HRS) relatively from rather low resistance state (LRS) by extract operation.
Reset operation can (for example) be realized by following operation：Apply to be enough to melt the memory element including chalcogenide material
At least one of resetting current is simultaneously quenched so that at least a portion of memory component becomes the state of quenching of amorphous phase, borrows
This forms HRS.In addition, may be additionally referred to as the resistance by memory cell for the erasing operation of setting operation for PCM cell
State changes into LRS from HRS.Setting operation can (for example) be realized by following operation：Apply enough to make including chalcogenide
The setting electric current of at least a portion crystallization of the memory component of thing material is so that the major part of memory component becomes and height
The crystalline state that resistance states are compared.
Fig. 2A is to illustrate for executing the multiple memories specified by the multiple orders being received by Memory Controller
Access sequential Figure 90 of the bidding protocol of accessing operation.The bidding protocol of Fig. 2A may be implemented in similar to depositing described in Fig. 1
In the storage arrangement of reservoir device 2, wherein Memory Controller can be configured to receive multiple orders, in the plurality of order
Each specify will to memory array initiate memory access operations, every in wherein designated memory access operations
One comprises one of write operation or read operation.
Again referring to Fig. 2A, access sequential Figure 90 and illustrate bus time line 90a, it shows the first order (CMD1)
100a, the second order (CMD2) 100b and the 3rd order (CMD3) 100c.Although for clear and concise description purpose, diagram is said
Bright first order 100a to the 3rd order 100c and respective operations, it will be understood that any number can be illustrated in a similar manner
Order and respective operations.Access sequential Figure 90 also illustrates descriptor line 90b, and it illustrates follows in first idle (IDLE)
102a, the second idle (IDLE) 102b and the 3rd leave unused first memory accessing operation (OP1) 106a after (IDLE) 102c,
Second memory accessing operation (OP2) 106b and the 3rd memory access operations (OP3) 106c.First memory accessing operation
106a to the 3rd memory access operations 106c is by the first order 100a to the 3rd order 100c triggering.Line 90b is extra for descriptor
Illustrate and deposited in first memory accessing operation 106a, second memory accessing operation 106b and the 3rd memory respectively
Before the first access before extract operation 106c, memory array being executed, operation 104a, the second access front operation 104b and the 3rd deposit
Operation 104c before taking.Descriptor line 90b extraly illustrates respectively in first memory accessing operation 106a, the second storage
Operate to after the first access of memory array execution after device accessing operation 106b and the 3rd memory access operations 106c
108c is operated after operation 108b and the 3rd access after 108a, the second access.
In certain embodiments, 104a, the front operation of the second access front operation 104b and the 3rd access are operated before the first access
104c can comprise (for example), to what the multiple row being connected to row decoder executed, from initial voltage, it is pre-charged to preliminary filling
The precharge operation of piezoelectric voltage.Precharge operation is followed of the first access behaviour to the first to the 3rd memory cell execution
Make 106a to the 3rd accessing operation 106c.Each of first to the 3rd accessing operation comprises to access pulse by first to the 3rd
It is applied to the corresponding line corresponding to memory cell to be accessed in multiple row.In addition, in certain embodiments, the first access
Afterwards operation 108a, second access after operation 108b and the 3rd access after operation 108c can comprise (for example) to be connected to row solution
The discharge operation it being returned to initial voltage from pre-charge voltage electric discharge of multiple row execution of code device.
Therefore, as illustrated in fig. 2, in response to three order (CMD1) 100a, (CMD2) 100b and
(CMD3) 100c and each of three memory access operations (OP1) 106a, (OP2) 106b executing and (OP3) 106c,
After operating (for example, precharge operation) 104a, 104b and 104c and individually accordingly access before executing individually corresponding access
Operation (for example, discharge operation) 108a, 108b and 108c.
Fig. 2 B is to illustrate according to some embodiments for executing the individual command institute being received by Memory Controller
Access sequential Figure 110 of the bidding protocol of multiple accessing operations specified.The bidding protocol of Fig. 2 B may be implemented in similar in Fig. 1
In the storage arrangement of described storage arrangement, described storage arrangement comprise to have the memory array of multiple wordline with
And Memory Controller, wherein said Memory Controller is configured to receive specify and multiple deposits execute to memory array
The individual command of access to store operation.Described bidding protocol can be implemented in storage arrangement further, wherein said memory
Controller is configured to respond to individual command further and continuously initiates designated multiple memory access operations, wherein singly
Each of designated multiple memory access operations of individual order comprise one of write operation or read operation.
Again referring to Fig. 2 B, access sequential Figure 110 and illustrate bus time line 110a, it shows individual command (CMD)
120.Access sequential Figure 110 also illustrates descriptor line 110b, and its description is triggered and memory array is held by individual command
Multiple accessing operations of row.Descriptor line 110b illustrates：After idle (IDLE) 112, individual command (CMD) 120 touches
Send out operation 114 before access.In certain embodiments, before accessing, operation 114 comprises will be connected to multiple row of row decoder simultaneously
From initial voltage precharge-to-precharge voltage.Before access, operation 124 is followed of multiple memory access operations (OP1)
116a, (OP2) 116b and (OP3) 116c.Although for clear and concise description purpose, illustrate the first operation 116a to
Three operation 116c, it will be understood that disclosed principle and advantage will be applied to any number operation.In certain embodiments, hold
The multiple memory access operations of row comprise：At the first accessing operation (OP1) 116a, access is connected to the first row in multiple row
First memory unit, access the second of the second row being connected in multiple row at the second accessing operation (OP2) 116b and deposit
Storage unit, and access is connected to the 3rd memory of the third line in multiple row at the 3rd accessing operation (OP3) 116c
Unit.The row of corresponding memory cell can be connected to execute accessing pulse and be applied in accessing operation by (for example)
Each.In certain embodiments, after multiple memory access operations (OP1) 116a, (OP2) 116b and (OP3) 116c
118 are operated after being followed by access.In certain embodiments, operate 118 to be included in after access will connect at single discharge operation simultaneously
The multiple row being connected to row decoder return to initial voltage from pre-charge voltage electric discharge.
Therefore, it is in embodiment illustrated in Fig. 2 B, compared with Fig. 2A, in response to individual command
(CMD) 120 and execute all three operation (OP1) 116a, (OP2) 116b and (OP3) 116c, execution access before operation 114
118 (for example, single discharge operations) are operated after (for example, single precharge operation) and single access.
In certain embodiments, can be connected to different rows memory cell execute three operation (OP1) 116a,
(OP2) 116b and 116c (OP3).In other embodiments, can be to two or more memory cells being connected to shared row
Any both or more person in three operations of execution.
In certain embodiments, three operation (OP1) 116a, (OP2) 116b and (OP3) 116c can comprise same operation
(that is, one of write, erasing and reading).In other embodiments, three operation (OP1) 116a, (OP2) 116b and
(OP3) 116c can mix and comprise different operating.
In Fig. 3 and 4A to 4B, disclose in the context of phase transition storage, according to some embodiments, there is controller
Storage arrangement and method using described storage arrangement, described controller is configured to cause is specified by individual command
Multiple accessing operations.However, it will be appreciated that embodiment disclosed herein can be generally applicable to other types of memory technology.
Fig. 3 is phase transition storage (PCM) device 130 being configured to compound storage operation according to an embodiment
Schematic circuit.Similar to the storage arrangement 2 of Fig. 1, according to some embodiments, PCM device 130 comprises to be electrically connected to row 20
Column decoder 44 and the row decoder 40 being electrically connected to row 22.It is also similar to Fig. 1, phase-changing storage device 130 extraly wraps
Contain and be electrically connected to the line driver 32 of row 22 and be electrically connected to the sensing amplifier 36 of row 20.Storage arrangement may be electrically connected to deposit
Memory controller 50, described Memory Controller is configured to receive access phase transition storage (PCM) array 122 from processor
One or more memory cells signal.Controller 50 is configured to for row and row control signal to be transmitted into column decoder 44 again
And row decoder 40.
Again referring to Fig. 3, PCM device 130 comprises PCM array 122, and described PCM array is " crosspoint " type arrays and bag
Contain and be placed in the many of the joining being formed with the row 22 being connected to line driver 32 by the row 20 being connected to sensing amplifier 36
Individual phase transition storage (PCM) unit 128.In certain embodiments, PCM cell can be defined by uniquely biasing its joining
Each of 128 row and row individually to access each of PCM cell 128.As used herein, to be accessed
PCM cell 128 is referred to alternatively as being located at target (T) unit of the joining being formed by select column 20-n and select row 22-m.Can
Access T unit by crossing over T unit applying access signal, wherein access signal can comprise to write access signal, erasing access
Signal or reading access signal.Access signal can be voltage signal or current signal, and other signal.
Generally, in " crosspoint " type PCM array, one or more T unit can be accessed, suppress remaining single simultaneously
Unit.This can (for example) apply to be substantially different from the suppression of the access signal being applied to T unit by crossing over remaining element
Signal and realize.Roughly, for example, can be by selected column voltage VCOL SELBeing applied to select column (is 20- in this example
N), simultaneously by select row voltage VROW SELIt is applied to select row (being 22-m in this example).Meanwhile, may span across remaining row to apply
Suppressed column voltage VCOL INHIBIT, and may span across the remaining row suppressed row voltage V of applyingROW INHIBIT.Under this arrangement, when
VCOL SELWith VROW SELBetween biasing more than VACCESSWhen, can access target unit T.In addition, crossing over along select column 20-n's
Suppressed unit (below, being referred to as " A " unit) applies about poor (VCOL SEL–VROW INHIBIT) value biasing.In addition, across
More apply about poor (V along the suppressed unit (below, being referred to as " B " unit) of select row 22-mROW SEL–VCOL INHIBIT)
The biasing of value.In addition, remaining the suppressed unit crossed over across suppressed row and suppressed row (below, is referred to as " C " single
Unit) apply about poor (VCOL INHIBIT–VROW INHIBIT) value biasing.
It is in embodiment illustrated in Fig. 3, each PCM cell 128 comprises chalcogenide memory element 124.
In certain embodiments, each PCM cell 128 can comprise heater and (for example be based on Ge-Se-Te by chalcogenide material
(GST) alloy of alloy system) memory element 124 that formed.In addition, being in embodiment illustrated in Fig. 3, each
PCM cell 128 comprises selector 126, and described selector comprises bipolar junction transistor (BJT).In figure 3, illustrated choosing
Selecting device 126 is PNP BJT.However, in alternative embodiments, selector can comprise NPN BJT or diode.In figure 3, PCM
The memory element 124 of unit 128 connects along row 20 (for example, bit line).In addition, the base contact edge of PNP BJT 126
Row 22 (for example, wordline) to connect.
Fig. 4 A is to illustrate according to some embodiments for executing the individual command institute being received by Memory Controller
Access sequential Figure 140 of the bidding protocol of multiple accessing operations specified.The bidding protocol of Fig. 4 A may be implemented in similar in Fig. 3
Described in the PCM memory device of PCM memory device in, described PCM memory device includes memory array and through joining
Put the Memory Controller of the individual command to receive specified multiple memory access operations.Although it will be appreciated that, access sequential chart
140 illustrate multiple programming operations (it can refer to the resistance of PCM cell is changed into the reset operation of HRS from LRS), but herein
Described in method be not limited to this and can be similarly effected that (it can refer in executing multiple read operations and/or erasing operation
The resistance of PCM cell is changed into the setting operation of LRS from HRS).
Again referring to Fig. 4 A, access sequential Figure 140 and illustrate bus time line 140a, its displaying is specified will be to memory array
The individual command (CMD) 132 of multiple memory access operations of row execution.Access sequential Figure 140 extraly illustrates description
Symbol line 140b, its description is by multiple memory access operations of individual command (CMD) 132 triggering.Descriptor line 130b diagram is said
Bright after idle (IDLE) 134 in order to simultaneously by multiple row from the single precharge of initial voltage precharge-to-precharge voltage
Operation 136.Precharge operation 136 may include (for example) by the suppressed column voltage V describing in figure 3ROW INHIBITApply
To multiple row.Single precharge operation 136 be followed of by apply access pulse (for example, programming pulse 138a arrives
138f) by multiple accessing operations of the multiple memory cell execution to PCM array, each of which accessing operation is followed of
Verification operation (140a to 140f).For clear and concise description purpose, the embodiment of Fig. 4 A illustrates six accesses (citing
For, programming) operate and associated verification operation.However, described principle and advantage are applicable to any suitable number access
Operation and associated verification operation.In illustrated embodiment, multiple accessing operations comprise to being connected to first to the 6th
First access (for example, programming) operation 138a to the 6th access (citing of the first to the 6th memory cell execution of row
For, programming) operate 138f, each of wherein first accessing operation 138a to the 6th accessing operation 138f to be followed of
Corresponding first verification operation 140a to the 6th verification operation 140f to the first to the 6th memory cell execution.Descriptor line
140b be further illustrated in the 6th verification operation 140f after at single discharge operation 142 simultaneously by multiple row from preliminary filling
Piezoelectric voltage discharges into initial voltage.Discharge operation 142 may include (for example) from multiple be about to describe in figure 3 suppressed
Column voltage VROW INHIBITElectric discharge.In a word, it is in embodiment illustrated in Fig. 4 A, in response to individual command 132
And multiple accessing operation 138a to the 138f to memory array execution, only execute single precharge operation 136 and single electric discharge
Operation 142.Therefore, compared with wherein executing precharge operation and the bidding protocol of discharge operation for each accessing operation, can
Realize the time and/or energy is saved in executing multiple accessing operations.
Fig. 4 B is the multiple programmings described according to specified by the individual command that the execution of an embodiment is received by controller
The flow chart of the method 150 of accessing operation.In particular, method 150 may be implemented in similar to the inclusion including PCM array 122
In the phase-changing storage device of PCM device 130 of Fig. 3.It is to be understood, however, that methods described may be implemented in comprise other types of
In other storage arrangements of array (such as flash memory array).Although additionally, method 150 illustrates the multiple volumes of execution
Journey operates, but method can be similarly effected in the multiple read operations of execution and/or erasing operation.
The method 150 executing multiple program access operations in response to individual command comprises to receive using Memory Controller
152 specify the individual command of multiple program access operations that PCM array is executed.After receiving individual command, described side
Method comprises to cause in response to single access command or initiate to execute designated multiple memory access operations to memory array.
In the flow chart of Fig. 4 B, some reference characters have " imaginary point ", are another reference character afterwards.Example is 158-1 or 158-
m.Character after imaginary point indicates the example number of one or more program access operation of individual command.For example, 158-1 refers to
Show the first example (the first programming operation of individual command), and 158-m instruction m example (the m programming operation of individual command).
The value of m is 2 or more than 2.
Referring back to Fig. 3, during standby mode, PCM array 122 may be configured to have standby bias scheme, wherein
(for example, wordline) 22 of going is pre-charged to and the standby cancellation for (for example) about 1.2V can select voltage VHX, and will arrange
20 " soft-sphere model " or float to VHXMedium voltage and ground connection between.Under this bias scheme, not select unit, and reverse bias
The PNP BJT 126 of PCM cell 128 makes array leakage reduce.
Then, again referring to Fig. 4 B, after receiving 152 individual commands, method 150 extraly comprises multiple row 22 from first
Beginning voltage pre-charge 154 arrives pre-charge voltage.For example, referring back to Fig. 3, can by row 22 from can for (for example) about
The standby cancellation of 1.2V selects voltage VHXIt is pre-charged to and the programming for (for example) about 5V can cancel selection voltage VHX PROG.Separately
Outward, by row 20 " soft-sphere model " or V can be floated toHX PROGMedium voltage and ground connection between.With this understanding, not select unit,
And the PNP BJT 146 of reverse bias PCM cell 130 makes array current leakage reduce.
Again referring to Fig. 4 B, after line precharge 154 is entered to multiple wordline, method 150 extraly comprise execute 158-1 by
The first program access operation that individual command is specified, it can comprise for the first programming pulse to apply 158a-1 to being connected to select row
First select PCM cell.For example, referring back to Fig. 3, can be by 0 volt of select row program voltage will be can be about
VROW SEL PROGIt is applied to select row 22-m and select column 20-n is biased to V simultaneouslyCOL SEL PROG(to about 5V) and select to be programmed
Target (T) PCM cell.In addition, remaining unselected row 22- (m+1) and 22- (m-1) can be held in the cancellation that can be about 5V
Select voltage VHX PROGUnder, and remaining unselected row 20- (n-1) and 20- (n+1) can be kept " soft-sphere model " or float on
VHX PROGUnder medium voltage and ground connection between.Under here programming bias scheme, the PNP BJT of forward bias T PCM cell
126 so that sufficient program current IPROGFlow through T PCM cell with by target (T) PCM cell from low resistance state (LRS)
It is switched to high resistance state (HRS).In addition, under here programming bias scheme, by unselected " A " unit along select column 20-n
PNP BJT 146 biasing reach close to 0 volt, and described PNP BJT may remain off.In addition, by along select row 22-m not
The PNP BJT 146 selecting " B " unit biases the threshold voltage reaching less than PNP BJT 146, and described PNP BJT also keeps closing
Disconnected.In addition, reverse bias is along unselected row 22- (m+1) and 22- (m+1) and along unselected row 20- (n-1) and 20- (n
+ 1) the PNP BJT 146 of unselected " C " unit is so that array leakage reduces.
Again referring to Fig. 4 B, after the first programming pulse is applied the selected PCM cell of 158a-1 to first, method 150 volume
Other places comprise by first program verification pulse apply 158b-1 in receive the first programming pulse first select PCM cell on
Determine whether the first resistance selecting PCM cell being connected to select row has been increased to wanted resistance levels.In some embodiments
In, the first checking pulse can be applied to the first the first select row selecting PCM cell, make the voltage on the rest of row simultaneously
Remain basically unchanged.For example, referring back to Fig. 3, can be by being the select row checking electricity of about 0 volt of (for example)
Pressure pulse VROW SEL VERIFYBe applied to select row 22-m and can be (for example) about 1.2V select column verifying voltage
VCOL SEL VERIFYIt is applied to select column 20-n and verify the state of target (T) PCM cell.Remaining unselected row 22- (m+1) and
22- (m-1) can keep being pre-charged to and the programming for (for example) about 5V can cancel selection voltage VHX PROG, and row 20 " floppy drive
Dynamic " or float to VHX PROGMedium voltage and ground connection between.Under here checking bias scheme, forward bias T PCM cell
PNP BJT 146 is so that flow through the verificating current I of T PCM cellVERIFYCan be sensed by sensing amplifier 36.In addition,
Under checking bias scheme, reverse bias is along the PNP BJT 146 of unselected " A " unit of select column 20-n, and described PNP
BJT may remain off.In addition, PNP BJT 146 biasing of unselected " B " unit along select row 22-m can be reached being less than
The threshold voltage of PNP BJT 146 is to be held off.In addition, reverse bias along unselected row 22- (m+1) and 22- (m+1) with
And along unselected row 20- (n-1) and 20- (n+1) unselected " C " unit PNP BJT 146 so that array leakage subtracts
Few.
Again referring to Fig. 4 B, method 150 extraly comprises based on following operation and carries out whether first select PCM cell
It is programmed into the first checking 158c-1 of wanted resistance levels：Amplified using the sensing being connected to select column (for example, bit line)
The electricity through described word-select memory unit that device sensing detects and described select column between in select row (for example, wordline)
Stream.After determining that the first selected PCM cell is not yet programmed into wanted resistance levels, execution 158-1 first program access operation volume
Other places is included in 158a-2 to 158a-n place and applies one or more additional programming pulse, applies 158b-2 to 158b-n additionally corresponding
Program verification operates, and is additionally accordingly verified 158c-2 to 158c-n, until first select PCM cell already programmed into
Till wanted resistance levels.
Method 150 extraly comprises to determine that 162-1 is operated by one or more extra program access that individual command is specified
No await to the second PCM cell execution being connected to corresponding to both the in multiple wordline of individual command.
After determining that one or more extra program access of being specified by individual command of 162-1 operates and await executing, method
150 extraly comprise execution 158-2 to 158-m is operated by the extra program access that individual command is specified, and it can comprise to apply
158a-1 to 158a-n proper number programming pulse, applies 158b-1 to 158b-n corresponding program verification operation, and carries out volume
Select outward corresponding checking 158c-1 to the 158c-n whether already programmed into wanted resistance levels for the PCM cell, this is similar to above
Select PCM cell for first to be discussed.The suitable number specified in individual command in each execution 158-2 to 158-m
After additional programming operation, this executes every time and is followed of at least one determining 162-2 to 162-m and being specified by individual command
Whether additional memory access operation awaits executing.
It will be appreciated that, compared with execution 158-1 first program access operation, being not required to by multiple traveling line precharges 154
To carry out the subsequently extra program access operation of 158-2 to 158-m, because multiple row are not discharged, until having executed by single
Till ordering program access operation 158-1 to the 158-m specifying.
Therefore, executing many program access operations of 158-1 to 158-m in response to individual command and determining 162-m no
Operated after awaiting execution by the additional memory access that individual command is specified, method 150 advances to multiple row from can be
(for example) selection voltage V is cancelled in the programming of about 5VHX PROGElectric discharge 164 can be standby for (for example) about 1.2V to return to
Select voltage V with cancellingHX.In addition, by row 20 " soft-sphere model " or floating to standby cancellation selection voltage VHXIn and ground connection between
Between voltage.
After by multiple row electric discharge 164, method 150 completes 166 and is operated by multiple program access that individual command is specified
And make array return to standby mode, wherein not select unit, and the PNP BJT 146 of reverse bias PCM cell 130 makes battle array
Column leakage reduces.Therefore, by using method 150, advantageously can be before executing multiple program access operations and afterwards to many
Individual row is only once pre-charged and is discharged, rather than all carries out the precharge to multiple row and put for each program access operation
Electricity, reduces the precharge with row and the discharge time being associated and energy whereby.
It is in the embodiment described in Fig. 4 A and 4B, Memory Controller is configured to for multiple memory access
(for example, program) operation cause cause after memory access (for example, programming) pulse is applied to PCM cell by
Program verification pulse is applied to PCM cell.However, in other embodiments (not illustrating), Memory Controller can be through joining
Put with cause multiple memory access (for example, program) pulse is applied to the first PCM cell after cause will be multiple
Program verification pulse is applied to accordingly multiple PCM cell.
Fig. 5 is to comprise the managed of at least one storage arrangement array 216 and controller 212 according to another embodiment
The schematic block diagram of storage arrangement 200, wherein controller 212 are configured to respond to single from host apparatus 210 reception
Order and cause and multiple accessing operations are executed at least one storage arrangement array 216.Managed storage arrangement 200 is extremely
A few storage arrangement array 216 also can comprise embedded controller, row decoder and row decoding in addition to memory array
Device, and other support circuit.Can (for example) with as described similar mode configuration memory dress in FIG above
Put array 216.
In one embodiment, the managed storage arrangement 200 of Fig. 5 includes embedded multi-media card (eMMC) device,
Wherein at least one storage arrangement array 216 comprises NAND Flash array, and controller 212 is contained in single encapsulated nude film
In managed storage arrangement 200 in.In one embodiment, the managed storage arrangement 200 comprising eMMC device can
There is external serial interface.External serial interface can have the bandwidth that (for example) is up to 400 Mbytes per second.
Generally, in NAND Flash memory array, execution write operation or read operation under " page " level.Page
The multiple memory cells being connected to single wordline can be comprised.The big I of the number of memory cell in page and page is very big
In the range of change.
Fig. 6 A is to illustrate in response to many in storage arrangement (such as conventional NAND flash memory device)
Individual order and execute the access sequential chart 220 of the bidding protocol of multiple accessing operations.The bidding protocol of Fig. 6 A may be implemented in and comprises
In the conventional NAND flash memory device of memory array, described memory array may be connected to be configured to receive and cause
The Memory Controller of multiple orders, each of the plurality of order is specified and is deposited initiateed by Memory Controller one
Access to store operates.Memory Controller can be configured to respond to each of multiple orders further and initiate designated
Memory access operations, each of wherein designated memory access operations include write operation or read operation
One of.
Again referring to Fig. 6 A, access sequential chart 220 and illustrate storage arrangement bus time line 220a, it is shown and specifies the
The first program command 222a of one programming operation 230a, first state 224a after the first program command 222a, immediately preceding
After first state 224a specify the first read operation 232 the first reading order 226a, the first reading order 226a it
The second state 224b afterwards, the second program command specifying the second programming operation 230b after the second state 224b
222b, and third state 224c.In first program command 222a, the first reading program 226a and the second program command 222b
Each may specify the accordingly single accessing operation less than page size.By way of illustration, for the page of 16 kilobytes
Size, each of the first program command 222a, the first reading order 226a and second program command 222b can each specify
4 kilobytes of access memory.
Access sequential chart 220 also illustrates description line 220b, and its description is deposited by multiple command triggers and to NAND Flash
Multiple accessing operations of memory array execution.Description line 220b illustrates being compiled by first of the first page to NAND Flash array
First programming operation 230a of journey order 222a triggering.Subsequently, description line 220b illustrates to the execution of NAND Flash array
The first read operation 232 by the first reading order 226a triggering.First read operation 232 to first page or can be different from first
The second page execution of page.Subsequently, description line 220b illustrates to the execution of NAND Flash array by the second program command 222b
Second programming operation 230b of triggering.Second programming operation 230b can be to first page, the second page different from first page or difference
Page three execution in first page and second page.By way of illustration, for the page size of 16 kilobytes, the first programming behaviour
Make the phase that each of 230a, the first read operation 232 and second programming operation 230b may be in response in multiple access commands
Answer 4 kilobytes of one and each self-access memory.
Fig. 6 B is to illustrate according to some embodiments in response to comprising NAND Flash memory array and control
Individual command on the storage arrangement of device and execute the access sequential chart 240 of the bidding protocol of multiple accessing operations.Fig. 6 B's
Bidding protocol may be implemented in the storage arrangement similar to the managed storage arrangement 200 describing in Figure 5 above, described
Storage arrangement comprises storage arrangement 216 and the Memory Controller 212 with memory array, and described memory controls
Device is configured to receive individual command and initial multiple memory access operations that memory array will be executed.Memory controls
Device is configured to respond to individual command further and initiates designated multiple memory access operations, wherein designated memory
Each of accessing operation includes one of write operation or read operation.
Again referring to Fig. 6 B, access sequential chart 240 and illustrate managed memory bus timeline 240a, its displaying is single
Order 242 and the single accumulation state 244 after individual command 242.It will be appreciated that, different from may correspond to routine in Fig. 6 A
The memory bus timeline 220a of storage arrangement, the managed memory bus timeline 240a in Fig. 6 A correspond to similar
In the managed storage arrangement of the managed storage arrangement 216 of Fig. 5, described managed storage arrangement is except memory array
Row are outer also can to comprise embedded controller, row decoder and column decoder, and other support circuit, as described above.Single
Individual order 242 may specify (for example) multiple program access operation 250 and multiple reading accessing operation 252.
Access sequential chart 240 also illustrates description line 240b, and its description is triggered and to NAND Flash by individual command 242
Multiple accessing operations of memory array execution.Description line 240b illustrates to the execution of NAND Flash array by individual command
Multiple program access operations 250 of 242 triggerings and multiple reading accessing operation 252.It will be appreciated that, individual command 242 is sent to
Managed memory, and accessing operation itself executes to NAND Flash array.Similar to Fig. 6 A, that specifies in individual command is every
One accessing operation can be less than page size.By way of illustration, for the page size of 16 kilobytes, individual command 242 can
The multiple program access comprising the first program access operation and the operation of the second program access are specified to operate 250 each self-programming 4 K words
Section and specified multiple reading accessing operations 252 reading 4 kilobytes comprising read operation.In response to individual command, controller can
The first program access operation and the second program access operative combination is caused to be 8 kilobytes programming operations and single page is executed, and
Cause designated page is executed and read accessing operation.Therefore, compared with Fig. 6 A, will be to memory by specifying in individual command
Multiple operations of array execution, can avoid providing (for example) multiple case and wordline is repeatedly pre-charged with to single
The overhead of page write.
As described above, may be implemented in various contexts using the method that individual command executes multiple storage operations
In.Hereinafter, the example structure of individual command is described according to embodiment.
Table 1 describes the example according to the information in the operating parameter list that may be included in individual command of embodiment.Operation
Parameter list comprises parameter list header and multiple (first is arrived last) operation descriptor.Parameter list header contains
The information that all operations specified in individual command share.In addition, operation descriptor contains the details of each operation.
Table 1：Operating parameter list
Table 2 describes the example of the information that may be included in parameter list header according to embodiment.Parameter list header can
Comprise parameter list length, action type, the number of operation, base address and flag.Parameter list length field assigned operation
The length of parameter list.The identification of action type field is by by storage arrangement to the type of the operation that memory array executes (i.e.,
Programming, erasing, read).The number field of operation specifies the number of the operation descriptor that will comply with parameter list header.Operation is retouched
The number stating symbol corresponds to the number of multiple operations that memory array is executed.Base address field contains in multiple operations
The base address of the operation specified in each of descriptor.
Flags field can contain the information of several types.For example, flags field may specify execution in operation descriptor
In the certain order of multiple operations specified.In particular, flags field may specify will with operation descriptor in list time
Sequence or alternatively to execute multiple operations different from the order of order listed in operation descriptor.May be included in flags field
In other types of packet contain status format (for example, share or according to operation), command option etc..
Table 2：Parameter list header
| Byte | Description |
| … | Parameter list length |
| … | Action type |
| … | The number of operation |
| … | Base address |
| … | Flag |
Table 3 describes the example of the information that may be included in operation descriptor according to embodiment.Operation descriptor can comprise
Data descriptor length, action type, operation mark, address, data length and/or multiple data (the 0th to (n-1)
Individual).The length of descriptor length field assigned operation descriptor.Action type field is specified will be by storage arrangement to memory
The type (for example, read, program, wiping etc.) of the operation of array execution.For example, if in parameter list header or
Similar information is provided, then action type field can be omitted in some embodiments at other.Operation tag field identification is every
One specific operation descriptor.In case of presence, each operation descriptor in operating parameter list has unique value.Address
Field contains the start address of operation.Data length field specifies the amount of the data byte being related in operation.For example, have
The data length having 0 value specifies no data to be sent to device, and this is not qualified as mistake.In some embodiments, (citing comes
Say) if data transmission is never called in operation, then length field can be omitted.The decline of operation descriptor contains can be from main frame
It is sent to multiple data (the 0th individual to (n-1)) of storage arrangement.In some embodiments, (for example) if
The action type that length field is set to specify in 0, or action type does not comprise to transfer data to device, then can omit
Data field.
Table 3：Operation descriptor
Table 4 description may be included in the example of the information in data descriptor, wherein according to embodiment, will be to memory array
The operation of execution comprises request and from device, data is sent to main frame.Data descriptor can comprise data descriptor length, operation
Type, data length and/or multiple data (the 0th individual to (n-1)).Data descriptor length field specifies data descriptor
Length.Action type field may correspond to the value receiving in described request.Operation tag field identification operating parameter list
In the specific operation descriptor related to data to be sent.Data length field specifies the number being contained in data descriptor
According to amount (for example, in units of byte).
Again referring to table 4, in certain embodiments, storage arrangement is configured to single bag transmission and operating parameter list
Associated data, is wherein enclosed related to each operation descriptor in order with the order listed in operating parameter list
Data.In other embodiments, storage arrangement is configured to be packaged in data and is retouched similar in operating parameter list
In the structure of the structure stated.In other embodiments, storage arrangement is configured to multiple bag transmission and operating parameter list
Associated data.
Table 4：Data descriptor
Referring back to table 3, in certain embodiments, specify, in operation descriptor, the data transmission comprising from main frame to device
Operation in the case of, operation descriptor may specify the data length corresponding to data to be sent.Then, after order,
The available data descriptor structure similar to structure described in table 4 above is individually to transfer data.
Table 5 describes the example of the information that may be included in state descriptors according to embodiment.Described state descriptors can
Comprise state descriptors length, action type, operation mark and state.State descriptors length field designated state data describes
The length of symbol.Action type field has the value of the value that may correspond to receive in the request in operating parameter list.Operation mark
The note field identification operation descriptor related to described data.
Storage arrangement may be provided in the accumulation state of the operation specified in operating parameter list.Described state will be in success
" successful " is indicated in the case of completing the operation specified in operating parameter list.Alternatively, device can be carried using operation mark
For the state for each operation specified in operating parameter list to identify each operation.
Table 5：State descriptors
Although describing the present invention according to some embodiments, other enforcements that those skilled in the art is understood
Example (comprising not provide the embodiment of all features set forth herein and advantage) is also within the scope of the invention.Additionally, on
Various embodiments described by literary composition can be combined to provide other embodiments.In addition, institute's exhibition in the context of an embodiment
The some features shown may also be incorporated in other embodiments.Therefore, the scope of the present invention comes boundary only with reference to appended claims
Fixed.
Claims (26)
1. a kind of equipment, it includes：
Memory array, it includes multiple memory cells；And
Memory Controller, it is configured to：
Receive and specify the individual command to multiple memory access operations that described memory array executes, and
Cause and described designated multiple memory access operations are executed to described memory array, wherein in described individual command
Each of the plurality of memory access operations specified include one of programming operation or read operation.
2. equipment according to claim 1,
Wherein said memory array includes phase transition storage PCM cell, and
Wherein said Memory Controller is configured to following operation further and causes described designated multiple memories
Accessing operation：
Cause multiple wordline of described memory array from initial voltage precharge-to-precharge voltage；
Cause and first memory access pulse is applied to the first PCM cell being connected to one of the plurality of wordline, make
First memory accessing operation must be executed；
Cause and second memory access pulse is applied to the second PCM cell being connected to one of the plurality of wordline, make
Second memory accessing operation must be executed；And
Cause the plurality of word line discharge to described initial voltage.
3. equipment according to claim 2, wherein said first PCM cell and described second PCM cell are connected to described
The same wordline of memory array and be connected to the different lines of described memory array.
4. equipment according to claim 2, it is described that wherein said Memory Controller is configured to cause applying further
First memory access pulse simultaneously causes the described second memory of applying to access pulse, and does not cause and deposit in described first and second
By the plurality of word line discharge between access to store pulse.
5. equipment according to claim 2, wherein said first memory access pulse includes set pulse or reset arteries and veins
Punching one of, and wherein said second memory access pulse include in described set pulse or described reset pulse with institute
State one described in first memory access pulse identical.
6. equipment according to claim 2, wherein said first memory access pulse includes set pulse or reset arteries and veins
Punching one of, and wherein said second memory access pulse include in described set pulse or described reset pulse with institute
State one of first memory access pulse difference.
7. equipment according to claim 5, wherein said Memory Controller is configured to further：
Cause by described first memory access pulse be applied to described first PCM cell after, cause and the first program tested
Card pulse is applied to described first PCM cell；And
Cause by described second memory access pulse be applied to described second PCM cell after, cause and the second program tested
Card pulse is applied to described second PCM cell.
8. equipment according to claim 7, wherein cause memory access pulse and subsequently cause checking pulse comprise by
Word line voltage keeps substantial constant.
9. equipment according to claim 5, wherein said Memory Controller is configured to further：
After causing first and second memory access pulse described is applied to described first PCM cell, cause first
And second program verification pulse be applied to described first and second PCM cell corresponding.
10. equipment according to claim 2, one of first and second memory access pulse wherein said includes putting
One of digit pulse or reset pulse, and the other of first and second memory access pulse described includes reading arteries and veins
Punching.
A kind of 11. equipment, it includes：
Managed storage arrangement, it includes multiple storage arrangements；And
Memory Controller, it is configured to：
Receive and specify the individual command to multiple memory access operations that described storage arrangement executes, and
Cause and described designated multiple memory access operations are executed to described storage arrangement, wherein in described individual command
Each of the plurality of memory access operations specified include one of write operation or read operation.
12. equipment according to claim 11, wherein said Memory Controller is integrated together with described storage arrangement
In single package.
13. equipment according to claim 11,
Each of wherein said storage arrangement includes multiple flash memory cells pages, each of which flash memory list
Metapage includes the multiple flash memory cells being connected to common word line, and
Wherein said individual command specifies first memory operation and second memory operation, wherein said second memory operation
One of different including operating from described first memory in programming operation or read operation, and
Wherein said Memory Controller is configured to following operation further and causes described designated multiple memories
Accessing operation：
The sub-fraction to a flash memory cells page is caused to execute described first memory accessing operation, and
The sub-fraction to a flash memory cells page is caused to execute described second memory accessing operation.
14. equipment according to claim 13,
Wherein said individual command further specifies that and one of described first or second memory operation identical type
3rd storage operation, and
Wherein said Memory Controller is configured to cause the sub-fraction execution to a flash memory cells page further
Described 3rd memory access operations,
Wherein said Memory Controller is configured to cause further and executes described 3rd storage in order to described same one page
In device accessing operation and first and second storage operation described with described in described 3rd memory access operations identical
One.
A kind of 15. accesses include the method electronically implemented of the memory array of multiple memory cells, methods described
Including：
Receive and specify the individual command to multiple memory access operations that described memory array executes；And
Described designated multiple memory access operations are executed to described memory array,
Each of described designated multiple memory access operations of wherein said individual command include programming operation or reading
One of extract operation.
16. methods according to claim 15, wherein said memory array includes multiple phase transition storage PCM cell,
And wherein execute described designated multiple memory access operations and include：
By multiple wordline of described memory array from initial voltage precharge-to-precharge voltage；
First memory access pulse is applied to the first PCM cell being connected to one of the plurality of wordline；
Second memory access pulse is applied to the second PCM cell being connected to one of the plurality of wordline；And
By the plurality of word line discharge to described initial voltage.
17. methods according to claim 16, wherein said first PCM cell and described second PCM cell are connected to institute
The same wordline stating memory array and the different lines being connected to described memory array.
18. methods according to claim 16, wherein apply first and second memory access pulse described, and not in institute
State remaining word line discharge in the plurality of wordline between first and second memory access pulse.
19. methods according to claim 18, wherein first and second memory access pulse each include set pulse
Or the same one in reset pulse.
20. methods according to claim 19, wherein execute described designated multiple memory access operations and wrap further
Include：
After the access pulse of described first memory is applied to described first PCM cell, the first program verification pulse is applied
It is added to described first PCM cell；And
After the access pulse of described second memory is applied to described second PCM cell, the second program verification pulse is applied
It is added to described second PCM cell.
21. methods according to claim 15, wherein said memory array includes multiple flash memory cells pages, its
In each flash memory cells page include multiple flash memory cells of being connected to common word line, and
Wherein said individual command specifies first memory operation and the second memory different from described first memory operation
Operation,
Wherein execute described designated multiple memory access operations to include：
Described first memory accessing operation is executed to the sub-fraction of a flash memory cells page, and
Described second memory accessing operation is executed to the sub-fraction of a flash memory cells page.
22. methods according to claim 21,
Wherein said individual command further specifies that and one of described first or second memory operation identical type
3rd storage operation, and
Wherein execute described designated multiple memory access operations to further include：To for its execution described first and second
The sub-fraction execution described the with the described page of one described in described 3rd storage operation identical in storage operation
Three memory access operations.
A kind of 23. equipment, it includes：
Memory array；
Memory Controller, it is configured to respond to cause from the individual command of main frame many to described memory array
Individual memory access operations,
Wherein said individual command specifies continuous operation descriptor, and described continuous operation descriptor is specified will be to described memory array
Arrange each of the plurality of memory access operations causing,
Each of described multiplexed memory accessing operation of wherein said individual command includes write operation or read operation
One of.
24. equipment according to claim 23, wherein said memory access operations are included in write or read operation
Different persons.
25. equipment according to claim 23, wherein said Memory Controller is configured to cause described further
The single status corresponding to described multiplexed memory accessing operation are produced after multiple memory access operations.
26. equipment according to claim 23, wherein said Memory Controller be configured and with different from described list
The order specifying the order of described continuous operation descriptor in individual order causes described multiple operation.
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| CN201910855051.5A CN110751973A (en) | 2014-05-06 | 2015-05-04 | Apparatus and method for performing multiple memory operations |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/270,944 US9384830B2 (en) | 2014-05-06 | 2014-05-06 | Apparatuses and methods for performing multiple memory operations |
| US14/270,944 | 2014-05-06 | ||
| PCT/US2015/029108 WO2015171522A1 (en) | 2014-05-06 | 2015-05-04 | Apparatuses and methods for performing multiple memory operations |
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|---|---|---|---|
| CN201910855051.5A Division CN110751973A (en) | 2014-05-06 | 2015-05-04 | Apparatus and method for performing multiple memory operations |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580023175.7A Active CN106463172B (en) | 2014-05-06 | 2015-05-04 | For executing the device and method of multiplexed memory operation |
| CN201910855051.5A Withdrawn CN110751973A (en) | 2014-05-06 | 2015-05-04 | Apparatus and method for performing multiple memory operations |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910855051.5A Withdrawn CN110751973A (en) | 2014-05-06 | 2015-05-04 | Apparatus and method for performing multiple memory operations |
Country Status (8)
| Country | Link |
|---|---|
| US (5) | US9384830B2 (en) |
| EP (1) | EP3140833A4 (en) |
| JP (2) | JP6434535B2 (en) |
| KR (2) | KR102097228B1 (en) |
| CN (2) | CN106463172B (en) |
| SG (1) | SG11201608934PA (en) |
| TW (1) | TWI576841B (en) |
| WO (1) | WO2015171522A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20190035470A1 (en) | 2019-01-31 |
| EP3140833A4 (en) | 2018-01-10 |
| EP3140833A1 (en) | 2017-03-15 |
| SG11201608934PA (en) | 2016-11-29 |
| US20190244667A1 (en) | 2019-08-08 |
| US20170256319A1 (en) | 2017-09-07 |
| KR20180137601A (en) | 2018-12-27 |
| CN110751973A (en) | 2020-02-04 |
| US10068649B2 (en) | 2018-09-04 |
| US20160351263A1 (en) | 2016-12-01 |
| US9384830B2 (en) | 2016-07-05 |
| US10529428B2 (en) | 2020-01-07 |
| KR101935119B1 (en) | 2019-01-03 |
| CN106463172B (en) | 2019-10-08 |
| TW201611002A (en) | 2016-03-16 |
| JP6853611B2 (en) | 2021-03-31 |
| TWI576841B (en) | 2017-04-01 |
| JP2019049976A (en) | 2019-03-28 |
| US10311957B2 (en) | 2019-06-04 |
| JP2017524997A (en) | 2017-08-31 |
| KR20160144415A (en) | 2016-12-16 |
| US9685234B2 (en) | 2017-06-20 |
| KR102097228B1 (en) | 2020-05-28 |
| US20150325288A1 (en) | 2015-11-12 |
| JP6434535B2 (en) | 2018-12-05 |
| WO2015171522A1 (en) | 2015-11-12 |
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