CN106449759B - Isolated form LDMOS structure and its manufacturing method - Google Patents

Abstract

The present invention provides a kind of isolated form LDMOS structure and its manufacturing method, including the isolation moat structure being integrated on same P type substrate substrate and LDMOS structure；Isolation moat structure is located inside the P type substrate between the second p-type heavily doped region of LDMOS structure and p-type diffusion well region, isolation moat structure includes the first oxide layer of at least one slot, the filled media inside slot, the first area P of trench bottom, groove edge, and slot upper surface is the third oxide layer of LDMOS；The present invention injects semiconductor impurities identical with substrate material doping type in isolation trench bottom, it solves source surface and shifts to an earlier date breakdown problem, further increase breakdown voltage, meanwhile slot isolation helps to inhibit the horizontal expansion of LDMOS well region, reduces device area size, the present invention changes the field distribution close to source, drift doping concentration is improved, and then improves device pressure resistance and reduces than conducting resistance, has been advanced optimized than conducting resistance and breakdown voltage relationship.

Description

Isolated LDMOS structure and manufacturing method thereof

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to an isolated LDMOS structure and a manufacturing method thereof.

Background technique

LDMOS (Lateral Double-Diffused MOSFET) is a commonly used semiconductor device, which has the advantages of high power gain, high efficiency and low cost, and is widely used in semiconductor technology. In order to improve the LDMOS breakdown voltage and increase the output power, the method of increasing the length of the drift region and reducing the doping concentration of the drift region is usually used, which will lead to an increase in the specific on-resistance of the device and increase power consumption. Since the introduction of RESURF technology and slot isolation technology, improved structures such as Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURFLDMOS, and SJ LDMOS have had a significant effect on reducing the specific on-resistance. However, this type of structure cannot completely improve the electric field distribution problem in the device body, and there is still a problem of contradiction between the device withstand voltage and the on-resistance.

SUMMARY OF THE INVENTION

Aiming at the contradictory relationship between LDMOS breakdown voltage and specific on-resistance, the invention proposes an isolated LDMOS structure and a manufacturing method thereof.

In order to realize the foregoing invention object, the technical scheme of the present invention is as follows:

An isolated LDMOS structure, comprising an isolation trench structure and an LDMOS structure integrated on the same P-type substrate; the isolation trench structure is located between the second P-type heavily doped region and the P-type diffused well region of the LDMOS structure Inside the P-type substrate, the isolation trench structure includes at least one trench, a filling medium inside the trench, a first P region at the bottom of the trench, and a first oxide layer on the edge of the trench, the first oxide layer is used for filling the interior of the isolation trench The semiconductor silicon material outside the medium and the groove, and the upper surface of the groove is the third oxide layer of LDMOS.

As a preferred manner, the LDMOS structure is one of Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, and SJ LDMOS.

As a preferred manner, the LDMOS structure includes a P-type substrate, an N-type diffused well region, a P-type diffused well region, a second P region, a first P-type heavily doped region, a second P-type heavily doped region, a An N-type heavily doped region, a second N-type heavily doped region, a second oxide layer, a third oxide layer, a gate, a source electrode, a drain electrode, a substrate electrode, and a body electrode; the N-type diffused well The region is located in the P-type substrate and its upper surface is flush with the upper surface of the P-type substrate, and the P-type diffused well region, the second P region, and the second N-type heavily doped region are all located in the N-type diffused well region And its upper surface is flush with the upper surface of the N-type diffused well region, the second P region is located between the P-type diffused well region and the second N-type heavily doped region, the first P-type heavily doped region, The first N-type heavily doped region is located in the P-type diffused well region and its upper surface is flush with the upper surface of the P-type diffused well region, and the second P-type heavily doped region is located in the P-type substrate and on it The surface is flush with the upper surface of the P-type substrate, and the third oxide layer is located between the P-type diffused well region and the second N-type heavily doped region and covers the surface of the N-type diffused well region and the second P-region, so The second oxide layer is located between the first N-type heavily doped region and the third oxide layer and covers the surface of the P-type diffused well region, the gate is located on the upper surface of the second oxide layer, and the source is connected to the first The potential of the N-type heavily doped region, the drain is connected to the potential of the second N-type heavily doped region, the substrate electrode is connected to the potential of the second P-type heavily doped region, and the body electrode is connected to the first P-type heavily doped region. Potential of the doped region.

As a preferred manner, the depth of the groove is greater than that of the N-type diffusion well region.

As a preferred manner, the depth of the groove is 1 μm˜3 μm greater than that of the N-type diffusion well region. This enables better isolation, reduces substrate leakage, and improves the electric field near the source region.

As a preferred manner, the dose of P-type impurities implanted at the bottom of the trench is greater than 10 ¹² cm ^-2 . This enables better isolation, reduces substrate leakage, and improves the electric field near the source region.

As a preferred manner, the shape of the groove is one or more of strip shape, trapezoid shape, inverted trapezoid shape and step shape.

As a preferred manner, the sidewall of the trench on one side of the LDMOS structure is implanted with N-type impurities by oblique injection.

As a preferred manner, each doping type in the device is correspondingly changed to the opposite doping type, that is, when P-type doping changes to N-type doping, N-type doping changes to P-type doping.

In order to achieve the purpose of the above invention, the present invention also provides a method for manufacturing the above isolated LDMOS structure, comprising the following steps:

Step 1: Using a P-type silicon wafer as a substrate;

Step 2: forming isolation grooves, groove side walls and bottom oxidation;

Step 3: P-type impurities are injected into the bottom of the tank;

Step 4: Fill the tank with medium;

Step 5: Pre-oxidation, photolithography of the window of the N-type diffused well area, implantation of the N-type diffused well area, pushing the junction, and etching the redundant oxide layer;

Step 6: LDMOS Manufacturing Process.

Aiming at the contradictory relationship between LDMOS breakdown voltage and specific on-resistance, the invention proposes an isolated LDMOS structure and a manufacturing method thereof. The semiconductor device of the present invention injects semiconductor impurities of the same doping type as the substrate material at the bottom of the isolation groove, so as to solve the problem of early breakdown on the surface of the source end and further improve the breakdown voltage. At the same time, the trench isolation helps to suppress the lateral expansion of the LDMOS well region and reduce the device area size. The invention changes the electric field distribution close to the source end, increases the doping concentration of the drift region, further improves the withstand voltage of the device, reduces the specific on-resistance, and further optimizes the relationship between the specific on-resistance and the breakdown voltage.

The beneficial effects of the present invention are:

1. An isolated LDMOS structure of the present invention injects semiconductor materials of the same doping type as the substrate at the bottom of the isolation trench to assist the depletion of the drift region, reduce the surface electric field near the source end, and prevent premature breakdown on the surface near the source end. Compared with the traditional trench isolation LDMOS structure, the trench depth is shallower, and the process implementation difficulty and cost are reduced;

2. The isolation groove of an isolated LDMOS structure of the present invention can suppress the lateral expansion of the N-type well region, reduce the area size, and at the same time, increase the concentration near the boundary of the isolation groove on the side of the N-type well region, and increase the vertical withstand voltage near the source region ;

3. The isolation groove of an isolation type LDMOS structure of the present invention can prevent crosstalk between high-voltage integrated circuit devices, and the semiconductor material with the same doping type as the substrate is implanted at the bottom to reduce substrate leakage.

4. The isolation groove of an isolated LDMOS structure of the present invention can be integrated with LDMOSs of different structures, further optimizing the relationship between the breakdown voltage and the specific on-resistance.

5. The isolation groove of an isolation type LDMOS structure of the present invention is obliquely implanted with N-type impurities on the side wall near the LDMOS structure, which can optimize the concentration of the well region near the groove boundary and improve the withstand voltage.

Description of drawings

FIG. 1 is a schematic structural diagram of an isolated LDMOS provided by the present invention.

Fig. 2 is a schematic diagram of process simulation of an embodiment of the present invention.

3(1) to 3(6) are schematic process flow diagrams of a method for manufacturing an isolated LDMOS structure provided by an embodiment of the present invention.

FIG. 4(1)-FIG. 4(6) are process simulation diagrams corresponding to the manufacturing process of the devices in FIG. 3(1)-FIG. 3(6).

FIG. 5 is a schematic diagram of various shapes of the groove 2 .

FIG. 6 is a schematic diagram of implanting N-type impurities into the sidewall of one side of the LDMOS structure by oblique injection.

Among them, 1 is the first P region, 2 is the groove, 3 is the first oxide layer, 4 is the second P region, 5 is the P-type substrate, 6 is the N-type diffused well region, 7 is the P-type diffused well region, 8 is the first P-type heavily doped region, 9 is the first N-type heavily doped region, 10 is the second N-type heavily doped region, 11 is the second P-type heavily doped region, 12 is the second oxide layer , 13 is the gate, 14 is the third oxide layer, 15 is the source, 16 is the drain, 17 is the substrate electrode, 18 is the body electrode, and 20 is the oblique injection N-type impurity region.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

An isolated LDMOS structure, including an isolation trench structure and an LDMOS structure integrated on the same P-type substrate 5; the isolation trench structure is located in the second P-type heavily doped region 11 and the P-type diffused well region of the LDMOS structure Inside the P-type substrate 5 between 7, the isolation groove structure includes at least one groove 2, a filling medium inside the groove 2, a first P region 1 at the bottom of the groove 2, and a first oxide layer 3 on the edge of the groove 2. An oxide layer 3 is used to isolate the filling medium inside the trench 2 from the semiconductor silicon material outside the trench 2 , and the upper surface of the trench 2 is a third oxide layer 14 of LDMOS.

The LDMOS structure is one of Single-RESURF LDMOS, Double RESURF LDMOS, Triple RESURF LDMOS, Multiple RESURF LDMOS, 3D RESURF LDMOS, and SJ LDMOS.

Preferably, the LDMOS structure includes a P-type substrate 5, an N-type diffused well region 6, a P-type diffused well region 7, a second P-region 4, a first P-type heavily doped region 8, a second P-type heavily doped region Impurity region 11, first N-type heavily doped region 9, second N-type heavily doped region 10, second oxide layer 12, third oxide layer 14, gate 13, source 15, drain 16, substrate electrode 17, body region electrode 18; the N-type diffused well region 6 is located in the P-type substrate 5 and its upper surface is flush with the upper surface of the P-type substrate 5; the P-type diffused well region 7, the second P Region 4 and the second N-type heavily doped region 10 are located in the N-type diffused well region 6 and their upper surfaces are flush with the upper surface of the N-type diffused well region 6, and the second P region 4 is located in the P-type diffused well region 7 and the second N-type heavily doped region 10, the first P-type heavily doped region 8 and the first N-type heavily doped region 9 are located in the P-type diffused well region 7 and their upper surfaces are all connected to the P The upper surface of the diffused well region 7 is flush, the second P-type heavily doped region 11 is located in the P-type substrate 5 and its upper surface is flush with the upper surface of the P-type substrate 5, and the third oxide layer 14 Located between the P-type diffused well region 7 and the second N-type heavily doped region 10 and covering the surface of the N-type diffused well region 6 and the second P region 4, the second oxide layer 12 is located in the first N-type heavily doped region Between the impurity region 9 and the third oxide layer 14 and covering the surface of the P-type diffused well region 7, the gate 13 is located on the upper surface of the second oxide layer 12, and the source 15 is connected to the first N-type heavily doped region 9 potential, the drain 16 is connected to the potential of the second N-type heavily doped region 10, the substrate electrode 17 is connected to the potential of the second P-type heavily doped region 11, and the body electrode 18 is connected to the potential of the first P-type heavily doped region. Doped region 8 potential.

Preferably, the depth of the trench 2 is greater than the depth of the N-type diffusion well region 6 by 1 μm˜3 μm. This enables better isolation, reduces substrate leakage, and improves the electric field near the source region.

The dose of P-type impurities injected into the bottom of the groove 2 is greater than 10 ¹² cm ^-2 . This enables better isolation, reduces substrate leakage, and improves the electric field near the source region.

As shown in FIG. 5 , the shape of the groove 2 is one or more of strip shape, inverted trapezoid shape, trapezoid shape and step shape.

Preferably, as shown in FIG. 6 , the sidewall of the trench 2 on one side of the LDMOS structure is implanted with N-type impurities by oblique injection to form an oblique N-type impurity region 20 .

The method for manufacturing the above isolated LDMOS structure includes the following steps:

Step 1: Using a P-type silicon wafer as a substrate;

Step 2: forming isolation grooves, groove side walls and bottom oxidation;

Step 3: injecting P-type impurities into the bottom of the groove; injecting N-type impurities into the side walls of the groove to form obliquely injected N-type impurity regions 20;

Step 4: Fill the tank with medium;

Step 5: Pre-oxidation, photolithography of the window of the N-type diffused well area, implantation of the N-type diffused well area, pushing the junction, and etching the redundant oxide layer;

Step 6: LDMOS Manufacturing Process.

As a modification, each doping type in the device is correspondingly changed to an opposite doping type, that is, when P-type doping is changed to N-type doping, N-type doping is changed to P-type doping.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications or changes to the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (9)

1. An isolation type LDMOS structure is characterized in that: comprise the isolation groove structure and the LDMOS structure integrated on the same P-type substrate (5) substrate; The isolation groove structure is located inside the P-type substrate (5) between the second P-type heavily doped region (11) and the P-type diffusion well region (7) of the LDMOS structure, and the isolation groove structure includes at least one groove (2 ), the filling medium inside the groove (2), the first P region (1) at the bottom of the groove (2), the first oxide layer (3) on the edge of the groove (2), and the first oxide layer (3) is used for The filling medium inside the isolation groove (2) is separated from the semiconductor silicon material outside the groove (2), and the upper surface of the groove (2) is a third oxide layer (14) of LDMOS; The LDMOS structure includes a P-type substrate (5), an N-type diffused well region (6), a P-type diffused well region (7), a second P-region (4), a first P-type heavily doped region (8) , the second P-type heavily doped region (11), the first N-type heavily doped region (9), the second N-type heavily doped region (10), the second oxide layer (12), the third oxide layer ( 14), gate (13), source (15), drain (16), substrate electrode (17), body region electrode (18); the N-type diffused well region (6) is located in the P-type substrate (5) and its upper surface is flush with the upper surface of the P-type substrate (5), the P-type diffused well region (7), the second P region (4), the second N-type heavily doped region (10 ) are located in the N-type diffused well region (6) and its upper surface is flush with the upper surface of the N-type diffused well region (6), and the second P region (4) is located between the P-type diffused well region (7) and the second P-type diffused well region (7). Between the two N-type heavily doped regions (10), the first P-type heavily doped region (8) and the first N-type heavily doped region (9) are located in the P-type diffused well region (7) and their The upper surfaces are all flush with the upper surface of the P-type diffused well region (7), and the second P-type heavily doped region (11) is located in the P-type substrate (5) and its upper surface is aligned with the P-type substrate (5). ) is flush with the upper surface, and the third oxide layer (14) is located between the P-type diffused well region (7) and the second N-type heavily doped region (10) and covers the N-type diffused well region (6), the second Two surfaces of the P region (4), the second oxide layer (12) is located between the first N-type heavily doped region (9) and the third oxide layer (14) and covers the P-type diffusion well region (7) surface, the gate (13) is located on the upper surface of the second oxide layer (12), the source (15) is connected to the potential of the first N-type heavily doped region (9), and the drain (16) is connected to The potential of the second N-type heavily doped region (10), the substrate electrode (17) is connected to the potential of the second P-type heavily doped region (11), and the body region electrode (18) is connected to the first P-type heavily doped region. Miscellaneous region (8) potential. 2. The isolated LDMOS structure according to claim 1, wherein the LDMOS structure is one of Single-RESURF LDMOS, Double-RESURF LDMOS, Triple-RESURF LDMOS, Multiple-RESURF LDMOS, 3DRESURF LDMOS, SJ LDMOS. 3. The isolated LDMOS structure according to claim 1, characterized in that: the depth of the trench (2) is greater than the depth of the N-type diffused well region (6). 4. The isolated LDMOS structure according to claim 3, characterized in that: the depth of the trench (2) is greater than the depth of the N-type diffusion well region (6) by 1 μm˜3 μm. 5. The isolated LDMOS structure according to claim 1, characterized in that: the dose of P-type impurities implanted into the bottom of the trench (2) is greater than 10 ¹² cm ^-2 . 6. The isolated LDMOS structure according to claim 1, characterized in that: the shape of the groove (2) is one or more of a strip shape, a trapezoid shape, an inverted trapezoid shape, and a step shape. 7. The isolated LDMOS structure according to claim 1, characterized in that: the sidewall of the groove (2) on one side of the LDMOS structure is implanted with N-type impurities by oblique injection. 8. The isolated LDMOS structure according to claim 1, characterized in that: each doping type correspondingly changes to the opposite doping type, that is, when P-type doping changes to N-type doping, N-type doping changes to It is P-type doped. 9. The method for manufacturing an isolated LDMOS structure according to any one of claims 1 to 8, characterized in that it comprises the following steps: Step 1: Using a P-type silicon wafer as a substrate; Step 2: forming isolation grooves, groove side walls and bottom oxidation; Step 3: P-type impurities are injected into the bottom of the tank; Step 4: Fill the tank with medium; Step 5: Pre-oxidation, photolithography of the window of the N-type diffused well area, implantation of the N-type diffused well area, pushing the junction, and etching the redundant oxide layer; Step 6: LDMOS Manufacturing Process.