CN106449611B

CN106449611B - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN106449611B
Application number: CN201610648773.XA
Authority: CN
Inventors: 麦可·凯利; 大卫·海纳; 罗纳·休莫勒; 罗杰·圣艾曼德
Original assignee: Amkor Technology Inc
Current assignee: Anrely Technology Singapore Holdings Pte Ltd
Priority date: 2015-08-11
Filing date: 2016-08-09
Publication date: 2022-10-04
Anticipated expiration: 2036-08-09
Also published as: KR101982905B1; CN106449611A; KR20170019298A; CN206040641U

Abstract

A semiconductor device. By way of non-limiting example, various features of this disclosure are to provide various semiconductor package structures, and methods for fabricating the same, that include a thin fine pitch redistribution structure.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The present invention relates to a semiconductor device.

Cross reference to/incorporation by reference of related applications

This application is related to U.S. patent application serial No. 13/753,120, filed on 29/1/2013 and entitled "semiconductor device and method of manufacturing a semiconductor device"; U.S. patent application Ser. No. 13/863,457, filed on 2013, 4, month 16 and entitled "semiconductor device and method of manufacturing the same"; 2013. U.S. patent application Ser. No. 14/083,779, filed on 19/11/year and entitled "semiconductor device with through-silicon-via-less deep well"; U.S. patent application Ser. No. 14/218,265 entitled "semiconductor device and method of manufacturing the same," filed 3/18/2014; U.S. patent application Ser. No. 14/313,724, entitled "semiconductor device and method of manufacturing the same," filed 24/6 2014; 2014. U.S. patent application Ser. No. 14/444,450, filed on 28/7/9/year and entitled "semiconductor device with thin redistribution layer"; U.S. patent application serial No. 14/524,443, entitled "semiconductor device with reduced thickness", filed on 27/10/2014; U.S. patent application Ser. No. 14/532,532, filed 11/4/2014 and entitled "interposer, method of manufacturing the same, semiconductor package using the same, and method for manufacturing the same"; U.S. patent application serial No. 14/546,484, entitled "semiconductor device with reduced warpage," filed on 11/18 2014; and U.S. patent application Ser. No. 14/671,095, filed 3/27/2015 and entitled "semiconductor device and method of manufacturing the same"; the contents of each of these U.S. patent applications are hereby incorporated by reference in their entirety.

Background

Current semiconductor packages and methods for forming semiconductor packages are inadequate, for example, resulting in excessive cost, lower reliability, or excessive package size. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such conventional and traditional approaches with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

Various features of the present disclosure provide a semiconductor device structure and a method for fabricating a semiconductor device. Various features of the present disclosure provide, by way of non-limiting example, various semiconductor package structures and methods for fabricating the same, including a thin fine pitch redistribution (redistribution) structure.

One aspect of the present invention is a semiconductor device including: a redistribution structure, comprising: a first redistribution layer, comprising: a first dielectric layer comprising a first dielectric material; and a first conductive line; and a second redistribution layer comprising: a second dielectric layer comprising a second dielectric material different from the first dielectric material; and a second electrically conductive trace electrically coupled to the first electrically conductive trace; a first semiconductor die attached to the first redistribution layer; a second semiconductor die attached to the first redistribution layer; and a conductive interconnect structure attached to the second redistribution layer.

Another aspect of the present invention is a semiconductor device including: a redistribution structure, comprising: an upper redistribution layer, comprising: a first dielectric layer comprising a first dielectric material; and a first conductive line; and an underlying redistribution layer comprising: a second dielectric layer comprising a second dielectric material; and a second conductive trace electrically coupled to the first conductive trace; a first semiconductor die attached to an upper side of the redistribution structure; a second semiconductor die attached to the upper side of the redistribution structure; a first molding material covering at least the upper side of the redistribution structure and a respective lateral side of each of the first and second semiconductor dies; a substrate comprising a substrate side attached to an upper side of a lower side of the redistribution structure; and a second molding material at least covering the upper substrate side, a lateral side of the first molding material, and a lateral side of the redistribution structure.

Another aspect of the present invention is a semiconductor device including: a redistribution structure, comprising: an upper redistribution layer comprising: a first dielectric layer comprising a first dielectric material; and a first electrically conductive line; an underlying redistribution layer comprising: a second dielectric layer comprising a second dielectric material; and a second electrically conductive line electrically coupled to the first electrically conductive line; and a plurality of conductive pillars extending from the underlying redistribution layer and attached to the second conductive lines; a first semiconductor die attached to an upper side of the redistribution structure; and a second semiconductor die attached to the upper side of the redistribution structure.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings are examples depicting the inventive content and together with the description serve to explain various principles of the inventive content. In the drawings:

fig. 1A-1J are cross-sectional views showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 2 is a flow chart of an exemplary method of fabricating a semiconductor package according to various features of the present disclosure.

Fig. 3A-3B are cross-sectional views showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package, depicting various features in accordance with the present disclosure.

Fig. 4A-4D are cross-sectional views showing an exemplary semiconductor package and an exemplary method of fabricating a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 5A-5F are cross-sectional views showing an exemplary semiconductor package and an exemplary method of fabricating a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 6A-6D are cross-sectional views showing an exemplary semiconductor package and an exemplary method of fabricating a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 7A-7L are cross-sectional views showing an exemplary semiconductor package and an exemplary method of fabricating a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 8 is a flow chart of an exemplary method of manufacturing a semiconductor package according to various features of the present disclosure.

Fig. 9 is a cross-sectional view showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 10A-10B are cross-sectional views showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package, depicting various features in accordance with the present disclosure.

Fig. 11A-11D are cross-sectional views showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package, depicting various features in accordance with the present disclosure.

Fig. 12A-12B are cross-sectional views showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package, depicting various features in accordance with the present disclosure.

Fig. 13 is a cross-sectional view showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 14 is a cross-sectional view showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 15 is a cross-sectional view showing an exemplary semiconductor package and an exemplary method of fabricating a semiconductor package depicting various features in accordance with the present disclosure.

Fig. 16 is a cross-sectional view showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package depicting various features in accordance with the present disclosure.

Detailed Description

The following discussion presents the features of the present invention by way of various examples thereof. Such examples are not limiting, and thus the scope of various features of this disclosure should not necessarily be limited by any particular characteristics of the examples provided. In the discussion that follows, the terms "for example," "such as," and "exemplary" are not limiting, and are generally synonymous with "exemplary and non-limiting," "for example and non-limiting," and the like.

As used herein, "and/or" means any one or more of the items added by "and/or" in the list. For example, "x and/or y" represents any element in the set of three elements { (x), (y), (x, y) }. In other words, "x and/or y" means "one or both of x and y". As another example, "x, y, and/or z" represents any one of the set of seven elements { (x), (y), (z), (x, y), (x, z), (y, z), (x, y, z) }. In other words, "x, y, and/or z" means "one or more of x, y, and z.

The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," and the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element, a first member, or a first segment discussed below could be termed a second element, a second member, or a second segment without departing from the teachings of the present disclosure. Similarly, various terms such as "above," "below," "side," and the like may be used in a relative manner to distinguish one element from another. However, it should be understood that the components may be oriented in different ways, e.g., a semiconductor device may be turned to the side so that its "top" surface is oriented horizontally and its "side" surface is oriented vertically, without departing from the teachings of the present disclosure.

Various features of the present disclosure provide a semiconductor device or package and a method of manufacturing (or fabricating) the same that may reduce cost, improve reliability, and/or improve manufacturability of the semiconductor device.

The above features and other features of the present disclosure will be described in, or are apparent from, the following description of various exemplary embodiments. Various features of this summary will now be presented with reference to the attached drawings, so that those skilled in the art can readily implement the various features.

Fig. 1A-1J are cross-sectional views showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package depicting various features in accordance with the present disclosure. The structures illustrated in FIGS. 1A-1J may share any or all of the features with similar structures shown in FIGS. 3A-3B, 4A-4D, 5A-5F, 6A-6D, 7A-7L, 9, 10A-10B, 11A-11D, 12A-12B, 13, 14, 15, and 16. Fig. 2 is a flow chart of an exemplary method 200 of fabricating a semiconductor package according to various features of the present disclosure. Fig. 1A-1J, for example, may depict a semiconductor package that is an example of various steps (or blocks) of the method 200 of fig. 2. FIGS. 1A-1J and FIG. 2 will now be discussed together. It should be noted that the order of the blocks of the example of the method 200 may be varied without departing from the scope of this disclosure.

The exemplary method 200 may include preparing a logic wafer for processing (e.g., for packaging) at block 205. Block 205 may include preparing a logical wafer for processing in any of a variety of ways, non-limiting of which are presented herein.

For example, block 205 may include receiving a logical wafer, such as from a supplier, from an upstream process at a manufacturing location, and so on. The logic wafer may comprise, for example, a semiconductor wafer that includes a plurality of active semiconductor dies. The semiconductor die may include, for example, a processor die, memory die, programmable logic die, application specific integrated circuit die, general logic die, and the like.

Block 205 may include, for example, forming conductive interconnect structures on the logic wafer. Such conductive interconnect structures may include, for example, conductive pads, lands, bumps or balls, conductive pillars, and the like. The forming may include, for example, attaching a pre-formed interconnect structure to the logic wafer, plating an interconnect structure on the logic wafer, and so forth.

In an exemplary embodiment, the conductive structures may include conductive pillars (including copper and/or nickel) and may include a solder cap (e.g., including tin and/or silver). For example, a conductive structure including a conductive post may include: (a) An under bump metallization ("UBM") structure comprising (i) a titanium-Tungsten (TiW) layer formed by sputtering, which may be referred to as a "seed layer," and (ii) a copper (Cu) layer formed by sputtering on the titanium-tungsten layer; (b) a copper pillar formed on the UBM by electroplating; and (c) a solder layer formed on the copper pillar, or a nickel layer formed on the copper pillar and a solder layer formed on the nickel layer.

Furthermore, in an exemplary embodiment, the conductive structures may include a lead and/or lead-free wafer bump. For example, lead-free wafer bumps (or interconnects) may be formed, at least in part, by: (a) Forming an Under Bump Metallization (UBM) structure by (i) forming a titanium (Ti) or titanium-Tungsten (TiW) layer by sputtering, (ii) forming a copper (Cu) layer on the Ti or Ti-tungsten layer by sputtering, (iii) and forming a nickel (Ni) layer on the copper layer by electroplating; and (b) forming a lead-free solder material by electroplating on the nickel layer of the UBM structure, wherein the lead-free solder material is of a composition having a 1-4% by weight of silver (Ag), and the remainder of the composition by weight is tin (Sn).

Block 205 may include, for example, performing partial or full thinning (e.g., grinding, etching, etc.) of the logic wafer. Block 205 may also include, for example, dicing the logical wafer into individual dies or groups of dies for subsequent mounting. Block 205 may also include receiving the logical wafer from a neighboring or upstream manufacturing station at a manufacturing facility, from another geographic location, and so on. The received logic wafer may, for example, be already prepared or additional preparation steps may be performed.

Generally, block 205 may include preparing a logic wafer for processing (e.g., for packaging). Thus, the scope of this disclosure should not be limited by characteristics of a particular type of logic wafer and/or die processing.

The exemplary method 200 may include preparing a carrier, substrate, or wafer at block 210. The prepared (or received) wafer may be referred to as a redistribution structure wafer or RD wafer. Block 210 may include preparing a RD wafer for processing in any of a variety of ways, non-limiting examples of which are presented herein.

The RD wafer may include, for example, an interposer wafer, a wafer of package substrates, and so forth. The RD wafer may, for example, include a redistribution structure formed (e.g., on a die-by-die basis) on a semiconductor (e.g., silicon) wafer. The RD wafer may, for example, include only electrical paths and no electronic devices (e.g., semiconductor devices). The RD wafer may also include passive electronic devices, but does not include active semiconductor devices, for example. For example, the RD wafer may include one or more conductive layers or lines formed on (e.g., directly or indirectly on) or coupled to a substrate or carrier. Examples of the carrier or substrate may include a semiconductor (e.g., silicon) wafer or a glass substrate. Examples of processes used to form conductive layers (e.g., copper, aluminum, tungsten, etc.) on a semiconductor wafer include processes utilizing semiconductor wafers, which may also be referred to herein as back end of line (BEOL). In an exemplary embodiment, the conductive layers may be deposited on or over a substrate using a sputtering and/or electroplating process. The conductive layers may be referred to as redistribution layers. The redistribution layers may be used to route an electrical signal between two or more electrical connections and/or route an electrical connection into a wider or narrower pitch.

In an example implementation, various portions of the redistribution structures (e.g., interconnect structures (e.g., planes, lines, etc.) that may be attached to an electronic device) may be formed with a sub-micron pitch (or center-to-center spacing) and/or a pitch less than 2 microns. In various other embodiments, a pitch of 2-5 microns may be utilized.

In an example embodiment, a silicon wafer on which the redistribution structure is formed may comprise lower grade silicon than can be fully utilized to form the semiconductor die to which the redistribution structure is ultimately attached. In another exemplary embodiment, the silicon wafer may be a recycled silicon wafer from a failed semiconductor device wafer fabrication. In another exemplary embodiment, the silicon wafer may include a thinner layer of silicon than can be fully utilized to form the semiconductor die that is ultimately attached to the redistribution structure. Block 210 may also include receiving the RD wafer from a neighboring or upstream manufacturing station at a manufacturing facility, from another geographic location, and so on. The received RD wafer may, for example, be already prepared or additional preparation steps may be performed.

FIG. 1A is a diagram providing an example of various features of block 210. Referring to fig. 1A, the RD wafer 100A may include, for example, a support layer 105 (e.g., a silicon or other semiconductor layer, a glass layer, etc.). A Redistribution (RD) structure 110 may be formed on the support layer 105. The RD structure 110 may include, for example, a base dielectric layer 111, a first dielectric layer 113, first conductive traces 112, a second dielectric layer 116, second conductive traces 115, and interconnect structures 117.

The base dielectric layer 111 may be, for example, on the support layer 105. The base dielectric layer 111 may comprise, for example, an oxide layer, a nitride layer, or the like. The base dielectric layer 111 may be formed, for example, to specification and/or may be natural. The dielectric layer 111 may be referred to as a protection layer. For example, the dielectric layer 111 may be or include a silicon dioxide layer formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process.

The RD wafer 100A may also include first conductive traces 112 and a first dielectric layer 113, for example. The first conductive lines 112 may comprise, for example, a deposited conductive metal (e.g., copper, aluminum, tungsten, etc.). The conductive line 112 may be formed by sputtering and/or plating. The conductive lines 112 may be formed at a sub-micron or sub-two-micron pitch (or center-to-center spacing), for example. The first dielectric layer 113 can, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). Note that in various embodiments, the dielectric layer 113 may be formed before the first conductive traces 112, such as by forming holes that are then filled with the first conductive traces 112 or portions thereof. In one exemplary embodiment, such as one including copper conductive lines, a dual damascene process may be utilized to deposit the lines.

In an alternative assembly, the first dielectric layer 113 may comprise an organic dielectric material. For example, the first dielectric layer 113 may include bismaleimide/triazine (BT), phenolic resin (phenol resin), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, equivalents thereof, and compounds thereof, but the inventive concept is not limited thereto. The organic dielectric material may be formed in any of a variety of ways, such as Chemical Vapor Deposition (CVD). In such an alternative device, the first conductive traces 112 may be, for example, at a pitch (or center-to-center spacing) of 2-5 microns.

The RD wafer 100A may also include second conductive traces 115 and a second dielectric layer 116, for example. The second conductive lines 115 can include, for example, deposited conductive metal (e.g., copper, etc.). The second conductive lines 115 may, for example, be connected to respective first conductive lines 112 through respective conductive vias 114 (e.g., in the first dielectric layer 113). The second dielectric layer 116 can comprise, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer 116 may comprise an organic dielectric material. For example, the second dielectric layer 116 may include bismaleimide/triazine (BT), phenol resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, equivalents thereof, and compounds thereof, but the inventive concept is not limited thereto. The second dielectric layer 116 may be formed by a CVD process, for example, although the scope of the present disclosure is not limited in this respect.

Although two sets of dielectric layers and conductive lines are depicted in fig. 1A, it should be understood that the RD structure 110 of the RD wafer 100A may include any number of such layers and lines. For example, the RD structure 110 may include only one dielectric layer and/or multiple sets of conductive traces, three sets of dielectric layers and/or conductive traces, and so on.

As with the logic wafer preparation at block 205, block 210 may include forming interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) on a surface of the RD structure 110. An example of such an interconnect structure 117 is illustrated in fig. 1A, wherein the RD structure 110 includes an interconnect structure 117, which is illustrated as being formed on the front (or top) side of the RD structure 110 and electrically connected to respective second conductive lines 115 through conductive vias in the second dielectric layer 116. Such interconnect structures 117 may be utilized, for example, to couple the RD structure 110 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.).

The interconnect structures 117 may comprise, for example, any of a variety of conductive materials (e.g., any one or combination of copper, nickel, gold, etc.). The interconnect structures 117 may also include solder, for example.

Generally, block 210 may include preparing a redistribution structure wafer (RD wafer). Thus, the scope of this summary should not be limited by features of any particular manner of performing such preparation.

The exemplary method 200 may include forming an interconnect structure (e.g., a Through Mold Via (TMV) interconnect structure) on the RD wafer at block 215. Block 215 may include forming such an interconnect structure in any of a variety of ways.

The interconnect structures may include any of a variety of features. For example, the interconnect structures may include solder balls or bumps, multi-ball solder columns, elongated solder balls, metal (e.g., copper) core balls having a solder layer over a metal core, plated column structures (e.g., copper columns, etc.), wire structures (e.g., wire-bonded wires), and so forth.

The interconnect structures may include any of a variety of dimensions. For example, the interconnect structures may extend from the RD wafer to a height that is less than a height of electronic components coupled to the RD wafer (e.g., at block 220). Also for example, the interconnect structures may extend from the RD wafer to a height that is greater than or equal to a height of electronic components coupled to the RD wafer. The significance of this relative height will become apparent in the discussion herein (e.g., in the discussion of mold thinning, package stacking, top substrate attachment, formation of top redistribution structures, etc.). The interconnect structures may also be formed at various pitches (or center-to-center spacings), for example. For example, the interconnect structures (e.g., conductive pillars or pillars) may be plated and/or bonded at a pitch of 150-250 microns or less. Also for example, the interconnect structures (e.g., elongated and/or metal-filled solder structures) may be attached at a pitch of 250-350 microns or less. Also for example, the interconnect structures (e.g., solder balls) may be attached at a pitch of 350-450 microns or less.

Block 215 may include attaching the interconnect structures in any of a variety of ways. For example, block 215 may include reflow attaching interconnect structures on the RD wafer, plating interconnect structures on the RD wafer, wire bonding interconnect structures on the RD wafer, attaching pre-formed interconnect structures to the RD wafer using conductive epoxy, and so forth.

Fig. 1B is a diagram providing an example of various features of block 215 (e.g., features of interconnect structure formation). In the exemplary assembly 100B, interconnect structures 121 (e.g., solder balls) are attached (e.g., reflow attached, attached using a ball drop process of a solder, etc.) to the RD structures 110 of the RD wafer 100A.

Although two columns of interconnect structures 121 are shown, various embodiments may include a single column, three columns, or any number of columns. As will be discussed herein, various example implementations may not have such an interconnect structure 121, and thus block 215 may be included in example method 200.

It is noted that although in the exemplary method 200, the block 215 is performed prior to the wafer molding operation of block 230, the interconnect structures may alternatively be formed after the wafer molding operation (e.g., forming a via in the molding material and then filling such a via with a conductive material). It is also noted that block 215, as shown in fig. 2, may be performed, for example, after die attach operations of block 220, rather than before die attach.

Generally, block 215 may include forming interconnect structures on the RD wafer. Thus, the scope of this disclosure should not be limited by characteristics of the particular type of interconnect structure or by characteristics of any particular manner of forming such interconnect structures.

The example method 200 may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) at block 220. Block 220 may include attaching the die to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein.

The semiconductor die may include features of any of various types of semiconductor dies. For example, the semiconductor die may include a processor die, a memory die, an application specific integrated circuit die, a general logic die, active semiconductor components, etc.). It is noted that passive components may also be attached at block 220.

Block 220 may include attaching the semiconductor die in any of a variety of ways (e.g., as prepared at block 205). For example, block 220 may include attaching the semiconductor die using mass reflow (mass reflow), thermal Compression Bonding (TCB), conductive epoxy, and the like.

Fig. 1B is a diagram providing an example of various features of block 220, such as die attach features. For example, a first die 125 (e.g., which may have been diced from a logical wafer prepared at block 205) is electrically and mechanically attached to the redistribution structure 110. Similarly, second dies 126 (e.g., which may have been diced from a logical wafer prepared at block 205) are electrically and mechanically attached to the redistribution structure 110. For example, as illustrated at block 205, the logic wafer (or die thereof) may have been prepared with various interconnect structures (e.g., conductive pads, planes, bumps, balls, wafer bumps, conductive pillars, etc.) formed thereon. Such a structure is shown generally in fig. 1B as item 119. Block 220 may, for example, comprise electrically and mechanically attaching such interconnect structures to the redistribution structure 110 using any of a variety of attachment processes (e.g., batch reflow, thermal Compression Bonding (TCB), conductive epoxy, etc.).

The first die 125 and the second die 126 may include any of a variety of die features. In an example scenario, the first die 125 may include a processor die and the second die 126 may include a memory die. In another example scenario, the first die 125 may include a processor die and the second die 126 may include a co-processor die. In another example scenario, the first die 125 may include a sensor die and the second die 126 may include a sensor processing die. Although the component 100B in fig. 1B is shown with two dies 125, 126, it may have any number of dies. For example, it may have only one grain, three grains, four grains, or more than four grains.

Furthermore, although the first die 125 and second die 126 are shown attached laterally to the redistribution structure 110 relative to each other, they may also be configured with a vertical component. Various non-limiting examples of such structures are shown and discussed herein (e.g., a stack of dies on a die, attachment of dies to opposing substrate sides, etc.). Further, although the first die 125 and the second die 126 are illustrated as having substantially similar dimensions, such dies 125, 126 may include different individual features (e.g., die height, footprint, connection pitch, etc.).

The first die 125 and the second die 126 are depicted as having a substantially uniform pitch, but this is not necessarily so. For example, most or all of the contacts 119 of the first die 125 in an area of the first die footprint proximate to the second die 126 and/or most of the contacts 119 of the second die 126 in an area of the second die footprint proximate to the first die 125 may have a substantially finer pitch than the other most or all of the contacts 119. For example, the contacts 119 in the front 5, 10, or n rows of the first die 125 closest to the second die 126 (and/or the second die 126 closest to the first die 125) may have a pitch of 30 microns, while the other contacts 119 may have a pitch of approximately 80 microns and/or 200 microns. The RD structures 110 may thus have corresponding contact structures and/or lines at the corresponding pitches.

Generally, block 220 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Thus, the scope of this disclosure should not be limited by the characteristics of any particular die, or by the characteristics of any particular multi-die layout, or by the characteristics of any particular manner of attaching such dies, etc.

The exemplary method 200 may include underfill (underfill) at block 225 attached to the semiconductor die and/or other components of the RD structure at block 220. Block 225 may include performing such underfill in any of a variety of ways, non-limiting examples of which are presented herein.

For example, after die attachment at block 220, block 225 can include underfilling the semiconductor die with a capillary underfill. For example, the underfill may comprise a sufficiently viscous reinforced polymeric material that flows between the attached die and the RD wafer in a capillary action.

Also for example, block 225 may include underfilling the semiconductor die with a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while the die is being attached (e.g., using a thermocompression bonding process) at block 220. For example, such underfill material may be deposited (e.g., printed, sprayed, etc.) prior to attaching the semiconductor die.

As with all blocks depicted in the exemplary method 200, block 225 may be performed anywhere in the flow of the method 200 as long as the space between the die and redistribution structure is accessible.

The underfill may also occur at a different block of the example method 200. For example, the underfill may be performed as part of the wafer mold block 230 (e.g., with a mold underfill).

Fig. 1B is a diagram providing an example of various features of block 225 (e.g., the underfill feature). The underfill 128 is disposed between the first semiconductor die 125 and the redistribution structure 110, and between the second semiconductor die 126 and the redistribution structure 110, for example, surrounding the contacts 119.

Although the underfill fill 128 is depicted as being substantially planar, the underfill fill may rise and form fillets (filets) on the sides of the semiconductor die and/or other components. In one exemplary scenario, at least one-quarter or at least one-half of the die side surfaces may be covered with the underfill material. In another example scenario, one or more or all of the entire side surfaces may be covered with the underfill material. Also for example, a substantial portion of the space directly between the semiconductor dies, between the semiconductor die and other components, and/or between other components may be filled with the underfill material. For example, at least half or all of the space between laterally adjacent semiconductor dies, between the die and other components, and/or between other components may be filled with the underfill material. In an exemplary embodiment, the underfill fill 128 may cover the entire redistribution structure 110 of the RD wafer. In such an exemplary embodiment, when the RD wafer is later diced, such dicing may also cut through the underfill 128.

Generally, block 225 may include underfill to fill the semiconductor die and/or other components attached to the RD structure at block 220. Thus, the scope of this disclosure should not be limited to any particular type of underfill filling or to the features of any particular manner of performing such underfill filling.

The exemplary method 200 may include molding the RD wafer (e.g., or an RD structure) at block 230. Block 230 may include molding the RD wafer in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 230 may include molding over a top surface of the RD wafer, over dice and/or other components to which block 220 is attached, over interconnect structures formed at block 215 (e.g., conductive balls, ellipsoids, pillars or pillars (e.g., plated pillars, wires or bond wires, etc.), over underfill fills formed at block 225, and so forth.

Block 230 may include, for example, using compression molding (e.g., using liquid, powder, and/or film), or vacuum molding. Also for example, block 230 may include utilizing a transfer molding process (e.g., a wafer level transfer molding process).

The molding material may include any of a variety of features, for example. For example, the molding material (e.g., epoxy Molding Compound (EMC), epoxy molding compound, etc.) may include a relatively high modulus, e.g., to provide wafer support during a subsequent process. Also for example, the molding material may include a relatively low modulus to provide wafer resiliency during a subsequent process.

As illustrated herein, the molding process of block 230 may provide an underfill fill between the die and the RD wafer, for example, with respect to block 225. In such instances, there may be a uniform material between the molded underfill material and the molding material encapsulating the semiconductor die.

Fig. 1C is a diagram providing an example of various features (e.g., molding features) of block 230. For example, the molding assembly 100C is illustrated with the molding material 130 covering the top surfaces of the interconnect structures 121, the first semiconductor die 125, the second semiconductor die 126, the underfill 128, and the redistribution structure 110. Although the molding material 130 (which may also be referred to herein as an encapsulation material) is shown to completely cover the sides and top of the first and second semiconductor dies 125, 126, this need not be the case. For example, block 230 may include molding techniques that utilize a film assist or die seal to keep the top of the die free of molding material.

Generally, the molding material 130 may, for example, directly contact and cover portions of the dies 125, 126 not covered by the underfill 128. For example, in a scenario in which at least a first portion of the sides of the dies 125, 126 are covered by the underfill 128, the molding material 130 may directly contact and cover a second portion of the sides of the dies 125, 126. The molding material 130 may also, for example, fill in the space between the dies 125, 126 (e.g., at least a portion of the space that has not been filled with the underfill 128).

Generally, block 230 may include molding the RD wafer. Thus, the scope of this disclosure should not be limited by characteristics of any particular molding material, structure, and/or technique.

The exemplary method 200 may include grinding (or otherwise thinning) the molding material applied at block 230 at block 235. Block 235 may include grinding (or thinning) the molding material in any of a variety of ways, non-limiting examples of which are presented herein.

Block 235 may, for example, comprise mechanically grinding the molding material to thin the molding material. Such thinning may, for example, leave the die and/or interconnect structure overmolded, or may expose one or more dies and/or one or more interconnect structures.

The block 235 may, for example, include grinding other components in addition to the molding compound. For example, block 235 may include grinding on a top side (e.g., a back side or an inactive side) of a die to which block 220 is attached. Block 235 may also include, for example, polishing the interconnect structures formed in block 215. In addition, in a scenario where the underfill applied in block 225 or block 230 is sufficiently extended upward, block 235 may also include polishing such underfill material. Such polishing can, for example, produce a flat planar surface on top of the material being polished.

Block 235 may be skipped, for example, in a scenario where the height of the molding material was originally formed at a desired thickness.

Fig. 1D is a diagram providing an example of various features of block 235 (e.g., the molded abrasive feature). Component 100D is depicted wherein the molding material 130 (e.g., relative to molding material 130 depicted in fig. 1C) is thinned to expose the top surfaces of the

dice

125, 126. In this case, the dies 125, 126 may also have been ground (or thinned).

Although the top surface of the molding material is above the interconnect structures 121, and thus the interconnect structures 121 are not polished, as depicted in fig. 1D, the interconnect structures 121 may also be polished. Such an exemplary embodiment may, for example, produce a top surface at this stage that includes a top surface of the

dice

125, 126, a top surface of the molding material 130, and a top surface of the interconnect structure 121, all on a common plane.

As illustrated herein, the molding material 130 may be retained to cover the dies 125, 126 in an over mold (over mold) configuration. For example, the molding material 130 may not be ground, or the molding material 130 may be ground, but not to a height that exposes the

die

125, 126.

Generally, block 235 may include grinding (or otherwise thinning) the molding material applied at block 230. Thus, the scope of this disclosure should not be limited by the amount or type of any particular grinding (or thinning) feature.

The exemplary method 200 may include, at block 240, ablating the molding material applied at block 230. Block 240 may include ablating the molding material in any of a variety of ways, non-limiting examples of which are provided herein.

As discussed herein, the molding material may cover the interconnect structure formed at block 215. If the molding material covers interconnect structures and the interconnect structures need to be exposed (e.g., for subsequent package attachment, redistribution layer formation on the top side, laminate substrate attachment on the top side, electrical connections, heat spreader connections, connections for electromagnetic shielding, etc.), block 240 may include ablating the molding material to expose the connection structures.

Block 240 may include exposing the interconnect structures through the molding material, for example, using laser ablation. Also for example, block 240 may include drilling with soft beams, mechanical drilling, chemical drilling, and the like.

Fig. 1D is a diagram providing an example of various features of the block 240, such as the ablation feature. For example, the component 100D is shown to include an ablated via 140 extending through the molding material 130 to the interconnect structure 121. Although the ablated vias 140 are shown as having vertical sidewalls, it should be understood that the vias 140 can comprise any of a variety of shapes. For example, the sidewalls may be sloped (e.g., have a larger opening at the top surface of the molding material 130 than at the interconnect structure 121).

Although block 240 is depicted in fig. 2 as being immediately after wafer molding of block 230 and molding grinding of block 235, block 240 may be performed at any point later in the method 200. For example, block 240 may be performed after the wafer support structure (e.g., attached at block 245) is removed.

Generally, block 240 may include ablating the molding material applied at block 230 (e.g., to expose the interconnect structures formed at block 215). Thus, the scope of this disclosure should not be limited by the features of any particular manner of performing such ablation, or by the features of any particular ablated via structure.

The example method 200 may include, at block 245, attaching the molded RD wafer (e.g., the top or molded side thereof) to a wafer support structure. Block 245 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, non-limiting examples of which are provided herein.

The wafer support structure may include, for example, a wafer or fixture formed of silicon, glass, or various other materials (e.g., dielectric materials). Block 245 may include, for example, attaching the molded RD wafer to the wafer support structure using an adhesive, a vacuum fixture, or the like. Note that as depicted and described herein, a redistribution structure may be formed on the top side (or back side) of the die and molding material prior to attachment of the wafer support.

Fig. 1E is a diagram providing an example of various features of block 245, such as wafer support attachment features. A wafer support structure 150 is attached to the molding material 130 and to the top side of the dies 125, 126. The wafer support structure 150 may be attached, for example, using an adhesive, and such adhesive may also be formed in the vias 140 and contact the interconnect structures 121. In another example assembly, the adhesive does not enter via 140 and/or does not contact interconnect structure 121. Note that in an assembly in which the top of the dies 125, 126 are covered with molding material 130, the wafer support structure 150 may only be directly coupled to the top of the molding material 130.

Generally, block 245 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Thus, the scope of this disclosure should not be limited by features of any particular type of wafer support structure, or by features of any particular manner of attaching a wafer support structure.

The exemplary method 200 may include removing a support layer from the RD wafer at block 250. Block 250 may include removing the support layer in any of a variety of ways, non-limiting examples of which are presented herein.

As discussed herein, the RD wafer may include a support layer on which an RD structure is formed and/or supported. The support layer may comprise, for example, a semiconductor material (e.g., silicon). In an example scenario in which the support layer comprises a silicon wafer layer, block 250 may comprise removing the silicon (e.g., removing all of the silicon from the RD wafer, removing substantially all of the silicon (e.g., at least 90% or 95%) from the RD wafer, etc.). For example, block 250 may include mechanically polishing substantially all of the silicon, followed by a dry or wet chemical etch to remove the remaining portion (or substantially all of the remaining portion). In an example scenario where the support layer is loosely attached to the RD structure formed (or carried) thereon, block 250 may include pulling or peeling apart the support layer and the RD structure.

Fig. 1F is a diagram providing an example of various features of the block 250, such as a support layer removal feature. For example, the support layer 105 (shown in fig. 1E) is removed from the RD structure 110. In the illustrated example, the RD structure 110 may still include a base dielectric layer 111 (e.g., an oxide, nitride, etc.) as discussed herein.

Generally, block 250 may include removing a support layer from the RD wafer. Thus, the scope of this disclosure should not be limited to features of any particular type of wafer material, or to features of any particular manner of removal of wafer material.

The exemplary method 200 may include forming and patterning a dielectric layer of a first redistribution layer (RDL) for etching an oxide layer of the RD structure at block 255. Block 255 may include forming and patterning the first RDL dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein.

In examples generally discussed herein, the RD structure of the RD wafer is generally formed on an oxide layer (or nitride or other dielectric). To enable metal-to-metal attachment to the RD structure, the portion of the oxide layer covering the lines (or pads or planes) of the RD structure may be removed, for example, by etching. Note that the oxide layer does not necessarily need to be removed or completely removed, so long as it has acceptable conductivity.

The first RDL dielectric layer may comprise, for example, a polyimide or a Polybenzoxazole (PBO) material. The first RDL dielectric layer may comprise, for example, a laminated film or other material. The first RDL dielectric layer may, for example, substantially comprise an organic material. However, in various exemplary embodiments, the first RDL dielectric layer may include an inorganic material.

In an exemplary embodiment, the first RDL dielectric layer may comprise an organic material (e.g., polyimide, PBO, etc.) formed on a first side of a base dielectric layer of the RD structure, which may comprise an oxide or nitride or other dielectric material.

The first RDL dielectric layer may be utilized, for example, as a mask for etching a base dielectric layer, such as an oxide or nitride layer (e.g., at block 260). Also for example, after etching, the first RDL dielectric layer may remain, for example, utilized to form conductive RDL lines thereon.

In an alternative exemplary scenario (not shown), a temporary masking layer (e.g., a temporary photoresist layer) may be utilized. For example, after etching, the temporary shield layer may be removed and replaced with a permanent RDL dielectric layer.

FIG. 1G is a diagram providing an example of various features of block 255. For example, the first RDL dielectric layer 171 is formed and patterned on the base dielectric layer 111. The patterned first RDL dielectric layer 171 may, for example, include a via 172 through the first RDL dielectric layer 171, while the base dielectric layer 111 may, for example, be etched through via 172 (e.g., at block 260), and a first line (or portion thereof) may be formed in via 172 (e.g., at block 265).

Generally, block 255 may include, for example, forming and patterning a first dielectric layer (e.g., a first RDL dielectric layer) on the base dielectric layer. Thus, the scope of the present disclosure should not be limited by characteristics of a particular dielectric layer or by characteristics of a particular manner of forming a dielectric layer.

The exemplary method 200 may include, at block 260, etching the base dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, such as an unmasked portion thereof. Block 260 may include performing the etch in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 260 may include performing a dry etch process (or a wet etch process) to etch through portions of the base dielectric layer (e.g., oxide, nitride, etc.) exposed by vias through the first dielectric layer, which acts as a shield for the etch.

Fig. 1G is a diagram providing an example of various features (e.g., dielectric etch features) of block 260. For example, the portion of the base dielectric layer 111 that is shown in fig. 1F under the first conductive lines 112 is removed from fig. 1G. This enables, for example, a metal-to-metal contact between the first conductive line 112 and the first RDL line formed at block 265.

Generally, block 260 may include, for example, etching the base dielectric layer. Thus, the scope of this disclosure should not be limited to any particular manner of performing such etching.

The exemplary method 200 may include forming a first redistribution layer (RDL) line at block 265. Block 265 may include forming the first RDL line in any of a variety of ways, non-limiting examples of which are presented herein.

As discussed herein, the first RDL dielectric layer (e.g., formed at block 255) may be utilized for etching (e.g., at block 260) and then retained for formation of the first RDL lines. Alternatively, the first RDL dielectric layer may be formed and patterned after the etching process. In yet another alternative embodiment discussed herein, the etch process for the base dielectric layer may be skipped, for example, in an embodiment where the base dielectric layer (e.g., a thin oxide or nitride layer) is sufficiently conductive to adequately act as a conductive path between metal lines.

Block 265 may include forming the first RDL line to attach to a first conductive line of the RD structure exposed through the patterned first RDL dielectric layer. The first RDL line may also be formed on the first RDL dielectric layer. Block 265 may include forming the first RDL line in any of a variety of ways, such as by electroplating, although the scope of this disclosure is not limited to the features of any particular way of forming such a line.

The first RDL lines may comprise any of a variety of materials (e.g., copper, gold, nickel, etc.). The first RDL line may include, for example, any of a variety of sized features. A typical pitch for the first RDL line may be, for example, 5 microns. In an exemplary embodiment, the first RDL lines may be formed, for example, at a center-to-center spacing that is about or at least an order of magnitude greater than a spacing (e.g., at a sub-micron spacing, at a spacing of about 0.5 micron, etc.) at which various lines of RD structures of the RD wafer are formed.

Fig. 1G and 1H are diagrams providing an example of various features (e.g., RDL line formation features) of block 265. For example, a first portion 181 of a first RDL line may be formed in a via 172 of the first RDL dielectric layer 171 and contact the first conductive line 112 of the RD structure 110 exposed by such via 172. Also for example, a second portion 182 of the first RDL line may be formed on the first RDL dielectric layer 171.

Generally, block 265 may include forming a first redistribution layer (RDL) line. Thus, the scope of this disclosure should not be limited by characteristics of any particular RDL line, or by characteristics of any particular manner of forming such RDL lines.

The exemplary method 200 at block 270 may include forming and patterning a second RDL dielectric layer over the first RDL lines (e.g., formed at block 265) and the first RDL dielectric layer (e.g., formed at block 255). Block 270 may include forming and patterning the second dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 270 may share any or all of the features with block 255. The second RDL dielectric layer may be formed, for example, using the same material as the first RDL dielectric layer formed at block 255.

The second RDL dielectric layer may comprise, for example, a polyimide or a Polybenzoxazole (PBO) material. The second RDL dielectric layer may, for example, substantially comprise an organic material. However, in various exemplary embodiments, the first RDL dielectric layer may include an inorganic material.

FIG. 1H is a diagram providing an example of various features of block 270. For example, the second RDL dielectric layer 183 is formed on the

first RDL lines

181, 182 and on the first RDL dielectric layer 171. As shown in FIG. 1H, a via 184 is formed in the second RDL layer 183, and a conductive contact may be made through the via 184 to the first RDL line 182 exposed by such via 184.

Generally, block 270 may include forming and/or patterning a second RDL dielectric layer. Thus, the scope of the present disclosure should not be limited by characteristics of any particular dielectric layer, or by characteristics of any particular manner of forming a dielectric layer.

The exemplary method 200 may include forming a second redistribution layer (RDL) line at block 275. Block 275 may include forming the second RDL line in any of a variety of ways, non-limiting examples of which are presented herein. Block 275 may, for example, share any or all of the features with block 265.

Block 275 may include forming second RDL lines attached to the first RDL lines (e.g., formed at block 265) exposed through vias in the patterned second RDL dielectric layer (e.g., formed at block 270). The second RDL lines may also be formed on the second RDL dielectric layer. Block 275 may include forming the second RDL lines in any of a variety of ways, such as by electroplating, although the scope of this disclosure is not limited to any particular manner of features.

As with the first RDL lines, the second RDL lines may comprise any of a variety of materials (e.g., copper, etc.). Further, the second RDL line may include any of a variety of sized features, for example.

FIGS. 1H and 1I are diagrams providing an example of various features of block 275. For example, the second RDL lines 191 may be formed within the via 184 in the second RDL dielectric layer 183 to contact the first RDL line 181 exposed through such via 184. In addition, the second RDL line 191 may be formed on the second RDL dielectric layer 183.

Generally, block 275 may include forming second redistribution layer (RDL) lines. Thus, the scope of this disclosure should not be limited by characteristics of any particular RDL line, or by characteristics of any particular manner of forming such RDL lines.

The exemplary method 200 may include, at block 280, forming and patterning a third RDL dielectric layer over the second RDL line (e.g., formed at block 275) and the second RDL dielectric layer (e.g., formed at block 270). Block 280 may include forming and patterning the third dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein.

For example, block 280 may share any or all of the features with

blocks

270 and 255. The third RDL dielectric layer may be formed, for example, from the same material as the first RDL dielectric layer formed at block 255 (and/or after etching at block 260 and stripping a temporary mask layer), and/or from the same material as the second RDL dielectric layer formed at block 270.

The third RDL dielectric layer may comprise, for example, a polyimide or a Polybenzoxazole (PBO) material. The third RDL dielectric layer may, for example, substantially comprise an organic material. However, in various exemplary embodiments, the third RDL dielectric layer may include an inorganic material.

FIG. 1I is a diagram providing an example of various features of block 280. For example, the third RDL layer 185 may be formed on the second RDL lines 191 and on the second RDL layer 183. As shown in fig. 1I, vias are formed in the third RDL layer 185, through which vias conductive contacts can be made to the second RDL line 191 exposed by such vias.

Generally, block 280 may include forming and/or patterning a third RDL dielectric layer. Thus, the scope of this disclosure should not be limited by characteristics of any particular dielectric layer, or by characteristics of any particular manner of forming a dielectric layer.

The exemplary method 200 may include forming an interconnect structure on the second RDL lines, and/or on the third RDL dielectric layer at block 285. Block 285 may include forming the interconnect structures in any of a variety of ways, non-limiting examples of which are presented herein.

Block 285 may, for example, comprise forming an under bump (underbump) metal on the portion of the second RDL line exposed through the via in the third dielectric layer. Region 285 may then, for example, include attaching a conductive bump or ball to the underbump metallization. Other interconnect structures may also be utilized, examples of which are presented herein (e.g., conductive pillars or columns, solder balls, solder bumps, etc.).

Fig. 1I is a diagram providing an example of various features of block 285, such as features of interconnect structure formation. For example, interconnect structures 192 are attached to the second RDL lines 191 through vias formed in the third RDL dielectric layer 185. It is noted that although interconnect structures 192 are depicted as being smaller than interconnect structures 121, this disclosure is not so limited. For example, the interconnect structures 192 may be the same size as the interconnect structures 121 or larger than the interconnect structures 121. Furthermore, interconnect structures 192 may be the same type of interconnect structure as interconnect structure 121 or may be a different type.

Although the redistribution layers formed at blocks 255-285, which may also be referred to as front redistribution layers (RDLs), are depicted in fig. 1A-1J as substantially fan-out components (e.g., extending beyond the footprint of dies 125, 126), they may also be formed as fan-in components, e.g., where interconnect structure 192 does not extend substantially beyond the footprint of dies 125, 126. Non-limiting examples of such components are presented herein.

Generally, block 285 may include, for example, forming interconnect structures on the second RDL lines and/or on the third RDL dielectric layer. Thus, the scope of this disclosure should not be limited by characteristics of any particular interconnect structure or by any particular manner of forming an interconnect structure.

The exemplary method 200 may include debonding (or detaching) the wafer support attached at block 245 at block 290. Block 290 may include performing such debonding in any of a variety of ways, non-limiting features of which are presented herein.

For example, in an exemplary scenario in which the wafer support is adhesively attached, the adhesive may be released (e.g., using heat and/or force). Also for example, chemical release agents may be utilized. In another example scenario, where the wafer support is attached using a vacuum force, the vacuum force may be released. Note that in a scenario involving adhesive or other substances to facilitate installation of the wafer support, block 285 may include cleaning residues from the electrical components and/or from the wafer support after the debonding.

FIGS. 1I and 1J are diagrams providing an example of various features of block 290. For example, the wafer support 150 depicted in fig. 1I is removed in fig. 1J.

Generally, block 290 may include debonding the wafer support. Thus, the scope of this disclosure should not be limited by the characteristics of any particular type of wafer support, or by any particular manner of detackifying a wafer support.

The exemplary method 200 may include dicing the wafer at block 295. Block 295 may include dicing the wafer in any of a variety of ways, non-limiting examples of which are presented herein.

The discussion herein has generally focused on the processing of a single die of the RD wafer. This focusing on a single die of the RD wafer is for clarity of illustration only. It should be understood that all of the process steps discussed herein may be performed on an entire wafer. For example, each of the illustrations presented in FIGS. 1A-1J and other figures herein can be replicated tens or hundreds of times on a single wafer. For example, there may be no separation between one of the illustrated components of the wafer and an adjacent component prior to dicing.

Block 295 may include, for example, cutting (e.g., mechanical punch cutting, mechanical saw cutting, laser cutting, soft beam cutting, plasma cutting, etc.) individual packages from the wafer. The end result of such a cut may be, for example, the package shown in fig. 1J. For example, the cut may form a side surface of the package that is coplanar including a plurality of members of the package. For example, the side surfaces of any or all of the molding material 130, the dielectric layers of the RD structure 110, the various RDL dielectric layers, the underfill 128, and so on may be coplanar.

Generally, block 295 may include dicing the wafer. Thus, the scope of this disclosure should not be limited by features of any particular manner of dicing a wafer.

FIGS. 1A-1J and 2 illustrate various exemplary method features and variations thereof. Other exemplary method features will now be set forth with reference to the drawings.

As discussed herein, in the discussion of fig. 1A-1J and fig. 2, block 235 may include grinding (or otherwise thinning) the molding material 130 to expose one or more of the dies 125, 126. An example is provided in fig. 1D.

As also discussed, the molding grind (or thinning) at block 235 need not be performed, or may be performed to the extent that the tops of the

dice

125, 126 are still covered by the molding material 130. An example is provided in fig. 3A-3B. As shown in fig. 3A, the molding material 130 covers the top of the semiconductor dies 125, 126. Note that the interconnect structures 121 may be shorter or taller than the dies 125, 126. Continuing the comparison, rather than the resulting package 100J appearing as shown in fig. 1J, the resulting package 300B may appear as shown in fig. 3B.

Also, as discussed herein, in the discussion of fig. 1A-1J and fig. 2, the block 215 of forming the TMV interconnect structure and the block 240 of TMV mold degradation may be skipped. An example is provided in fig. 4A-4D. As shown in fig. 4A, TMV interconnect structure 121 is not formed relative to block 215 and fig. 1B. As shown in fig. 4B, the molding material 130 does not cover the interconnect structure, as opposed to block 230 and fig. 1C.

Continuing the comparison, as illustrated herein, the molding grind (or thinning) at block 235 may be performed to the extent that one or more of the top ends of the

dice

125, 126 are exposed from the molding material 130. Fig. 4C is a diagram providing an example of such processing. Generally, the element 400C of FIG. 4C is similar to the element 100J of FIG. 1J, minus the interconnect structures 121 and the ablated vias that pass through the molding material 130 to expose the interconnect structures.

Also for example, as illustrated herein, the molding grind (or thinning) at block 235 may be skipped or performed to the extent that the tops of the dies 125, 126 are covered with molding material 130. Fig. 4D is a diagram providing an example of such processing. Generally, the device 400D of fig. 4D is similar to the device 100J of fig. 1J, minus the interconnect structure 121 and the ablated via that passes through the molding material 130 to expose the interconnect structures, and wherein the molding material 130 covers the dies 125, 126.

In another example, as illustrated herein, in the discussion of block 215, the TMV interconnects may include any of a variety of structures, such as a conductive pillar (e.g., plated pillar or post, vertical conductive line, etc.). Fig. 5A is a diagram providing an example of conductive pillars 521 attached to the RD structure 110. The conductive pillars 521 may be, for example, electroplated on the RD structure 110. The conductive pillars 521 may also include, for example, wires (e.g., wire bonded wires) attached (e.g., wire bonded attachment, soldering, etc.) to the RD structure 110 and extending vertically. The conductive pillars 521 may extend from the RD structure 110 to a height that is greater than a height of the dies 125, 126, equal to a height of one or more of the dies 125, 126, less than a height of the dies 125, 126, etc. In an exemplary embodiment, the pillars may have a height greater than or equal to 200 microns and at a center-to-center spacing of 100-150 microns. Note that any number of columns of posts 521 may be formed. In general, the assembly 500A of fig. 5A is similar to the assembly 100B of fig. 1B, with the conductive pillars 521 serving as interconnect structures instead of the conductive balls 121.

Continuing with the example, fig. 5B depicts RD structure 110, conductive pillars 521, semiconductor dies 125, 126, and underfill 128 covered with molding material 130. The molding may be performed, for example, according to block 230 of the example method 200. In general, the assembly 500B of fig. 5B is similar to the assembly 100C of fig. 1C, with the conductive pillars 521 serving as interconnect structures instead of the conductive balls 121.

Continuing with the example, fig. 5C depicts the molding material 130 as having been thinned (e.g., ground) to a desired thickness. The thinning may be performed, for example, according to block 235 of the exemplary method 200. For example, it is noted that the conductive pillars 521 and/or the semiconductor dies 125, 126 may also be thinned. Generally, the device 500D of fig. 5D is similar to the device 100D of fig. 1D, wherein the conductive pillars 521 serve as interconnect structures instead of the conductive balls 121, and also do not have the ablated via 140 of fig. 1D. For example, the thinning of the molding material 130 may expose the tips of the conductive pillars 521. However, if the thinning of the molding material 130 does not expose the tips of the conductive posts 521, a molding ablation operation (e.g., according to block 240) may be performed. Note that although the device is shown with the top ends of the semiconductor dies 125, 126 exposed, the top ends need not be exposed. For example, the pillars 521 may be higher than the semiconductor dies 125, 126. Such an exemplary configuration may, for example, allow the posts 521 to be exposed from the molding material 130 and/or protrude from the molding material 130 while the molding material 130 continuously covers the back surface of the semiconductor dies 125, 126, which may, for example, provide protection to the semiconductor dies 125, 126 from or reduce warpage, etc.

In an exemplary embodiment in which the pillars 521 are formed with a height less than the

die

125, 126, the thinning may include first grinding the molding material 130, followed by grinding the molding material 130 and the backside (or inactive) side of the

die

125, 126 until the pillars 521 are exposed. At this point, the thinning may be stopped, or may continue, such as by grinding the molding material 130, the dies 125, 126, and the pillars 521.

Continuing with the example, the component 500C shown in fig. 5C may be further processed by forming a redistribution layer (RDL) 532 over the molding material 130 and dies 125, 126. Fig. 5D shows an example of such processing. The redistribution layer 532 may also be referred to herein as a backside Redistribution (RDL) layer 532. Although such formation of the backside RDL is not explicitly shown in any of the blocks of the example method 200, such an operation may be performed in any of the blocks, such as after the mold grinding operation of block 235 and before the wafer support attachment of block 245 (e.g., at block 235, at block 240, at block 245, or between any of such blocks).

As shown in fig. 5D, a first backside dielectric layer 533 may be formed and patterned over the molding material 130 and the dies 125, 126. The first backside dielectric layer 533 may be formed and patterned, for example, in the same or similar manner as the first RDL dielectric layer 171 formed at block 260, although the first RDL dielectric layer 171 is on a different surface. For example, the first backside dielectric layer 533 can be formed over the molding material 130 and over the semiconductor dies 125, 126 (e.g., directly over the exposed back surfaces of the dies 125, 126, over the molding material 130 covering the back surfaces of the dies 125, 126, etc.), and a via 534 can be formed (e.g., by etching, ablating, etc.) in the first backside dielectric layer 533 to at least expose the tops of the conductive posts 521. Note that in an exemplary configuration in which the molding material 130 covers the back surfaces of the semiconductor dies 125, 126, the first back side dielectric layer 533 may still be formed, but it is not necessary so (e.g., the back side line 535 discussed below may be formed directly on the molding material 130 instead of on the first back side dielectric layer 533).

A backside line 535 may be formed on the first backside dielectric layer 533 and in the via 534 of the first backside dielectric layer 533. The backside traces 535 may thus be electrically connected to the conductive pillar 521. The backside lines 535 may be formed, for example, in the same or similar manner as the first RDL line formed at block 265. At least some, if not all, of the backside lines 535, for example, can extend horizontally from the conductive pillar 521 to a location directly above the semiconductor die 125, 126. At least some of the backside traces 535, for example, may also extend from the conductive pillar 521 to locations other than directly above the semiconductor dies 125, 126.

A second backside dielectric layer 536 may be formed and patterned over the first backside dielectric layer 533 and backside lines 535. The second backside dielectric layer 536 may be formed and patterned, for example, in the same or similar manner as the second RDL dielectric layer 183 formed at block 270, although the second RDL dielectric layer 183 is on a different surface. For example, the second backside dielectric layer 536 may be formed over the first backside dielectric layer 533 and over the backside lines 535, and a via 537 may be formed in the second backside dielectric layer 536 (e.g., by etching, ablating, etc.) to expose contact areas of the backside lines 535.

Backside interconnect pads 538 (e.g., ball contact pads) may be formed on the second backside dielectric layer 536 and/or in the vias 537 of the second backside dielectric layer 536. The back interconnect pads 538 may thus be electrically connected to the back traces 535. The backside interconnect pads 538 may be formed, for example, in the same or similar manner as the second RDL lines formed at block 275. The back side interconnect pads 538 may be formed, for example, by forming metal contact pads and/or by forming underbump metallization (e.g., to enhance subsequent attachment to the back side lines 535 via interconnect structures).

Although the backside RDL layer 532 is shown with two backside

dielectric layers

533, 536 and one layer of backside wiring 535, it should be appreciated that any number of dielectric and/or wiring layers may be formed.

As illustrated, for example, in fig. 5E, after the backside RDL layer 532 is formed, a wafer support structure 150 may be attached to the backside RDL layer 532 (e.g., directly, with an intervening adhesive layer, with vacuum force, etc.). The wafer support 150 may be attached, for example, in the same or similar manner as the wafer support 150 attached at block 245. For example, fig. 5E illustrates attachment of the wafer support 150 in a manner similar to the attachment of fig. 1E, although in which it is attached to the RDL layer 532, rather than to the molding layer 130 and semiconductor dies 125, 126.

As depicted, for example, in fig. 5F, the support layer 105 (shown in fig. 5E) may be removed from the RD wafer, a front side redistribution layer may be formed on a side of the RD structure 110 opposite the

dice

125, 126, interconnect structures 192 may be formed, and the wafer support 150 may be removed.

For example, the support layer 105 may be removed in a manner the same as or similar to that discussed herein with respect to block 250 and FIGS. 1E-1F. Also for example, a front redistribution layer may be formed in a manner the same as or similar to that discussed herein with respect to blocks 255-280 and FIGS. 1G-1H. Also for example, interconnect structure 192 may be formed in a manner the same as or similar to that discussed herein with respect to block 285 and fig. 1I. Also for example, the wafer support 150 may be removed in a manner the same as or similar to that discussed herein with respect to block 290 and fig. 1J.

In another exemplary embodiment, a substrate (e.g., a build-up substrate, package substrate, etc.) may be attached over the semiconductor dies 125, 126, such as in place of or in addition to the backside RDL discussed herein with respect to fig. 5A-5F. For example, as depicted in fig. 6A, interconnect structure 621 may be formed at a height that will extend to the height of

dice

125, 126. Note that this height is not necessary, for example, in a scenario where the back substrate has its own interconnect structures, or where additional interconnect structures are utilized between the interconnect structures 621 and the back substrate. The interconnect structures 621 may be attached, for example, in a manner the same as or similar to that discussed herein with respect to block 215 and fig. 1B.

Continuing with the example, the assembly 600B may be molded, and if necessary, the mold may be thinned, as depicted in fig. 6B. Such molding and/or thinning may be performed, for example, in a manner the same as or similar to that discussed herein with respect to

blocks

230 and 235 and fig. 1C and 1D.

As shown in fig. 6C, a wafer support 150 may be attached, the support layer 105 may be removed, and a front side RDL may be formed. For example, a wafer support 150 may be attached in a manner the same as or similar to that discussed herein with respect to block 245 and fig. 1E. Also for example, the support layer 105 may be removed in a manner the same as or similar to that discussed herein with respect to block 250 and fig. 1F. Also for example, a front side RDL may be formed in a manner the same as or similar to that discussed herein with respect to blocks 255-280 and FIGS. 1G-1H.

As depicted in fig. 6D, interconnect structures 192 may be attached, the wafer support 150 may be removed, and a backside substrate 632 may be attached. For example, the interconnect structure 192 may be attached in a manner the same as or similar to that discussed herein with respect to block 285 and fig. 1I. Also for example, the wafer support 150 may be removed in a manner the same as or similar to that discussed herein with respect to block 290 and fig. 1J. Also for example, the backside substrate 632 may be electrically attached to the interconnect structure 621, and/or mechanically attached to the molding material 130 and/or the dies 125, 126. The back substrate 632 may be attached, for example, in wafer (or panel) form and/or single package form, and may be attached, for example, before or after dicing (e.g., as discussed in block 295).

The exemplary methods and components shown in FIGS. 1A-1J through 7A-7L and discussed herein are non-limiting examples only, which are presented to illustrate various features of the present disclosure. Such methods and assemblies may also share any or all of the features with the methods and assemblies shown and discussed in the following co-pending U.S. patent applications: U.S. patent application Ser. No. 13/753,120, filed on 29/1/2013 and entitled "semiconductor device and method of manufacturing a semiconductor device"; U.S. patent application serial No. 13/863,457 filed on 16/4/2013 and entitled "semiconductor device and method of manufacturing the same"; U.S. patent application serial No. 14/083,779, entitled semiconductor device with through tsv-less deep well, filed on 19/11/2013; U.S. patent application Ser. No. 14/218,265 entitled "semiconductor device and method of manufacturing the same" filed 3/18/2014; U.S. patent application Ser. No. 14/313,724, entitled "semiconductor device and method of manufacturing the same," filed 24/6/2014; U.S. patent application Ser. No. 14/444,450, entitled "semiconductor device with thin redistribution layer," filed on 7/28 2014; U.S. patent application Ser. No. 14/524,443, entitled "semiconductor device with reduced thickness", filed on 27/10/2014; U.S. patent application Ser. No. 14/532,532, filed on 11/4/2014 and entitled "interposer, method of manufacturing the same, semiconductor package using the same, and method for manufacturing the same"; U.S. patent application Ser. No. 14/546,484 entitled "semiconductor device with reduced warpage" filed on 11/18/2014; and U.S. patent application Ser. No. 14/671,095, entitled "semiconductor device and method of manufacturing the same", filed 3/27/2015; the contents of each of these U.S. patent applications are hereby incorporated by reference in their entirety.

It should be noted that any or all of the semiconductor packages discussed herein may be (but are not required to be) attached to a package substrate. Various non-limiting examples of such semiconductor device packages and methods of making the same will now be discussed.

Fig. 7A-7L are cross-sectional views showing an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package, depicting various features in accordance with the present disclosure. The structures shown in FIGS. 7A-7L may, for example, share any or all of the features with similar structures shown in FIGS. 1A-1J, 3A-3B, 4A-4D, 5A-5F, 6A-6D, 9, 10A-10B, 11A-11D, 12A-12B, 13, and 14. Fig. 8 is a flow chart of an exemplary method 800 of fabricating a semiconductor package according to various features of the present disclosure. The example method 800 may, for example, share any or all of the features with the example method 200 depicted in FIG. 2 and discussed herein, as well as with any of the methods discussed herein. Fig. 7A-7L, for example, may depict exemplary semiconductor packages at various steps (or blocks) of the method 800 of manufacture of fig. 8. Fig. 7A-7L and fig. 8 will now be discussed together.

The example method 800 may include preparing a logic wafer for processing (e.g., for packaging) at block 805. Block 805 may include preparing a logic wafer for processing in any of a variety of ways, non-limiting examples of which are presented herein. Block 805 may, for example, share any or all of the features with block 205 of the example method 200 shown in fig. 2 and discussed herein.

The exemplary method 800 may include preparing a redistribution structure wafer (RD wafer) at block 810. Block 810 may include preparing a RD wafer for processing in any of a variety of ways, non-limiting examples of which are provided herein. Block 810 may, for example, share any or all of the features with block 210 of the example method 200 shown in fig. 2 and discussed herein.

FIG. 7A is a diagram providing an example of various features of block 810. Referring to fig. 7A, the RD wafer 700A may include a support layer 705 (e.g., a silicon layer), for example. A Redistribution (RD) structure 710 may be formed on the support layer 705. The RD structure 710 may include, for example, a base dielectric layer 711, a first dielectric layer 713, first conductive traces 712, a second dielectric layer 716, second conductive traces 715, and interconnect structures 717.

The base dielectric layer 711 may be, for example, on the support layer 705. The base dielectric 711 may include, for example, an oxide layer, a nitride layer, and the like. The base dielectric layer 711 may be formed to specification, for example, and/or may be natural.

The RD wafer 700A, for example, may also include first conductive traces 712 and a first dielectric layer 713. The first conductive lines 712 may include, for example, a deposited conductive metal (e.g., copper, etc.). The first dielectric layer 713 may include, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the first dielectric layer 713 may comprise an organic dielectric material.

The RD wafer 700A, for example, may also include second conductive traces 715 and a second dielectric layer 716. The second conductive traces 715 can comprise, for example, a deposited conductive metal (e.g., copper, etc.). The second conductive lines 715 may be connected to respective first conductive lines 712, for example, through respective conductive vias 714 (e.g., in the first dielectric layer 713). The second dielectric layer 716 can comprise, for example, an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer 716 may comprise an organic dielectric material.

Although two sets of dielectric layers and conductive lines are depicted in fig. 7A, it is understood that the RD structure 710 of the RD wafer 700A may include any number of such layers and lines. For example, the RD structure 710 may include only one dielectric layer and/or one set of conductive traces, three sets of dielectric layers and/or conductive traces, and so on.

As with the logic wafer preparation at block 805, block 810 may include forming interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) on a surface of the RD structure 710. An example of such an interconnect structure 717 is illustrated in fig. 7A, where the RD structure 710 includes an interconnect structure 717, which is illustrated as being formed on the front (or top) side of the RD structure 710 and electrically connected to respective second conductive lines 715 through conductive vias in the second dielectric layer 716. Such an interconnect structure 717 may be utilized, for example, to couple the RD structure 710 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.).

The interconnect structures 717 can comprise, for example, any of a variety of conductive materials (e.g., any one or combination of copper, nickel, gold, etc.). The interconnect structures 717 may also include solder, for example.

Generally, block 810 may include preparing a redistribution structure wafer (RD wafer). Thus, the scope of this summary should not be limited by features of any particular manner of performing such preparation.

The example method 800 may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) at block 820. Block 820 may include attaching the die to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 820 may, for example, share any or all of the features with block 220 of the example method 200 shown in fig. 2 and discussed herein.

Fig. 7B is a diagram providing an example of various features of block 820 (e.g., the die attach). For example, a first die 725 (e.g., which may have been diced from a logic wafer prepared at block 805) is electrically and mechanically attached to the redistribution structure 710. Similarly, the second die 726 (which may have been cut from a logic wafer prepared at block 805, for example) is electrically and mechanically attached to the redistribution structure 710.

The first die 725 and the second die 726 may include any of a variety of die features. In an example scenario, the first die 725 may include a processor die and the second die 726 may include a memory die. In another example scenario, the first die 725 may include a processor die and the second die 726 may include a co-processor die. In another example scenario, the first die 725 may include a sensor die and the second die 726 may include a sensor processing die. Although the component 700B in fig. 7B is shown with two dies 725, 726, it may have any number of dies. For example, it may have only one grain, three grains, four grains, or more than four grains.

Furthermore, although the first die 725 and second die 726 are shown attached laterally to the redistribution structure 710 relative to each other, they may also be arranged in a vertical assembly. Various non-limiting example components of such a structure are shown and discussed herein (e.g., a stack of dies on a die, attachment of dies to opposing substrate sides, etc.). Further, although the first die 725 and the second die 726 are shown as having substantially similar dimensions, such dies 725, 726 may include different individual features (e.g., die height, footprint, connection pitch, etc.).

The first die 725 and the second die 726 are depicted as having substantially uniform pitch, but this is not necessarily so. For example, most or all of the contacts of the first die 725 in an area of the first die footprint proximate to the second die 726 and/or most of the contacts of the second die 126 in an area of the second die footprint proximate to the first die 725 may have a substantially finer pitch than the other most or all of the contacts. For example, the first die 725 closest to the front 5, 10, or n rows of contacts of the second die 726 (and/or the second die 726 closest to the first die 725) may have a pitch of 30 microns, while the other contacts may have a pitch of approximately 80 microns and/or 200 microns. The RD structures 710 may thus have corresponding contact structures and/or lines at the corresponding pitch.

Generally, block 820 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Thus, the scope of this disclosure should not be limited by the features of any particular die, or by the features of any particular multi-die layout, or by the features of any particular manner of attaching such dies, etc.

The exemplary method 800 may include, at block 825, underfill filling the semiconductor die and/or other components attached to the RD structure at block 820. Block 825 may include performing such underfill fill in any of a variety of ways, non-limiting examples of which are presented herein. Block 825 may, for example, share any or all of the features with block 225 of the example method 200 shown in fig. 2 and discussed herein.

Figure 7B is a diagram providing an example of various features of block 825 (e.g., the underfill). The underfill 728 is disposed between the first semiconductor die 725 and the redistribution structure 710 and between the second semiconductor die 726 and the redistribution structure 710.

Although the underfill 728 is depicted as being substantially planar, the underfill may be raised and rounded on the sides of the semiconductor die and/or other components. In one exemplary scenario, at least one-quarter or at least one-half of the die side surfaces may be covered with the underfill material. In another example scenario, one or more or all of the entire side surfaces may be covered with the underfill material. Also for example, a substantial portion of the space directly between the semiconductor dies, between the semiconductor dies and other components, and/or between other components may be filled with the underfill material. For example, at least half or all of the space between laterally adjacent semiconductor dies, between the semiconductor die and other components, and/or between other components may be filled with the underfill fill material. In an exemplary embodiment, the underfill 728 may cover the entire redistribution structure 710 of the RD wafer. In such an exemplary embodiment, when the RD wafer is later diced, such dicing may also cut through the underfill material 728.

Generally, block 825 may include an underfill to fill the semiconductor die and/or other components attached to the RD structure at block 820. Thus, the scope of this disclosure should not be limited by any particular type of underfill, or by the features of any particular manner of performing such underfill.

The exemplary method 800 may include molding the RD wafer (or RD structure) at block 830. Block 830 may include molding the RD wafer in any of a variety of ways, non-limiting examples of which are presented herein. Block 830 may, for example, share any or all of the features with block 230 of the example method 200 shown in fig. 2 and discussed herein.

Fig. 7C is a diagram providing an example of various features (e.g., molding features) of block 830. For example, the molding assembly 700C is illustrated with the molding material 730 covering the top surfaces of the first semiconductor die 725, second semiconductor die 726, underfill 728, and redistribution structure 710. Although the molding material 730 (which may also be referred to herein as an encapsulation material) is shown to completely cover the sides and top of the first semiconductor die 725 and the second semiconductor die 726, this need not be the case. For example, block 830 may include molding techniques that utilize a film assist or die seal to keep the top of the die free of molding material.

Generally, the molding material 730 may, for example, directly contact and cover portions of the

dice

725, 726 that are not covered by the underfill 728. For example, in a scenario in which at least a first portion of the sides of the

dice

725, 726 are covered by the underfill 728, the molding material 730 may directly contact and cover a second portion of the sides of the

dice

725, 726. The molding material 730 may also, for example, fill in the space between the dice 725, 726 (e.g., at least a portion of the space that has not been filled with the underfill 728).

Generally, block 830 may include molding the RD wafer. Thus, the scope of this summary should not be limited by characteristics of any particular molding material, structure, and/or technique.

The exemplary method 800 may include grinding (or otherwise thinning) the molding material applied at block 830 at block 835. Block 835 can include grinding (or thinning) the molding material in any of a variety of ways, non-limiting examples of which are presented herein. Block 835 may, for example, share any or all of the features with block 235 of the example method 200 shown in fig. 2 and discussed herein.

Fig. 7D is a diagram providing an example of various features of block 835 (e.g., the molded abrasive feature). The assembly 700D is depicted with the molding material 730 thinned (e.g., relative to the molding material 730 depicted in fig. 7C) to expose the top surfaces of the

dice

725, 726. In such instances, the dies 725, 726 may also have been ground (or thinned).

As illustrated herein, the molding material 730 may be retained in an overmolded element to cover the dies 725, 726. For example, the molding material 730 may be unground, or the molding material 730 may be ground, but not to the height of an exposed

die

725, 726.

Generally, block 835 may include grinding (or otherwise thinning) the molding material applied at block 830. Thus, the scope of this summary should not be limited to any particular amount or type of grinding (or thinning) of features.

The example method 800 may include, at block 845, attaching the molded RD wafer (e.g., the top or molded side thereof) to a wafer support structure. Block 845 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 845 may, for example, share any or all of the features with block 245 of the example method 200 shown in fig. 2 and discussed herein.

Fig. 7E is a diagram providing an example of various features of block 845 (e.g., features of wafer support attachment). The wafer support structure 750 is attached to the molding material 730 and the top side of the dies 725, 726. The wafer support structure 750 may be attached, for example, with an adhesive. Note that in an assembly in which the top of the dies 725, 726 is covered with the molding material 730, the wafer support structure 750 may only be directly coupled to the top of the molding material 730.

Generally, block 845 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Thus, the scope of this disclosure should not be limited by features of any particular type of wafer support structure, or by features of any particular manner of attaching a wafer support structure.

The exemplary method 200 may include removing a support layer from the RD wafer at block 850. Block 850 may include removing the support layer in any of a variety of ways, non-limiting examples of which are presented herein. Block 850 may, for example, share any or all of the features with block 250 of the example method 200 shown in fig. 2 and discussed herein.

As discussed herein, the RD wafer may include a support layer on which an RD structure is formed and/or carried. The support layer may, for example, comprise a semiconductor material (e.g., silicon). In an example scenario in which the support layer comprises a silicon wafer layer, block 850 may include removing the silicon (e.g., removing all of the silicon from the RD wafer, removing substantially all of the silicon (e.g., at least 90% or 95%) from the RD wafer, etc.). For example, block 850 may include mechanically polishing substantially all of the silicon, followed by a dry or wet chemical etch to remove the remaining portion (or substantially all of the remaining portion). In an example scenario where the support layer is loosely attached to the RD structure formed (or carried) thereon, block 850 may include pulling or peeling apart the support layer and the RD structure.

Fig. 7F is a diagram providing an example of various features of block 850, such as a support layer removal feature. For example, the support layer 705 (shown in fig. 7E) is removed from the RD structure 710. In the illustrated example, the RD structure 710 may still include a base dielectric layer 711 (e.g., an oxide, nitride, etc.) as discussed herein.

Generally, block 850 may include removing a support layer from the RD wafer. Thus, the scope of this disclosure should not be limited to features of any particular type of wafer material, or to features of any particular manner of removal of wafer material.

The exemplary method 800 may include, at block 855, forming and patterning a redistribution layer (RDL) dielectric layer for etching an oxide layer of the RD structure. Block 855 may include forming and patterning the RDL dielectric layer in any of a variety of ways, non-limiting examples of which are presented herein. Block 855 may, for example, share any or all of the features with block 255 of the example method 200 shown in fig. 2 and discussed herein.

Fig. 7G is a diagram providing an example of various features of block 855. For example, the RDL dielectric 771 is formed and patterned on the base dielectric 711. The patterned RDL dielectric layer 771 may include, for example, a via 772 through the RDL dielectric layer 771, for example, the base dielectric layer 711 may be etched through via 772 (e.g., at block 860), and conductive lines (or portions thereof) may be formed (e.g., at block 865) in via 772.

Generally, block 855 may comprise, for example, forming and patterning a dielectric layer (e.g., an RDL dielectric layer) over the base dielectric layer. Thus, the scope of the present disclosure should not be limited by characteristics of a particular dielectric layer or by characteristics of a particular manner of forming a dielectric layer.

The exemplary method 800 may include, at block 860, etching the base dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, e.g., unmasked portions thereof. Block 860 may include performing the etch in any of a variety of ways, non-limiting examples of which are presented herein. Block 860 may, for example, share any or all of the features with block 260 of the example method 200 shown in fig. 2 and discussed herein.

FIG. 7G is a diagram providing an example of various features of block 860. For example, the portion of the base dielectric layer 711 shown below the first conductive lines 712 in fig. 7F is removed from fig. 7G. This enables, for example, metal-to-metal contact between the first conductive lines 712 and the RDL lines formed at block 865.

Generally, block 860 may include, for example, etching the base dielectric layer. Thus, the scope of this disclosure should not be limited to any particular manner of performing such etching.

The exemplary method 800 may include forming redistribution layer (RDL) lines at block 865. Block 865 may include forming the RDL lines in any of a variety of ways, non-limiting examples of which are presented herein. Block 865 may, for example, share any or all of the features with block 265 of the example method 200 shown in fig. 2 and discussed herein.

Fig. 7G and 7H are diagrams providing an example of various features of block 865 (e.g., features of RDL line formation). For example, a first portion 781 of the RDL lines may be formed in via 772 of RDL dielectric layer 771 and contact first conductive lines 712 of the RD structure 710 exposed by such via 772. Also for example, a second portion 782 of the first RDL line can be formed on the first RDL dielectric layer 77 l.

In general, block 865 may include forming redistribution layer (RDL) lines. Thus, the scope of this disclosure should not be limited by characteristics of any particular RDL line, or by characteristics of any particular manner of forming such RDL lines.

It is noted that although the exemplary method 800 shows only one RDL dielectric layer at block 855 and only one RDL line at block 865, such blocks may be repeated as many times as desired.

The exemplary method 800 may form an interconnect structure on the RDL line at block 885. Block 885 may include forming the interconnect structures in any of a variety of ways, non-limiting examples of which are presented herein. For example, block 885 may share any or all of the features with block 285 of the example method 200 shown in fig. 2 and discussed herein.

Block 885 may, for example, form conductive pillars (e.g., metal pillars, copper pillars, solder-capped pillars, etc.) and/or conductive bumps (e.g., solder, etc.) on the RDL lines. For example, block 885 may include electroplating conductive pillars, disposing or coating conductive bumps, and so forth.

Fig. 7I is a diagram providing an example of various features (e.g., bumping features) of block 885. For example, interconnect structures 792 (e.g., which are shown as solder-capped pillars, such as copper pillars) are attached to the RDL lines 782.

Although the redistribution layers formed at blocks 855-885, which may also be referred to as front redistribution layers (RDLs), are depicted in fig. 7A-7L as being substantially fan-in elements (e.g., substantially contained within the footprint of the dies 725, 726), they may also be formed as fan-out elements, e.g., where at least a portion of the interconnect structure 792 extends substantially outside the footprint of the dies 725, 726. Non-limiting examples of such components are presented herein.

Generally, block 885 may include forming interconnect structures, for example, on the RDL lines and/or on the RDL dielectric layer. Thus, the scope of this disclosure should not be limited by characteristics of any particular interconnect structure or by any particular manner of forming an interconnect structure.

The example method 800 at block 890 may include debonding (or detaching) the wafer support attached at block 845. Block 890 may include performing such debonding in any of a variety of ways, non-limiting features of which are presented herein. For example, block 890 may share any or all of the features with block 290 of the example method 200 shown in fig. 2 and discussed herein.

Fig. 7H and 7I are diagrams providing an example of various features of block 890. For example, the wafer support 750 depicted in fig. 7H is removed in fig. 7I.

Generally, block 890 may include debonding the wafer support. Thus, the scope of this disclosure should not be limited by the characteristics of any particular type of wafer support, or by any particular manner of detackifying a wafer support.

The example method 800 may include dicing the wafer at block 895. Block 895 may include dicing the wafer in any of a variety of ways, non-limiting examples of which are presented herein. Block 895 may, for example, share any or all of the features with block 295 of the exemplary method 200 shown in fig. 2 and discussed herein.

The discussion herein has generally focused on the processing of a single die of the RD wafer. This focusing on a single die of the RD wafer is for clarity of illustration only. It should be understood that all of the process steps (or blocks) discussed herein may be performed on an entire wafer. For example, each of the illustrations presented in FIGS. 7A-7L and other figures herein can be replicated tens or hundreds of times on a single wafer. For example, one of the illustrated device components of the wafer may not be separated from an adjacent device component prior to dicing.

Block 895 may include, for example, cutting (e.g., mechanical punch cutting, mechanical saw cutting, laser cutting, soft beam cutting, plasma cutting, etc.) individual packages from the wafer. The end result of such dicing may be, for example, the package shown in fig. 7I. For example, the cut may form a side surface of the package that is coplanar including a plurality of members of the package. For example, the side surfaces of any or all of the molding material 730, the dielectric layer of the RD structure 710, the RDL dielectric layer 771, the underfill material 728, etc. may be coplanar.

Generally, block 895 may include dicing the wafer. Thus, the scope of this disclosure should not be limited by features of any particular manner of dicing a wafer.

The example method 800 at block 896 may include preparing a substrate, or wafer or panel thereof, for attachment of the component 700I thereto. Block 896 may include preparing a substrate in any of a variety of ways, non-limiting examples of which are presented herein. Block 896 may, for example, share any or all of the features with

blocks

205 and 210 of the example method 200 shown in fig. 2 and discussed herein.

The substrate may, for example, include features of any of a variety of substrates. For example, the substrate may include a package substrate, motherboard substrate, build-up substrate, molded substrate, semiconductor substrate, glass substrate, etc.). Block 896 may include, for example, preparing the front and/or back surfaces of the substrate for electrical and/or mechanical attachment. Block 896 may, for example, leave the substrate of a panel in panel form at this stage and later cut individual packages, or may cut individual substrates from a panel at this stage.

Block 896 may also include receiving the substrate from a manufacturing station adjacent or upstream from a manufacturing facility, from another geographic location, etc. The received substrate may, for example, be already prepared, or additional preparation steps may be performed.

FIG. 7J is a diagram providing an example of the various features of block 896. For example, the assembly 700J includes an exemplary substrate 793 prepared for attachment.

Generally, block 896 may include preparing a substrate, or wafer or panel thereof, for attachment of the component 700I thereto. Thus, the scope of various features of this disclosure should not be limited to characteristics of a particular substrate, or to characteristics of any particular manner of fabricating a substrate.

The example method 800 at block 897 may include attaching a component to the substrate. Block 897 may include attaching a component (e.g., a component 700I as illustrated in FIG. 7I or other components) in any of a variety of ways, non-limiting examples of which are presented herein. Block 897 may, for example, share any or all of the features with block 220 of the example method 200 shown in fig. 2 and discussed herein.

The components may include features of any of a variety of components, non-limiting examples of which are presented herein, such as in all figures and/or the discussion related thereto. Block 897 may include attaching the component in any of a variety of ways. For example, block 897 may include using batch reflow, thermal Compression Bonding (TCB), conductive epoxy, etc. to attach the component to the substrate.

Fig. 7J is a diagram providing an example of various features (e.g., component attachment features) of block 897. For example, the assembly 700I illustrated in fig. 7I is attached to the substrate 793.

Although not shown in fig. 7J, in various example implementations (e.g., as shown in fig. 7K and 7L), interconnect structures, such as through-mold interconnect structures, may be formed on the substrate 793. In such an example implementation, block 897 may share any or all of the features with block 215 of the example method 200 shown in fig. 2 and discussed herein, although with respect to forming the interconnect structures on the substrate 793. Note that this interconnect structure may be performed before or after the component is attached, or may also be performed before or after the underfill at block 898.

Generally, block 897 includes attaching a component to the substrate. Thus, the scope of this disclosure should not be limited by characteristics of any particular component, substrate, or manner of attaching a component to a substrate.

The example method 800 may include, at block 898, underfill dispensing the assembly on the substrate. Block 898 may include any of a variety of underfill fills, non-limiting examples of which are presented herein. Block 898 may, for example, share any or all of the features with block 825 and/or block 225 of the example method 200 shown in fig. 2 and discussed herein.

For example, block 898 may include underfilling the attached component with a capillary underfill fill after the component of block 897 is attached. For example, the underfill may comprise a reinforced polymeric material that is sufficiently viscous to flow between the component and the substrate in a capillary action.

Also for example, block 897 may include underfill filling the semiconductor die with a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while the component is being attached at block 897 (e.g., using a thermocompression bonding process). For example, such underfill material may be deposited (e.g., printed, sprayed, etc.) prior to attaching the assembly.

As with all blocks depicted in the example method 800, block 898 may be performed at any location in the flow of the method 800 as long as the space between the component and the substrate is accessible.

The underfill fill may also occur at a different block of the example method 800. For example, the underfill fill may be performed as part of substrate molding block 899 (e.g., with a mold underfill fill).

Fig. 7K is a diagram providing an example of various features of block 898, such as the underfill fillet feature. The underfill fill 794 is disposed between the assembly 700I and the substrate 793.

Although the underfill material 794 is depicted as being substantially planar, the underfill material may be raised and rounded on the sides of the assembly 700I and/or other components. In one exemplary scenario, at least one quarter or at least one half of the side surface of the component 700I may be covered with the underfill material. In another example scenario, one or more or all of the entire side surface of the device 700I may be covered with the underfill material. Also for example, a substantial portion of the space directly between the assembly 700I and other components, and/or between other components (shown in the various figures), may be filled into the underfill material 794. For example, at least half of the space or the entire space between the assembly 700I and a laterally adjacent member may be filled with the underfill material.

As shown in fig. 7J, the assembly 700J may include a first underfill fill 728 between the dies 725, 726 and the RD structure 710, and a second underfill fill 794 between the RD structure 710 and the substrate 793. Such underfill fills 728, 794 may be different, for example. For example, in an exemplary scenario where the distance between the

dice

725, 726 and the RD structure 710 is less than the distance between the RD structure 710 and the substrate 793, the first underfill fill 728 may generally comprise a smaller fill size (or have a higher viscosity) than the second underfill fill 794. In other words, the second underfill fill 794 may be less expensive than the first underfill fill 728.

Furthermore, the respective underfill dispensing processes performed at

blocks

898 and 825 may be different. For example, block 825 may include filling with a capillary underfill, and block 898 may include filling with a non-conductive paste (NCP) underfill.

In another example, blocks 825 and 898 may include being performed simultaneously in a same underfill dispensing process, such as after block 897. Additionally, as discussed herein, a molded underfill fill may also be utilized. In such an exemplary scenario, block 899 may include performing underfill dispensing of either or both of blocks 825 and/or 898 during the substrate molding process. For example, block 825 may include performing a capillary underfill fill, while block 898 is performed as a mold underfill fill process at block 899.

Generally, block 898 may include underfill to fill in components and/or other components attached to the substrate at block 897. Thus, the scope of this disclosure should not be limited by characteristics of any particular type of underfill, or any particular manner of performing underfill filling.

The example method 800 may include molding the substrate at block 899. Block 899 may include performing such molding in any of a variety of ways, non-limiting examples of which are presented herein. Block 899 may, for example, share any or all of the features with block 830 and/or block 230 of the example method 200 shown in fig. 2 and discussed herein.

For example, block 899 may include molding over the top surface of the substrate, over components to which block 897 is attached, over TMV interconnect structures (such as conductive balls, ellipsoids, posts or pillars (e.g., plated posts, wires or bond wires, etc.) if formed on the substrate, etc.).

Block 899 may include, for example, using transfer molding, compression molding, or the like. Block 899 may include, for example, a process that utilizes a panel molding in which multiple substrates are connected in a panel and molded together, or block 899 may include individually molded substrates. In the case of panel molding, block 899 may include performing a singulation process after the panel is molded, wherein individual substrates are separated from the panel of substrates.

The molding material may include any of a variety of features, for example. For example, the molding material (e.g., epoxy Molding Compound (EMC), epoxy molding compound, etc.) may include a relatively high modulus, e.g., to provide package support during a subsequent process. Also for example, the molding material may include a relatively low modulus to provide package flexibility in a subsequent process.

Block 899 may, for example, include using a molding material that is different than the molding material used at block 830. For example, block 899 may utilize a molding material having a lower modulus than the molding material utilized at block 830. In such a scenario, the central region of the element may be relatively stiff compared to the peripheral region of the element, which provides for the absorption of various forces in the more robust regions of the element.

In an example scenario in which the molding material 735 of the component 700K and the molding material 730 of the component 700I are different, and/or are formed at different stages, and/or are formed using different types of processes, block 899 (or another block) may include preparing the molding material 730 for adhesion to the molding material 735. For example, the molding material 730 may be physically or chemically etched. The molding material 730 may be plasma etched, for example. Also for example, grooves, notches, protrusions, or other physical features may be formed on the molding material 730. Also for example, an adhesive may be disposed on the molding material 730.

Block 899 may, for example, utilize a different type of molding process than the one utilized at block 830. In an exemplary scenario, block 830 may utilize a compression molding process and block 899 utilizes a transfer molding process. In such an example scenario, block 830 may utilize a molding material specifically adapted for compression molding, and block 899 may utilize a molding material specifically adapted for transfer molding. Such molding materials may, for example, have significantly different material characteristics (e.g., flow characteristics, cure characteristics, hardness characteristics, particle size characteristics, chemical compound characteristics, etc.).

As illustrated herein, for example with respect to block 898, the molding process of block 899 may provide an underfill between the component 700I and the substrate 793 and/or may provide an underfill between the dies 725, 726 and the RD structure 710. In such an example, there may be material uniformity between the mold underfill material and the mold material encapsulating substrate 793 and component 700I and/or the mold material encapsulating RD structure 710 and semiconductor dies 725, 726.

Fig. 7K is a diagram providing an example of the various features (e.g., the molded features) of block 899. For example, the molding assembly 700K is illustrated with the molding material 735 covering the interconnect structure 795 and the assembly 700I. Although the molding material 735 (which may also be referred to herein as an encapsulation material) is shown with the top end of the element 700I exposed, this need not be the case. For example, block 899 may completely cover the device 700I and need not be followed by a thinning (or grinding) operation to expose the top of the device 700I.

Generally, the molding material 735 may, for example, directly contact and cover portions of the assembly 700I not covered by the underfill 794. For example, in a scenario in which at least a first portion of the side of the component 700I is covered with the underfill 794, the molding material 735 may directly contact and cover a second portion of the side of the component 700I. Further, the molding material 735 may extend laterally to the edge of the substrate 793 and thus form a side surface that is coplanar with the substrate 793. Such components may be formed, for example, using panel molding followed by singulation of individual packages from the panel.

Generally, block 899 may include molding the substrate. Thus, the scope of this summary should not be limited by characteristics of any particular molding material, structure, and/or technique.

The example method 800 at block 886 may include forming an interconnect structure on the substrate, e.g., on a side of the substrate opposite the side to which the component is attached at block 897. The interconnect structures may include features of any of a variety of types of interconnect structures, such as structures that may be utilized to connect a semiconductor package to another package or a motherboard. For example, the interconnect structures may include conductive balls (e.g., solder balls) or bumps, conductive pillars, and the like.

Fig. 7K is a diagram providing an example of various features of block 886 (e.g., features of the form interconnect). For example, the interconnect structures 792 are depicted as being attached to the planar surface 791 of the substrate 793.

Generally, block 886 may include forming interconnect structures on the substrate. Thus, the scope of this disclosure should not be limited by characteristics of the particular interconnect structures or by any particular manner of forming such structures.

As discussed herein, the underfill 728 can cover at least a portion of the sides of the

dice

725, 726 and/or the underfill 794 can cover at least a portion of the sides of the component 700I. Fig. 7L is an illustrative example providing such coverage. For example, the assembly 700I is illustrated wherein the underfill 728 is part of the sides of the contact dies 725, 726. As discussed herein, during a cutting process, the underfill 728 may also be cut, which results in an element 700I that includes a flat side surface that includes a side surface of the RD structure 710, a side surface of the molding material 730, and a side surface of the underfill 728.

The assembly 700L (which may also be referred to as a package) is illustrated with an underfill fill 794 contacting a portion of the sides of the assembly 700I (e.g., the sides of the RD structure 710, the sides of the underfill fill 728, and the sides of the molding material 730). Note that as discussed herein, in various example embodiments, the underfill fill 794 may comprise a molded underfill fill that is the same material as the molding material 735. The molding material 735 is shown encapsulating the substrate 793, interconnect structure 795, underfill 794, and component 700I. Although the top of the device 700I and interconnect structure 795 are exposed from the molding material 735 in the example shown, this need not be the case.

FIGS. 7A-7L and 8 present various example method features and variations thereof. Additional exemplary method features will now be presented with reference to the additional figures.

As discussed herein, in the discussion of fig. 7A-7L and 8, block 835 may include grinding (or otherwise thinning) the molding material 730 to expose one or more of the dies 725, 726. An example is provided in fig. 7D.

As also discussed, the molding grind (or thinning) at block 835 need not be performed, or may be performed to the extent that the tops of dies 725, 726 are still covered with molding material 730. An example is provided in fig. 9, where the molding material 735 covers the top of the dies 725, 726 of the component 700I.

As also discussed herein, for example with respect to block 897 and fig. 7K and 7L, in various example embodiments, interconnect structures may be formed on the substrate. An example is provided in fig. 9. For example, although the top of die interconnect structures 795 is initially covered with molding material 735, via 940 is ablated in molding material 735 to expose interconnect structures 795.

Moreover, as discussed in the discussion of FIGS. 7A-7L and 8 herein, TMV interconnect structures need not be formed on the substrate in various exemplary embodiments. An example is provided in fig. 10A. As shown in fig. 10A, with respect to fig. 7K, no TMV interconnect structure 795 is formed. As also shown in fig. 10A, with respect to fig. 1J, the molding material 735 does not cover the interconnect structure.

Also for example, as illustrated herein, the molding grind (or thinning) at block 899 may be skipped or performed to the extent that the top of the component 700I and/or at least one of the dies 725, 726 is covered with molding material 735. Fig. 10A is a diagram providing an example of such processing. In general, the assembly 1000A of fig. 10A is similar to the assembly 700K of fig. 7K minus the interconnect structure 795, and wherein the molding material 735 is covering the assembly 700I.

Furthermore, as illustrated herein, the molding grinding (or thinning) at block 899 may be performed to the extent that the tops of the component 700I and/or one or more of the dies 725, 726 are exposed from the molding material 735 (and/or molding material 730). Fig. 10B is a diagram providing an example of such processing. Generally, the assembly 1000B of FIG. 10B is similar to the assembly 700K of FIG. 7K, minus the interconnect structure 795.

In another example, as illustrated herein, the TMV interconnects in the discussion of block 897 may include any of a variety of structures, such as a conductive pillar (e.g., plated pillar or pillar, vertical conductive line, etc.). Fig. 11A is a diagram providing an example of conductive posts 1121 attached to the substrate 793. The conductive posts 1121 can be, for example, plated on the substrate 793. The conductive posts 1121 can also include, for example, wires (e.g., wire bonded wires) attached (e.g., wire bonded attachment, soldering, etc.) to the substrate 793 and extending vertically. The conductive posts 1121 can extend from the substrate 793 to a height that is greater than a height of the dies 725, 726, equal to a height of one or more of the dies 725, 726, less than a height of the dies 725, 726, etc. It is noted that any number of columns of pillars 1121 can be formed. Generally, the component 1100A of fig. 11A is similar to the component 700K of fig. 7K (minus the molding compound 735) with the conductive pillars 1121 as interconnect structures instead of the elongated conductive balls 795.

Continuing with the example, fig. 11B depicts the substrate 793 covered with the molding material 735, the conductive pillars 1121, the component 700I (e.g., semiconductor dies 725, 726), and the underfill material 794. The molding may be performed, for example, according to block 899 of the example method 800. Generally, the component 1100B of fig. 11B is similar to the component 700K of fig. 7K, having the conductive pillars 1121 as interconnect structures instead of the elongated conductive balls 795, and having the molding material 735 not yet thinned or not yet thinned enough to expose the component 700I.

Continuing with the example, fig. 11C depicts the molding material 735 as having been thinned (e.g., ground) to a desired thickness. The thinning may be performed, for example, according to block 899 of the exemplary method 800. For example, it is noted that the conductive pillars 1121 and/or the component 700I (e.g., including the molding material 730 and/or the semiconductor dies 725, 726) may also be thinned. For example, the thinning of the molding material 735 may expose the tips of the conductive pillars 1121. However, if the thinning of the molding material 735 does not expose the tips of the conductive posts 1121, a molding ablation operation may be performed. Note that although the device 1100C is shown with the top ends of the semiconductor dies 725, 726 of the device 700I exposed, the top ends need not be exposed.

In general, the assembly 1100C of fig. 11C is similar to the assembly 700K of fig. 7K, with conductive pillars 1121 as interconnect structures, rather than the elongated conductive balls 795.

Continuing with the example, the component 1100C shown in fig. 11C may be further processed by forming a redistribution layer (RDL) 1132 over the molding material 735 and component 700I (e.g., semiconductor dies 725, 726 including the molding material 730 and/or the same). Fig. 11D shows an example of such processing. The redistribution layer 1132 may also be referred to herein as a backside Redistribution (RDL) layer 1132. Although the formation of such a backside RDL is not explicitly shown in one of the blocks of the exemplary method 800, such an operation may be performed in any of the blocks, such as after the mold-grinding operation (if performed) of the block 899.

As shown in fig. 11D, a first backside dielectric layer 1133 may be formed and patterned over the molding material 735 and the component 700I (e.g., the semiconductor dies 725, 726 including the molding material 730 and/or the same). The first backside dielectric layer 1133 may be formed and patterned, although on a different surface, for example, in the same or similar manner as the RDL dielectric layer 771 formed at block 855. For example, the first backside dielectric layer 1133 can be formed on the molding material 735, and/or on the component 700I (e.g., the semiconductor die 725, 726 including the molding material 730 and/or the semiconductor die 730, 726) such as directly on the exposed back surfaces of the dies 725, 726, on the molding material 730 and/or 735 covering the back surfaces of the dies 725, 726, and so on, and a via 1134 can be formed (e.g., by etching, ablating, and so on) in the first backside dielectric layer 1133 to expose at least the top end of the conductive pillar 1121.

A backside trace 1135 may be formed on the first backside dielectric layer 1133 and in the via 1134 of the first backside dielectric layer 1133. The backside traces 1135 may thus be electrically connected to the conductive pillars 1121. The back traces 1135 may be formed, for example, in the same or similar manner as the RDL traces 782 formed at block 865. At least some, if not all, of the backside lines 1135 may extend, for example, from conductive pillars 1121 to locations directly above the component 700I (e.g., the semiconductor dies 725, 726 including the molding material 730 and/or the same). At least some of the backside lines 1135 may also extend from the conductive pillars 1121, for example, to locations other than directly above the component 700I (e.g., the semiconductor dies 725, 726 including the molding material 730 and/or the same).

A second backside dielectric layer 1136 may be formed and patterned over the first backside dielectric layer 1133 and backside lines 1135. The second backside dielectric layer 1136 may be formed and patterned, for example, in the same or similar manner as the RDL dielectric layer 771 formed at block 855, albeit on a different surface. For example, the second backside dielectric layer 1136 may be formed over the first backside dielectric layer 1133 and over the backside lines 1135, and vias 1137 may be formed in the second backside dielectric layer 1136 (e.g., by etching, ablation, etc.) to expose contact areas of the backside lines 1135.

Backside interconnect pads 1138 (e.g., ball contact pads, lands, terminals, etc.) may be formed on the second backside dielectric layer 1136 and/or in the vias 1137 of the second backside dielectric layer 1136. The back interconnect pads 1138 may thus be electrically connected to the back traces 1135. The backside interconnect pads 1138 may be formed, for example, in the same or similar manner as the RDL lines formed at block 865. The back side interconnect pads 1138 may be formed, for example, by forming metal contact pads and/or by forming underbump metallization (e.g., to enhance subsequent attachment to the back side lines 1135 by other interconnect structures).

Although the backside RDL layer 1132 is illustrated with two backside

dielectric layers

1133, 1136 and a backside line 1135, it should be appreciated that any number of dielectric and/or line layers may be formed.

Although not shown in fig. 11D, interconnect structures may be formed on the substrate 793, such as on a side of the substrate 793 opposite the device 700I and molding material 735, as discussed herein, for example, with respect to block 886 and fig. 7K.

In another exemplary embodiment, a substrate (e.g., a laminate substrate, package substrate, etc.) may be attached over the component 700I (e.g., including the semiconductor dies 725, 726 and molding material 730) and the molding material 735, for example, instead of or in addition to the backside RDL discussed herein with respect to fig. 11A-11D.

For example, as depicted in figure 12A, the interconnect structures 795 may be formed at a height that will extend at least to the height of the device 700I. Note that this height need not be present, for example, in a scenario where the back substrate has its own interconnect structures, or where additional interconnect structures are utilized between the interconnect structures 795 and the back substrate. The interconnect structures 795 may be attached, for example, in a manner the same as or similar to that discussed herein with respect to block 897 and fig. 7K.

Continuing with the example, as depicted in fig. 12A, the assembly 1200A may be molded with a molding material 735, and the molding material 735 may be thinned, if necessary. Such molding and/or thinning may be performed, for example, in a manner the same as or similar to that discussed herein with respect to block 899 and fig. 7K.

As shown in fig. 12B, a back substrate 1232 may be attached. For example, the backside substrate 1232 may be electrically connected to the interconnect structure 795 and/or mechanically attached to the molding material 735 and/or the component 700I (e.g., the molding material 730 and/or the semiconductor dies 725, 726). The back substrate 1232 may be attached, for example, in panel form and/or in single package form, and may be attached, for example, before or after singulation.

As discussed herein, after the assembly 700I is attached to the substrate 793, the substrate 793 and/or assembly 700I may be covered with a molding material. Alternatively or additionally, the substrate 793 and/or assembly 700I may be covered with a cover or stiffener (stiffener). Fig. 13 provides an illustrative example. Fig. 13 generally shows the assembly 700J of fig. 7J with a cover 1310 (or reinforcement member) added.

The cover 1310 may comprise metal, for example, and provides electromagnetic shielding and/or heat dissipation. For example, the cover 1310 can be electrically coupled to a ground line on the substrate 793 to provide shielding. The cover 1310 may be coupled to the substrate 793, for example, using solder and/or conductive epoxy. Although not shown, thermal interface material may be formed in a gap 1315 between the assembly 700I and the lid 1310.

Although most of the examples shown and discussed herein show the assembly 700I attached to the substrate 793 generally, other means (e.g., active and/or passive means) may be attached to the substrate 793. For example, as shown in fig. 14, a semiconductor die 1427 may be attached (e.g., flip-chip bonded, wire bonded, etc.) to the substrate 793. The semiconductor die 1427 is attached to the substrate 793 in a manner laterally adjacent to the component 700I. After such attachment, any of the package structures discussed herein (e.g., interconnect structures, molding, lids, etc.) may then be formed.

In another exemplary embodiment, other components may be coupled to the top side of the assembly 700I in a vertically stacked assembly. Fig. 15 shows an example of such an assembly 1500C. A third die 1527 and a fourth die 1528 (e.g., the inactive side thereof) may be attached to the top of the device 700I. Such attachment may be performed, for example, using an adhesive. Bond pads on the active side of the third die 1527 and the fourth die 1528 may then be wire bonded to the substrate 793. It is noted that in a scenario where an RDL and/or substrate is attached over the component 700I, the third die 1527 and/or the fourth die 1528 may be flip-chip bonded to such RDL and/or substrate. After such attachment, any of the package structures discussed herein (e.g., interconnect structures, molding, lids, etc.) may then be formed.

In yet another example embodiment, another member may be coupled to a bottom side of the substrate. Fig. 16 shows an example of such an assembly. A third die 1699 is attached to the bottom side of the substrate 793, for example in a gap between interconnect structures on the bottom side of the substrate 793. After such attachment, any of the package structures discussed herein (e.g., interconnect structures, molding, lids, etc.) may then be formed.

The exemplary methods and components illustrated in FIGS. 8-16 and discussed herein are non-limiting examples only, and are presented to illustrate various features of the present disclosure. Such methods and assemblies may also share any or all of the features with the methods and assemblies shown and discussed in the co-pending U.S. patent applications listed below: U.S. patent application Ser. No. 13/753,120, filed on 29/1/2013 and entitled "semiconductor device and method of manufacturing a semiconductor device"; U.S. patent application Ser. No. 13/863,457, filed on 2013, 4, month 16 and entitled "semiconductor device and method of manufacturing the same"; U.S. patent application Ser. No. 14/083,779, entitled "semiconductor device with through-TSV-less deep well" filed on 11/19/2013; U.S. patent application Ser. No. 14/218,265 entitled "semiconductor device and method of manufacturing the same" filed 3/18/2014; U.S. patent application Ser. No. 14/313,724, entitled "semiconductor device and method of manufacturing the same," filed 24/6/2014; U.S. patent application Ser. No. 14/444,450, entitled "semiconductor device with thin redistribution layer," filed on 7/28 2014; U.S. patent application serial No. 14/524,443, entitled "semiconductor device with reduced thickness", filed on 27/10/2014; U.S. patent application Ser. No. 14/532,532, filed on 11/4/2014 and entitled "interposer, method of manufacturing the same, semiconductor package using the same, and method for manufacturing the same"; U.S. patent application serial No. 14/546,484, entitled "semiconductor device with reduced warpage," filed on 11/18 2014; and U.S. patent application Ser. No. 14/671,095, filed 3/27/2015 and entitled "semiconductor device and method of manufacturing the same"; the contents of each of these U.S. patent applications are hereby incorporated by reference in their entirety.

The discussion herein is inclusive of a number of illustrative figures that show various portions of a semiconductor package assembly. For purposes of clarity of illustration, the figures do not show all of the features of each example component. Any of the components of the examples presented herein may share any or all of the features with any or all of the other components presented herein. For example, and without limitation, any of the components of the examples shown and discussed with respect to fig. 1A-7L, or portions thereof, may be incorporated into any of the components of the examples discussed with respect to fig. 8-16. Conversely, any of the components shown and discussed with respect to fig. 8-16 may be incorporated into the components shown and discussed with respect to fig. 1A-7L.

In summary, various features of this summary are to provide a semiconductor device or package structure and a method for fabricating the same. While the foregoing has been described with reference to certain features and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the scope thereof. Therefore, it is intended that the present disclosure not be limited to the particular examples disclosed, but that the present disclosure will include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device, comprising:

a redistribution structure, comprising:

an upper redistribution layer comprising:

a first dielectric layer comprising a first dielectric material; and

a first conductive line; and

an underlying redistribution layer comprising:

a second dielectric layer comprising a second dielectric material; and

a second conductive trace electrically coupled to the first conductive trace;

a first semiconductor die attached to an upper side of the redistribution structure;

a third dielectric material between the first semiconductor die and the upper side of the redistribution structure, wherein the third dielectric material directly contacts a lower side of the first semiconductor die, a lateral side of the first semiconductor die, and an upper side of the first dielectric material;

a second semiconductor die attached to the upper side of the redistribution structure;

a first molding material covering at least the upper side of the redistribution structure and individual lateral sides of each of the first and second semiconductor dies, wherein the first molding material directly contacts a top side of the third dielectric material, and in vertical cross-section no portion of the first molding material is in direct contact with the upper side of the redistribution structure;

a substrate comprising an upper substrate side attached to a lower side of the redistribution structure; and

a second molding material covering at least the upper substrate side, a lateral side of the first molding material, and a lateral side of the redistribution structure.

2. The semiconductor device according to claim 1, wherein the first molding material and the second molding material are different materials.

3. The semiconductor device of claim 1, wherein an outer surface of the first molding material includes adhesion-enhancing features that enhance adhesion between the first molding material and the second molding material, the adhesion-enhancing features including recesses or protrusions.

4. The semiconductor device of claim 1, wherein:

the first molding material includes a first molding top surface;

the second molding material includes a second top molding surface coplanar with the first top molding surface; and is provided with

Further comprising an upper dielectric layer contacting and covering the first molded top surface, the second molded top surface, the first semiconductor die, and the second semiconductor die.

5. The semiconductor device of claim 1, comprising:

a fourth dielectric material between the substrate and the redistribution structure, wherein the third dielectric material and the fourth dielectric material are different types of materials.

6. The semiconductor device of claim 1, comprising:

a fourth dielectric material between the substrate and the redistribution structure, wherein the fourth dielectric material directly contacts the third dielectric material.

7. The semiconductor device of claim 1, comprising a fourth dielectric material between the redistribution structure and the second semiconductor die, wherein the third dielectric material comprises an underfill material comprising lateral sides orthogonal to the upper side of the redistribution structure.

8. The semiconductor device of claim 1, comprising a fourth dielectric material between the redistribution structure and the second semiconductor die, wherein the third dielectric material comprises an underfill fill material comprising a lateral side that is coplanar with the lateral side of the first molding material and the lateral side of the redistribution structure.

9. The semiconductor device of claim 1, wherein:

the first conductive lines comprise one or more portions that extend down through the first dielectric layer; and is

The second conductive lines include one or more portions that extend upwardly through the second dielectric layer.

10. A semiconductor device, comprising:

a redistribution structure, comprising:

an upper redistribution layer comprising:

a first conductive line; and

a first dielectric layer comprising a first organic dielectric material laminated on the first conductive line in a first direction;

an underlying redistribution layer comprising:

a second conductive trace electrically coupled to the first conductive trace; and

a second dielectric layer comprising a second organic dielectric material laminated on the second conductive lines in a second direction, the first direction being opposite to the second direction; and

a plurality of conductive posts extending from the underlying redistribution layer and attached to the second conductive trace;

a first semiconductor die attached to an upper side of the redistribution structure; and

a second semiconductor die attached to the upper side of the redistribution structure.

11. The semiconductor device according to claim 10, wherein:

the first organic dielectric material is laminated on the first conductive line in the first direction such that the first organic dielectric material contacts a lateral side of the first conductive line and an upward facing side of the first conductive line;

the second organic dielectric material is laminated on the second conductive line in the second direction such that the second organic dielectric material contacts a lateral side of the second conductive line and a downward facing side of the second conductive line.

12. The semiconductor device of claim 11, comprising:

a substrate attached to the plurality of conductive pillars;

a third dielectric material between the redistribution structure and the first semiconductor die and between the redistribution structure and the second semiconductor die; and

a fourth dielectric material between the substrate and the redistribution structure, wherein the third dielectric material and the fourth dielectric material are different materials.

13. The semiconductor device of claim 10, further comprising:

a first molding material covering at least the upper side of the redistribution structure and laterally surrounding the first and second semiconductor dies,

wherein:

the third dielectric material comprises an underfill material comprising lateral sides exposed from laterally outer sides of the first molding material; and

the second organic dielectric material and the first organic dielectric material are different materials.

14. A semiconductor device, comprising:

a first redistribution structure, comprising:

a first dielectric layer comprising a first dielectric material;

a first conductive line embedded in the first dielectric layer and comprising:

a first line top side partially covered by the first dielectric layer;

a first line bottom side exposed at a bottom side of the first dielectric layer; and

a first line lateral side covered by the first dielectric layer;

a first conductive via embedded in the first dielectric layer and comprising:

a first via top side exposed at a top side of the first dielectric layer;

a first via bottom side directly coupled to the first line top side; and

a first via lateral side covered by the first dielectric layer; and

a die interconnect structure at least a portion of which is formed over the first conductive via, wherein the die interconnect structure extends over the first dielectric layer;

a second redistribution structure on a bottom side of the first redistribution structure and comprising:

a second dielectric layer comprising a second dielectric material;

a second conductive line; and

a second conductive via extending through the second dielectric layer and electrically coupling the second conductive trace to the first conductive trace;

a semiconductor die attached to a top side of the first redistribution structure, wherein the semiconductor die includes conductive bumps soldered to the die interconnect structures of the first redistribution structure;

a molding material covering at least a portion of the top side of the first redistribution structure and respective lateral sides of the semiconductor die; and

a conductive pillar secured to the top side of the first redistribution structure in a solderless connection such that a top side of the conductive pillar is coplanar with a top side of the semiconductor die and a bottom side of the conductive pillar is vertically lower than the die interconnect structure.

15. The semiconductor device of claim 14, comprising a third dielectric material different from the mold material, the third dielectric material between the semiconductor die and the top side of the first redistribution structure, wherein the third dielectric material comprises an underfill fill material comprising lateral sides coplanar with lateral edges of the first and second redistribution structures.

16. The semiconductor device of claim 14, wherein the first dielectric material comprises an organic dielectric material.

17. The semiconductor device of claim 14, wherein the first conductive via is narrower in a lateral direction than the first conductive line.

18. The semiconductor device according to claim 14, wherein the second conductive line comprises:

a bottom side partially covered by the second dielectric material;

a top side exposed at a top side of the second dielectric material; and

a lateral side covered by the second dielectric material.

19. The semiconductor device of claim 18, wherein the top side of the conductive pillar, the top side of the molding material, and the top side of the semiconductor die are ground surfaces.

20. The semiconductor device of claim 14, wherein the first conductive line is free of a seed layer.

21. The semiconductor device of claim 14, wherein the first conductive lines and other conductive lines of the first redistribution structure have a sub-micron pitch.

22. A semiconductor device, comprising:

an upper redistribution structure, comprising:

a first dielectric layer; and

a first conductive line embedded in the first dielectric layer and comprising:

a first line top side partially covered by the first dielectric layer;

a first line lateral side covered by the first dielectric layer; and

a first conductive via embedded in the first dielectric layer and comprising:

a first via top side exposed at a top side of the first dielectric layer;

a first via bottom side directly coupled to the first line top side; and

a first via lateral side covered by the first dielectric layer;

a lower redistribution structure on a bottom side of the upper redistribution structure and comprising:

a second dielectric layer coupled at the bottom side of the first dielectric layer;

a third dielectric layer coupled at a bottom side of the second dielectric layer;

a second conductive line embedded in the third dielectric layer;

a second conductive via extending through the second dielectric layer, wherein:

the second conductive trace extends along the bottom side of the second dielectric layer;

the first conductive line extends along a top side of the second dielectric layer;

the second conductive via couples the first conductive trace to the second conductive trace; and

no conductive line is surrounded by the second dielectric layer;

a semiconductor die attached to a top side of the upper redistribution structure;

a molding material covering at least a portion of the top side of the upper redistribution structure and a respective lateral side of the semiconductor die; and

an upper dielectric material, different from the molding material, between the semiconductor die and the top side of the first redistribution structure.

23. The semiconductor device of claim 22, wherein the upper dielectric material comprises an underfill fill material that covers the top side of the upper redistribution structure such that the molding material is isolated from the top side of the upper redistribution structure.

24. The semiconductor device of claim 22, wherein the upper dielectric material comprises an underfill fill material that extends laterally at least to a lateral edge of the upper redistribution structure, and wherein a lateral side of the upper dielectric material is coplanar with a lateral side of the upper redistribution structure.

25. The semiconductor device of claim 22, wherein said upper redistribution structure is devoid of any dielectric layer other than said first dielectric layer.

26. The semiconductor device of claim 22, wherein the overlying dielectric material comprises an underfill fill material that extends laterally at least to lateral edges of the overlying redistribution structures, and wherein lateral sides of the molding material are coplanar with respective lateral sides of the underfill fill material and respective lateral sides of the overlying redistribution structures.

27. The semiconductor device of claim 26, wherein a top side of the molding material is coplanar with a top side of the semiconductor die.

28. The semiconductor device of claim 22, comprising:

a substrate;

a conductive interconnect structure connecting a bottom side of the semiconductor die to an upper side of the substrate; and

an encapsulation material covering at least a portion of the upper side of the substrate and laterally surrounding the semiconductor die, the upper redistribution structure, the lower redistribution structure, and the conductive interconnect structure.

29. The semiconductor device of claim 22 wherein a portion of said overlying dielectric material laterally surrounds said semiconductor die.

30. A semiconductor device, comprising:

an upper redistribution structure, comprising:

a first dielectric layer comprising a first dielectric material; and

a first conductive line;

an underlying redistribution structure, comprising:

a second dielectric layer comprising a second dielectric material; and

a second conductive trace electrically coupled to the first conductive trace;

a first semiconductor die attached to an upper side of the upper redistribution structure;

a third dielectric material between the first semiconductor die and the upper side of the upper redistribution structure and laterally surrounding at least a lower portion of the first semiconductor die;

a second semiconductor die attached to the upper side of the upper redistribution structure;

a fourth dielectric material between the second semiconductor die and the upper side of the upper redistribution structure and laterally surrounding at least a lower portion of the second semiconductor die such that a first volume extending completely and directly between the first semiconductor die and the second semiconductor die is completely filled with the third dielectric material and the fourth dielectric material;

a first molding material covering at least a portion of the upper side of the upper redistribution structure and at least a portion of a lateral side of the first semiconductor die such that a second volume extending completely and directly between the first semiconductor die and the second semiconductor die is completely filled with the first molding material; and

a second molding material different from the first molding material, the second molding material at least laterally surrounding the second semiconductor die.

31. The semiconductor device of claim 30, wherein the second molding material extends laterally outward to a greater extent in all lateral directions than the first molding material.

32. The semiconductor device of claim 31, wherein said third dielectric material and said fourth dielectric material are part of the same underfill fill layer.

33. The semiconductor device of claim 30, wherein the third and fourth dielectric materials comprise an underfill material disposed such that no portion of the first and second molding materials contacts the upper redistribution structure.