CN106449428A - Chip encapsulation process - Google Patents

Abstract

The invention provides a chip packaging process, which comprises the following steps: forming a first metal pattern layer on a carrier plate; disposing a chip on the first metal pattern layer, wherein the chip includes a first metal pattern layer provided with connection bumps. The side and the second side that are not provided with connection bumps, the second side is in contact with the first metal pattern layer; the first encapsulation layer is arranged on the carrier to cover the first metal pattern layer and the chip, and the first encapsulation The connection bumps are exposed on the surface of the material layer; a second metal pattern layer is formed on the first sealing material layer, and at least part of the second metal pattern layer is in contact with the connection bumps; a second metal pattern layer is arranged on the first sealing material layer For the sealing material layer, the surface of the second sealing material layer exposes the second metal pattern layer; the carrier board is removed, so that the surface of the first sealing material layer exposes the first metal pattern layer. The invention can dissipate the heat of the chip in time, thereby maintaining the performance of the chip.

Description

Chip Packaging Process

technical field

The invention relates to the technical field of chip packaging, in particular to a chip packaging process.

Background technique

With the continuous development of integrated circuit technology, electronic products are increasingly developing in the direction of miniaturization, intelligence and high reliability, and integrated circuit packaging directly affects the performance of integrated circuits, electronic modules and even the entire machine. In the case of shrinking and increasing integration, the electronics industry has put forward higher and higher requirements for the salvation of integrated circuit packaging.

In the current fan-out (fanout) process, the chip is buried in the resin material. When the chip is working, the heat generated by the chip is accumulated due to poor heat dissipation, which will cause the chip to overheat and reduce the performance.

Contents of the invention

The invention provides a chip packaging process, which can solve the problem in the prior art that the performance of the chip is reduced due to poor heat dissipation.

In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a chip packaging process, which includes the following steps: forming a first metal pattern layer on a carrier plate; placing the chip on the first metal pattern layer On, wherein, the chip includes a first side with connection bumps and a second side without connection bumps, the second side is in contact with the first metal pattern layer; set on the carrier A first sealing material layer, to cover the first metal pattern layer and the chip, and expose the connection bumps on the surface of the first sealing material layer; form a second sealing material layer on the first sealing material layer two metal pattern layers, and make at least a partial area of the second metal pattern layer contact with the connection bumps; a second sealing material layer is arranged on the first sealing material layer, and the second sealing material layer The surface of the second metal pattern layer is exposed; the carrier board is removed, so that the surface of the first encapsulant layer exposes the first metal pattern layer.

Wherein, after the step of forming the first metal pattern layer on the carrier, it further includes: forming a limiting component on the carrier to limit the position of the chip.

Wherein, the limiting component includes a plurality of limiting cylinders, and the plurality of limiting cylinders are embedded in the first encapsulant layer and enclose a loading space; the chip is placed in the first The step on the metal pattern layer further includes: disposing the chip in the loading space.

Wherein, the first metal pattern layer includes a base part and a heat dissipation part which are not connected to each other, and the base part is arranged on the outer periphery of the heat dissipation part; the step of arranging the chip on the first metal pattern layer is: The chip is arranged on the heat dissipation part, and the second side surface is in contact with the heat dissipation part; the step of forming a limiting part on the carrier board is: forming the Limit the column, and make one end of the limit column contact with the base.

Wherein, the limiting cylinder is a metal cylinder; the second metal pattern layer is formed on the first encapsulant layer, and at least part of the second metal pattern layer is connected to the connection bump The contacting step further includes: contacting at least a partial area of the second metal pattern layer with the other end of the limiting post.

Wherein, the base includes a plurality of interconnected wiring areas, each of which is provided with at least one limiting column.

Wherein, the first encapsulant layer is provided on the carrier to cover the first metal pattern layer and the chip, and the surface of the first encapsulant layer exposes the connection bumps. The steps include: pressing a first encapsulation prefabricated sheet on the carrier, so that the first encapsulation prefabricated sheet covers the first metal pattern layer and the chip; polishing the first encapsulation prefabricated sheet The surface of the material prefabricated sheet is formed to form the first encapsulant layer and expose the connection bumps.

Wherein, after the step of forming the first metal pattern layer on the carrier, it further includes: forming a limiting member on the carrier to limit the position of the chip;

The step of arranging a first encapsulant layer on the carrier to cover the first metal pattern layer and the chip, and exposing the connection bumps on the surface of the first encapsulant layer includes : Pressing the first encapsulation prefabricated sheet on the carrier, so that the first encapsulation prefabricated sheet covers the first metal pattern layer, the chip and the limiting component; The surface of the first encapsulant prefabricated sheet is formed to form the first encapsulant layer, and the connecting bumps and the limiting components are exposed.

Wherein, the step of arranging a second sealing material layer on the first sealing material layer, and exposing the second metal pattern layer on the surface of the second sealing material layer includes: pressing the second encapsulation prefabricated sheet, so that the second encapsulation prefabricated sheet covers the second metal pattern layer; polishing the surface of the second encapsulation prefabricated sheet to form the first The second sealing material layer is used to expose the second metal pattern layer.

Wherein, both the first sealing material layer and the second sealing material layer are resin layers.

The beneficial effects of the present invention are: different from the situation of the prior art, the present invention exposes the first metal pattern layer and the second metal pattern layer on both sides of the encapsulant layer respectively, and the second side of the chip and the first The first metal pattern layer is in contact with each other, so even if the chip is embedded in the encapsulation layer, the heat generated by the chip can be dissipated from the first metal pattern layer in time without causing heat accumulation, which prevents the chip from overheating and resulting in performance degradation.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a top view of a chip packaging structure provided by an embodiment of the present invention;

Fig. 2 is a side view of area A in Fig. 1;

Fig. 3 is a top view of the first metal pattern layer and the limiting component in the chip packaging structure provided by the embodiment of the present invention;

Fig. 4 is a side view of a region of a chip package structure provided by another embodiment of the present invention;

5 is a schematic flow chart of a chip packaging process provided by an embodiment of the present invention;

6 is a schematic flow chart of a chip packaging process provided by another embodiment of the present invention;

Fig. 7 is a top view during step S21 in Fig. 6;

Fig. 8 is a side view of area A in Fig. 7;

Fig. 9 is a top view during step S22 in Fig. 6;

Fig. 10 is a side view of area A in Fig. 9;

Fig. 11 is a top view during step S23 in Fig. 6;

Fig. 12 is a side view of area A in Fig. 11;

Fig. 13 is a top view of the first sealing prefabricated sheet in step S24 in Fig. 6 before lamination;

Fig. 14 is a side view of area A in Fig. 13;

Fig. 15 is a top view of the first encapsulation prefabricated sheet after lamination in step S24 in Fig. 6;

Fig. 16 is a side view of area A in Fig. 15;

Fig. 17 is a top view of the first encapsulant layer formed in step S24 in Fig. 6;

Fig. 18 is a side view of area A in Fig. 17;

Fig. 19 is a top view during step S25 in Fig. 6;

Fig. 20 is a side view of area A in Fig. 19;

Fig. 21 is a top view of the second sealing material prefabricated sheet after step S26 in Fig. 6 is pressed;

Fig. 22 is a side view of area A in Fig. 21;

Fig. 23 is a top view of the second encapsulant layer formed in step S26 in Fig. 6;

Fig. 24 is a side view of area A in Fig. 23 .

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

FIG. 1 is a top view of a chip package structure provided by an embodiment of the present invention. Fig. 2 is a side view of area A in Fig. 1 .

As shown in Figures 1 and 2, the chip packaging structure formed by the chip packaging process of the present invention at least includes a first metal pattern layer 10, a chip 20, a second metal pattern layer 30, and a sealing material layer 40, wherein the chip 20 is set On the first metal pattern layer 10 and in contact with the first metal pattern layer 10, the second metal pattern layer 30 is arranged on the chip 20, and the sealing material layer 40 covers the first metal pattern layer 10, the chip 20 and the second metal pattern layer. Metal pattern layer 30 .

Specifically, the chip 20 includes a first side 22 provided with connection bumps 21 and a second side 23 not provided with connection bumps 21, the chip 20 is arranged on the first metal pattern layer 10, and the second side 23 of the chip 20 It is in contact with the first metal pattern layer 10 so that the heat generated by the chip 20 can be dissipated from the first metal pattern layer 10 .

The second metal pattern layer 30 is disposed on the chip 20 , at least a part of the second metal pattern layer 30 is in contact with the connection bump 21 , so as to conduct the chip 20 with the external circuit through the second metal pattern layer 30 .

The sealing material layer 40 covers the first metal pattern layer 10, the chip 20 and the second metal pattern layer 30, and one side of the sealing material layer 40 exposes the first metal pattern layer 10, and the other side of the sealing material layer 40 exposes The second metal pattern layer 30 . On the one hand, the encapsulant layer 40 can play an insulating role, and on the other hand, the chip 20 can be more firmly fixed on the first metal pattern layer 40 , which can effectively prevent the chip 20 from falling off.

Different from the prior art, the present invention exposes the first metal pattern layer 10 and the second metal pattern layer 30 on both sides of the sealing material layer 40, and the second side 23 of the chip 20 is connected to the first metal pattern layer 10 contacts, therefore, even if the chip 20 is embedded in the encapsulant layer 40, the heat generated by the chip 20 during operation can be dissipated from the first metal pattern layer 10 in time, without causing accumulation of heat, and avoiding the overheating of the chip 20 and causing performance problems. reduce.

A limiting component is provided on the periphery of the chip 20 to limit the position of the chip 20 , so as to prevent the chip 20 from shifting due to expansion and contraction of the encapsulant during curing.

Specifically, in this embodiment, the limiting component includes a plurality of limiting cylinders 50, the plurality of limiting cylinders 50 are embedded inside the encapsulant layer 40 and enclose a loading space 60, and the chip 20 is arranged in the loading space Within 60. For example, the chip 20 in this embodiment is square, and the limiting columns 50 form a fence and enclose a square, and the chip 20 is loaded in the square loading space 60 . Certainly, in some other embodiments, the chip 20 may have other shapes, and the fence formed by the limiting cylinder 50 is surrounded by a shape similar to the chip 20 .

It can be understood that in some other embodiments, the limiting component can also be of other structures, for example, the limiting component is an L-shaped piece arranged at the four corners of the chip, or a baffle arranged on the four sides of the chip 20, etc. , as long as the position of the chip 20 can be limited to prevent the chip 20 from shifting.

The limiting cylinder 50 is formed on the first metal pattern layer 10, and one end of the limiting cylinder 50 is in contact with the first metal pattern layer 10, so that the first metal pattern layer 10 is used as the basis of the limiting cylinder 50 to form a frame The structure can increase the binding force and improve the stability of the limiting cylinder 50.

Please refer to FIG. 3 . FIG. 3 is a top view of the first metal pattern layer and the limiting component in the chip package structure provided by the embodiment of the present invention. The first metal pattern layer 10 includes a base portion 11 and a heat dissipation portion 12 which are not connected to each other, and the base portion 11 is disposed on the outer periphery of the heat dissipation portion 12 . Specifically, the limiting post 50 is formed on the base 11 , the chip 20 is disposed on the heat dissipation portion 12 , and the second side 23 is in contact with the heat dissipation portion 12 . Wherein, the heat dissipation part 12 is in the shape of a net. For example, the heat dissipation part 12 of the present embodiment is a square net whose shape and size are similar to those of the second side 23 of the chip. The second side of the chip 20 The side surface 23 is directly in contact with the heat dissipation part 12 , and since the heat dissipation part 12 is made of metal material, the heat dissipation part 12 can fully dissipate the heat of the chip 20 .

The limiting cylinder 50 is a metal cylinder, and at least a partial area of the second metal pattern layer 30 is in contact with the other end of the limiting cylinder 50 . Therefore, the two ends of the limiting cylinder 50 are respectively connected to the first metal pattern layer 10 and the second metal pattern layer 30, and the second metal pattern layer 30 is connected to the connection bump 21 of the chip 20, so that the connection bump 21 and the connection bump 21 can be established. Limit the connection between the post 20 and the first metal layer 10 . The first metal layer 10 can also be used as a baseline, so that both the first side 22 and the second side 23 of the chip 20 can be connected to external circuits.

For example, the second metal pattern layer 30 in this embodiment includes a plurality of circular lands 31 and connection bridges 32, a part of the second metal pattern layer 30, such as the middle area of this embodiment, each Each connection pad 31 corresponds to a connection bump 21 respectively, and is connected with the connection bump 21, and the connection pads 31 in the remaining areas are located at the outer periphery of the middle area, and among the connection pads 31 of the outer periphery, some connection pads 31 pass through the connection bridge 32 It is connected with some connection pads 31 in the middle area. In addition, the connecting bridge 32 can also be arranged in the middle area to establish a connection between two different connecting bumps 21 . The shapes and numbers of the connection pads 31 and the connection bridges 32 are set according to actual needs. Understandably, in other embodiments, the second metal pattern layer 30 may also have other patterns.

The base in the first metal pattern layer 10 is not connected to the heat sink 11 , so that the base 11 acts as a base line and communicates with an external circuit for conduction, while the heat sink 12 acts as a heat sink.

The base 11 includes a plurality of interconnected wiring areas, such as the wiring areas 13a, 13b, 13c, 13d, 13e and 13f in FIG. connection between the area and the chip 20 . For example, in Fig. 3, five space-limiting cylinders 50 are arranged on the wiring area 13a, one space-limiting cylinder 50 is respectively provided on the wiring areas 13b, 13c, and 13d, and four space-limiting cylinders 50 are provided on the wiring area 13e. The number of wiring areas and the number of limiting cylinders 50 provided on each wiring area are set according to actual requirements.

The sealing material layer 40 includes a first sealing material layer 41 and a second sealing material layer 42, the first metal pattern layer 10, the chip 20 and the limiting component are embedded in the first sealing material layer 41, and the second metal pattern layer 30 is embedded in the Inside the second sealing material layer 42 .

Specifically, the first encapsulant layer 41 of this embodiment covers the first metal pattern layer 10, the chip 20 and the limiting cylinder 50, so that the positions of the chip 20, the first metal pattern layer 10 and the limiting cylinder 50 are fixed. .

The second sealing material layer 42 covers the second metal pattern layer 30 so that the second metal pattern layer 30 can be more firmly fixed on the first sealing material layer 41 .

Specifically, the sealing material layer 40 is a resin layer, such as epoxy resin. The epoxy resin has better sealing performance and is easy to be molded.

To sum up, in the chip packaging structure of the present invention, the heat generated by the chip 20 can be dissipated from the first metal pattern layer 10 in time to avoid heat accumulation and maintain the performance of the chip 20 .

As shown in FIG. 4 , FIG. 4 is a side view of a region of a chip package structure provided by another embodiment of the present invention. The difference between this embodiment and the above-mentioned embodiments is that the chip packaging structure of this embodiment is a stack of the chip packaging structures of the two above-mentioned embodiments, and the second metal pattern layer 30 of the underlying chip packaging structure and the limiting posts 50, and the positions corresponding to the first metal pattern layer 10 of the top chip packaging structure and the position corresponding to the limiting pillars 50 are connected through solder balls 70 to realize the conduction between the two chips.

Understandably, in some other embodiments, multiple chip packaging structures of the above embodiments may also be stacked.

Please continue to refer to FIG. 5 , which is a schematic flowchart of a chip packaging process provided by an embodiment of the present invention.

The chip packaging process of this embodiment includes the following steps:

S11: forming a first metal pattern layer on the carrier.

The formation process of the first metal pattern layer 10 may be: firstly forming a metal layer on the carrier plate, and then forming a preset pattern through the yellow light process, exposure, development, etching and other steps, thereby forming the first metal pattern layer 10 .

S12: disposing the chip on the first metal pattern layer, wherein the chip includes a first side with connection bumps and a second side without connection bumps, and the second side is in contact with the first metal pattern layer.

Specifically, alignment marks are formed on one side of the carrier board by laser, and the chips 20 are arranged according to the alignment marks. In this embodiment, the entire second side surface 23 of the chip 20 is in contact with the first metal pattern layer 10 , so that heat can be sufficiently dissipated.

S13: disposing a first encapsulant layer on the carrier to cover the first metal pattern layer and the chip, and expose the connection bumps on the surface of the first encapsulant layer.

Specifically, in this embodiment, the setting of the first encapsulation layer 41 includes the following steps: first, press the first encapsulation prefabricated sheet on the carrier, so that the first encapsulation prefabricated sheet covers the first metal pattern layer 10 and chip 20, and then polish the surface of the first encapsulation prefabricated sheet to form the first encapsulation layer 41 and expose the connection bumps 21.

Understandably, in some other embodiments, the connection bumps 21 may also be exposed by forming through holes.

S14: forming a second metal pattern layer on the first encapsulant layer, and making at least a partial area of the second metal pattern layer contact with the connection bumps.

The formation process of the second metal pattern layer 30 can be: firstly forming a metal layer on the carrier plate, and then through the yellow light process, after exposure, development, etching and other steps to form a preset pattern, so as to form the second metal pattern layer 30 . And, the partial area of the second metal pattern layer 30 is in contact with the connection bump 21, thereby establishing the connection between the connection bump 21 and the second metal pattern layer 30, so that the external circuit is connected with the second metal pattern layer 30. Chip 20 is turned on.

S15: disposing a second sealing material layer on the first sealing material layer, the surface of the second sealing material layer exposing the second metal pattern layer.

In step S15, the setting of the second sealing material layer 42 includes the following steps: firstly pressing the second sealing material prefabricated sheet on the first sealing material layer 41, so that the second sealing material prefabricated sheet covers the second metal pattern layer 30, and then polish the surface of the second encapsulation prefabricated sheet to form the second encapsulation layer 42 and expose the second metal pattern layer 30.

S16: Remove the carrier board, so that the surface of the first encapsulant layer exposes the first metal pattern layer.

After step S16, the first metal pattern layer 10 is exposed on the surface of the first encapsulant layer 41, and the second side 23 of the chip 20 is in contact with the first metal pattern layer 41, so that the heat generated by the chip 20 can pass through the first metal pattern layer 41. The metal pattern layer 10 is dissipated without causing heat accumulation, so as to prevent the chip 20 from being overheated and causing performance degradation.

Please refer to FIG. 6 . FIG. 6 is a schematic flowchart of a chip packaging process provided by another embodiment of the present invention.

S21: forming a first metal pattern layer on the carrier.

As shown in FIG. 7 and FIG. 8 , FIG. 7 is a top view of step S21 in FIG. 6 . Fig. 8 is a side view of area A in Fig. 7 . The first metal pattern layer 10 of this embodiment is formed on the carrier 90, the first metal pattern layer 10 includes a base 11 and a heat dissipation portion 12, wherein the base 11 is arranged on the outer periphery of the heat dissipation portion 12, and the base 11 includes a plurality of interconnected Disconnected wiring regions 11a, 11b, 11c, 11d, 11e, and 11f. The heat dissipation portion 12 is in the shape of a mesh.

The base portion 11 and the heat dissipation portion 12 are not connected to each other, so that the base portion 11 is used as a baseline to communicate with an external circuit, and plays a role of conduction, while the heat dissipation portion 12 plays a role of heat dissipation.

S22: Form a limiting component on the carrier to limit the position of the chip.

Please refer to FIG. 9 and FIG. 10 , FIG. 9 is a top view of step S22 in FIG. 6 . Fig. 10 is a side view of area A in Fig. 9 . Specifically, the limiting component includes a plurality of limiting cylinders 50, the limiting cylinders 50 are metal cylinders, and the multiple limiting cylinders 50 enclose a loading space 60, for example, the limiting cylinders 5 surround the heat dissipation part 12 to form a loading space 60 above the heat sink 12 . The plurality of limiting cylinders 50 in this embodiment are all formed on the base 11 , and the base 11 is used as the foundation of the limiting cylinders 50 to form a frame structure, which can increase the binding force and improve the stability of the limiting cylinders 50 . At least one limiting column 50 is disposed on each wiring area of the base 11 .

It can be understood that in some other embodiments, the limiting component can also be of other structures, for example, the limiting component is an L-shaped piece arranged at the four corners of the chip 20, or a baffle arranged on the four sides of the chip 20 etc., as long as the position of the chip 20 can be limited to prevent the chip 20 from shifting.

S23: disposing the chip on the first metal pattern layer, wherein the chip includes a first side with connection bumps and a second side without connection bumps, and the second side is in contact with the first metal pattern layer.

As shown in FIG. 11 and FIG. 12 , FIG. 11 is a top view of step S23 in FIG. 6 , and FIG. 12 is a side view of area A in FIG. 11 .

The chip 20 includes a first side 22 with connection bumps 21 and a second side 23 without connection bumps 21 . The chip 20 is placed in the loading space 60 formed by the limiting cylinder 50 , so that the limiting cylinder 50 prevents the chip 20 from shifting due to expansion and contraction of the encapsulant during the curing process during plastic packaging. At the same time, the chip 20 is disposed on the heat dissipation part 12 so that the second side surface 23 is in contact with the heat dissipation part 12 .

S24: disposing a first encapsulant layer on the carrier to cover the first metal pattern layer, the chip and the limiting component, and expose the surface of the first encapsulating material layer to connect the bumps and the limiting component.

Step S24 specifically includes:

Firstly, the first encapsulation prefabricated sheet 43 is pressed on the carrier 90 so that the first encapsulation prefabricated sheet 43 covers the first metal pattern layer 10 , the chip 20 and the limiting cylinder 50 . As shown in FIG. 13 , FIG. 14 , FIG. 15 and FIG. 16 , FIG. 13 is a top view of the first sealing prefabricated sheet in step S24 in FIG. 6 before lamination. Fig. 14 is a side view of area A in Fig. 13 . FIG. 15 is a top view of the first encapsulation prefabricated sheet after lamination in step S24 in FIG. 6 . Fig. 16 is a side view of area A in Fig. 15 .

Then, the surface of the first sealing material prefabricated sheet 43 is polished to form the first sealing material layer 41 , and expose the connection bumps 21 and the limiting posts 50 . As shown in FIG. 17 and FIG. 18 , FIG. 17 is a top view of the first encapsulant layer formed in step S24 in FIG. 6 , and FIG. 18 is a side view of area A in FIG. 17 .

S25: Form a second metal pattern layer on the first encapsulant layer, and make at least a partial area of the second metal pattern layer be in contact with the connection bump, and at least a partial area be in contact with the other end of the limiting post.

As shown in FIG. 19 and FIG. 20 , FIG. 19 is a top view of step S25 in FIG. 6 . Fig. 20 is a side view of area A in Fig. 19 . In step S25, the second metal pattern layer 30 is formed on the first encapsulant layer 41. For example, the second metal pattern layer 30 in this embodiment includes a plurality of circular lands 31 and connection bridges 32. Part of the area of the second metal pattern layer 30, such as the middle area of this embodiment, each land 31 corresponds to a connection bump 21, and is connected to the connection bump 21, and the lands 31 of the remaining areas are located in the middle In the outer periphery of the region, some of the connecting pads 31 in the outer peripheral region are connected to some of the connecting pads 31 in the middle region through connecting bridges 32 . In addition, the connecting bridge 32 can also be arranged in the middle area to establish a connection between two different connecting bumps 21 . The shapes and numbers of the connection pads 31 and the connection bridges 32 are set according to actual needs. Understandably, in other embodiments, the second metal pattern layer 30 may also have other patterns.

S26: disposing a second sealing material layer on the first sealing material layer, the surface of the second sealing material layer exposing the second metal pattern layer.

Step S26 specifically includes the following steps:

As shown in FIGS. 21 and 22 , FIG. 21 is a top view of the second encapsulation prefabricated sheet after step S26 in FIG. 6 , and FIG. 22 is a side view of area A in FIG. 21 . The second sealing prefabricated sheet 44 is pressed on the first sealing material layer 41 so that the second sealing material prefabricated sheet 44 covers the second metal pattern layer 30 .

As shown in FIG. 23 and FIG. 24 , FIG. 23 is a top view of the second encapsulant layer formed in step S26 in FIG. 6 , and FIG. 24 is a side view of area A in FIG. 23 . The surface of the second encapsulation prefabricated sheet 44 is polished to form the second encapsulation layer 42 and expose the second metal pattern layer 30 .

S27: Remove the carrier board, so that the surface of the first encapsulant layer exposes the first metal pattern layer.

In step S27, after the carrier board is removed, a chip packaging structure as shown in FIG. 1 and FIG. The heat is dissipated.

In addition, since the first metal pattern layer 10 and the second metal pattern layer 30 are respectively exposed on both sides of the encapsulant layer 40, and since the limiting cylinder 50 is a metal cylinder, the two ends of the limiting cylinder 50 are respectively connected The first metal pattern layer 10 and the second metal pattern layer 30, the second metal pattern layer 30 is connected to the connection bump 21 of the chip 20, so that the connection bump 21 and the limiting column 50 and the first metal pattern layer 10 can be established. the connection between. The first metal pattern layer 10 can also be used as a baseline, so that both the first side 22 and the second side 23 of the chip 20 can be connected to external circuits.

In other embodiments of the present invention, in the above embodiment, after steps S21-S27, it also includes: stacking the two chip package structures formed through the above steps S21-S27, and soldering them through solder balls, and finally A chip package structure as shown in FIG. 4 is formed. Specifically, at the position corresponding to the second metal pattern layer 30 of the bottom chip packaging structure and the limiting column 50, and at the position corresponding to the first metal pattern layer 10 and the limiting column 50 of the chip packaging structure of the top layer. The solder balls 70 are connected to realize conduction between the two chips.

Understandably, in some other embodiments, multiple chip packaging structures of the above embodiments may also be stacked.

To sum up, the present invention can dissipate the heat generated by the chip in time, prevent heat accumulation, and maintain the performance of the chip.

The above is only the embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process conversion made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technologies fields, all of which are equally included in the scope of patent protection of the present invention.

Claims (10)

1. A chip packaging process, characterized in that, comprises the following steps: forming a first metal pattern layer on the carrier; A chip is placed on the first metal pattern layer, wherein the chip includes a first side with connection bumps and a second side with no connection bumps, the second side is connected to the first metal pattern layer. pattern layer contacts; A first encapsulant layer is disposed on the carrier to cover the first metal pattern layer and the chip, and expose the connection bumps on the surface of the first encapsulant layer; forming a second metal pattern layer on the first encapsulant layer, and making at least a partial area of the second metal pattern layer contact with the connection bump; A second sealing material layer is disposed on the first sealing material layer, and the surface of the second sealing material layer exposes the second metal pattern layer; The carrier board is removed, so that the surface of the first encapsulant layer exposes the first metal pattern layer. 2. The process according to claim 1, further comprising: A limiting component is formed on the carrier to limit the position of the chip. 3. The process according to claim 2, wherein the limiting component comprises a plurality of limiting cylinders, and the plurality of limiting cylinders are embedded inside the first sealing compound layer and form a loading space; The step of arranging a chip on the first metal pattern layer further includes: arranging the chip in the loading space. 4. The process according to claim 3, wherein the first metal pattern layer comprises a base portion and a heat dissipation portion which are not connected to each other, and the base portion is arranged on the periphery of the heat dissipation portion; The step of arranging the chip on the first metal pattern layer is: arranging the chip on the heat dissipation part, and making the second side contact with the heat dissipation part; The step of forming the limiting component on the carrier plate is: forming the limiting column on the base, and making one end of the limiting column contact the base. 5. The process according to claim 4, characterized in that, the limiting cylinder is a metal cylinder; The step of forming a second metal pattern layer on the first encapsulant layer, and making at least a partial area of the second metal pattern layer contact with the connection bumps further includes: making the second metal pattern At least a partial area of the layer is in contact with the other end of the limiting cylinder. 6 . The process according to claim 5 , wherein the base comprises a plurality of interconnected wiring areas, each of which is provided with at least one limiting post. 7 . 7. The process according to claim 1, characterized in that, the first encapsulant layer is provided on the carrier to cover the first metal pattern layer and the chip, and the first The step of exposing the connection bump on the surface of the sealing material layer comprises: Pressing a first encapsulation prefabricated sheet on the carrier, so that the first encapsulation prefabricated sheet covers the first metal pattern layer and the chip; Polishing the surface of the first encapsulation prefabricated sheet to form the first encapsulation layer and exposing the connection bumps. 8. The process according to claim 1, characterized in that, after the step of forming the first metal pattern layer on the carrier, it further comprises: forming a limiting member on the carrier to limit the chip s position; The step of arranging a first encapsulant layer on the carrier to cover the first metal pattern layer and the chip, and exposing the connection bumps on the surface of the first encapsulant layer includes : Pressing a first encapsulation prefabricated sheet on the carrier, so that the first encapsulation prefabricated sheet covers the first metal pattern layer, the chip and the limiting component; Polishing the surface of the first sealing material prefabricated sheet to form the first sealing material layer, and exposing the connecting bumps and the limiting components. 9. The process according to claim 1, wherein a second sealing material layer is provided on the first sealing material layer, and the surface of the second sealing material layer exposes the second metal pattern Layer steps include: Pressing a second sealing prefabricated sheet on the first sealing material layer, so that the second sealing material prefabricated sheet covers the second metal pattern layer; Polishing the surface of the second encapsulation prefabricated sheet to form the second encapsulation layer and exposing the second metal pattern layer. 10. The process according to claim 1, wherein both the first sealing material layer and the second sealing material layer are resin layers.