CN106449389B - Embedded flash memory structure and preparation method thereof - Google Patents

Abstract

The invention discloses a kind of embedded flash memory structure and preparation method thereof, the production method includes: to provide a substrate, forms a FGS floating gate structure on the substrate；The FGS floating gate structure is etched, forms a groove in the FGS floating gate structure；A barrier layer is deposited, the barrier layer covers side wall and the bottom of the groove；A first medium layer is formed on the barrier layer of the bottom portion of groove；The barrier layer is removed, the barrier layer under the first medium layer is retained；An erasing grid structure is formed on the barrier layer remained.The embedded flash memory structure formed in this way can reduce the coupling ratio of the erasing grid and floating gate, improve the efficiency of erasing of the embedded flash memory structure；It can also enough improving " smile effect " in device, the performance of device is improved.

Description

Embedded flash memory structure and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to an embedded flash memory structure and a manufacturing method thereof.

Background technique

Flash memory has become a research hotspot in non-volatile memory due to its convenience, high storage density, and good reliability. Since the first flash memory product came out in the 1980s, with the development of technology and the storage needs of various electronic products, flash memory has been widely used in mobile and communication devices such as mobile phones, notebooks, handheld computers and U disks. Today, flash memory has occupied most of the market share of non-volatile semiconductor memory, becoming the fastest growing non-volatile semiconductor memory.

It is well known that the coupling ratio between the erase gate (EG) and the floating gate (FG) of the embedded flash memory structure directly affects the erasing efficiency of the embedded flash memory structure. In the prior art, a layer of denser silicon dioxide is deposited between the floating gate and the erase gate, and the silicon dioxide acts as a tunnel oxide layer on the one hand and as an isolation layer between EG and FG , this method improves the erasing efficiency of the embedded flash memory structure to a certain extent, but it is difficult to further reduce the coupling ratio of the erasing gate and the floating gate fabricated in this way. Therefore, how to continue to reduce the coupling ratio between the erasing gate and the floating gate to improve the erasing efficiency of the embedded flash memory structure has become a major problem faced by those skilled in the art.

Contents of the invention

The technical problem to be solved by the present invention is to provide an embedded flash memory structure and its manufacturing method, which can improve the erasing efficiency of the flash memory structure, and improve the isolation mode between the erasing gate and the floating gate by optimizing the process, so as to reduce the erasure rate. The erasing efficiency of the flash memory structure is improved by eliminating the coupling ratio of the gate and the floating gate.

In order to solve the above-mentioned technical problems, a method for manufacturing an embedded flash memory structure provided by the present invention includes:

providing a substrate on which a floating gate structure is formed;

etching the floating gate structure to form a groove in the floating gate structure;

depositing a barrier layer covering the sidewalls and bottom of the groove;

forming a first dielectric layer on the barrier layer at the bottom of the groove;

removing the barrier layer, retaining the barrier layer under the first dielectric layer;

An erase gate structure is formed on the remaining barrier layer.

Further, the step of forming the floating gate structure includes: sequentially depositing a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer on the substrate from bottom to top.

Further, in the step of etching the floating gate structure and forming a groove in the floating gate structure, it includes: sequentially etching the polysilicon layer of the control gate, the inter-gate dielectric layer to the floating gate The upper surface of the polysilicon layer to form a first opening; continue to etch the bottom of the first opening until penetrating through the floating gate polysilicon layer to form a second opening, the cross-sectional width of the second opening is smaller than the first opening A cross-sectional width of , the first opening and the second opening form the groove.

Optionally, in the method for manufacturing the embedded flash memory structure, a first tunnel oxide layer is further deposited between the floating gate polysilicon layer and the substrate.

Preferably, in the manufacturing method of the embedded flash memory structure, the upper surface of the first dielectric layer is lower than the upper surface of the floating gate polysilicon layer.

Optionally, in the step of depositing a barrier layer, the barrier layer covering the sidewall and the bottom of the groove, including depositing a second dielectric layer, the second dielectric layer covering the sidewall of the groove and bottom; depositing the barrier layer on the second dielectric layer.

Further, after removing the blocking layer and before depositing the erasing gate structure, removing the second dielectric layer is also included.

Optionally, in the method for manufacturing the embedded flash memory structure, the barrier layer and the second dielectric layer are removed by wet etching.

Preferably, in the manufacturing method of the embedded flash memory structure, hydrofluoric acid is used to remove the second dielectric layer.

Further, in the manufacturing method of the embedded flash memory structure, when removing the second medium layer, it also includes removing the first medium layer.

Optionally, in the method for manufacturing the embedded flash memory structure, both the first dielectric layer and the second dielectric layer are oxide layers.

Optionally, the step of forming a first dielectric layer on the barrier layer at the bottom of the groove includes: depositing an oxide, the oxide covers the barrier layer and fills the groove; etches the oxide, retaining the oxide on the barrier layer at the bottom of the groove to form the first dielectric layer.

Preferably, the step of depositing an erasing gate structure on the remaining barrier layer includes depositing a second tunneling oxide layer on the remaining barrier layer and on the sidewall of the groove , forming an erasing gate polysilicon layer on the second tunnel oxide layer.

Preferably, in the manufacturing method of the embedded flash memory structure, the barrier layer is a silicon nitride layer.

Optionally, in the method for manufacturing the embedded flash memory structure, the silicon nitride layer is removed by phosphoric acid wet etching.

According to another aspect of the present invention, the present invention also provides an embedded flash memory structure, comprising:

a base;

a floating gate structure, the floating gate structure is located on the substrate;

a groove in the floating gate structure;

an erase gate structure on the substrate and in the groove; and

A blocking layer is located between the erasing gate structure and the substrate, and the blocking layer prevents the substrate and the erasing gate structure from being oxidized.

Further, in the embedded flash memory structure, the floating gate structure includes a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer stacked sequentially from bottom to top on the substrate.

Optionally, in the embedded flash memory structure, a first tunnel oxide layer is further included between the substrate and the floating gate polysilicon layer.

Preferably, in the embedded flash memory structure, the upper surface of the barrier layer is lower than the upper surface of the floating gate polysilicon layer.

Further, in the embedded flash memory structure, the erasing gate structure includes a second tunneling oxide layer on the barrier layer and a second tunneling oxide layer on the second tunneling oxide layer. of the erased gate polysilicon layer.

Preferably, in the embedded flash memory structure, the barrier layer is made of silicon nitride.

Compared with the prior art, the present invention has the following beneficial effects:

In the present invention, a barrier layer is deposited in the groove in the floating gate structure, and then a first dielectric layer is formed on the barrier layer at the bottom of the groove, the barrier layer is removed, and the first dielectric layer is retained the lower barrier layer, and finally, an erasing gate structure is formed on the remaining barrier layer. The embedded flash memory structure formed in this way is isolated between EG and FG through the barrier layer, which can reduce the coupling ratio between EG and FG and improve the erasing efficiency of the embedded flash memory structure; moreover, in the A barrier layer is included between the erasing gate structure and the base, the barrier layer can prevent the base and the erasing gate structure from being oxidized, and can improve the "smile effect" in the device and improve the performance of the device.

Further, the barrier layer is made of silicon nitride, and silicon nitride is used to isolate EG and FG, which can reduce the coupling ratio between EG and FG and improve the erasing efficiency of the embedded flash memory structure.

Description of drawings

Fig. 1 is the flowchart of the manufacturing method of embedded flash memory structure in the embodiment of the present invention;

2 to 10 are structural diagrams corresponding to each step in the method for fabricating the embedded flash memory structure in the embodiment of the present invention.

Detailed ways

During the research process, the inventor found that in the prior art, silicon dioxide is used for isolation between EG and FG, but in the case of limited thickness of silicon dioxide, there is no way to further reduce the coupling ratio between EG and FG ; At the same time, during the corresponding thermal oxidation process, oxygen will pass through the silicon dioxide and react with polysilicon to form a thicker oxide layer, aggravating the "smile effect" of the device, thereby affecting the performance of the device. Therefore, the inventor considers improving the isolation between EG and FG by optimizing the process, thereby improving the embedded flash memory structure, so as to further reduce the coupling ratio of EG and FG, improve the erasing efficiency of the device, and reduce the "smile effect" of the device , to improve device performance.

Based on the above research and discovery, the inventor provides a method for making an embedded flash memory structure, including:

S1. Provide a substrate, and form a floating gate structure on the substrate;

S2. Etching the floating gate structure to form a groove in the floating gate structure;

S3, depositing a barrier layer, the barrier layer covering the sidewall and the bottom of the groove;

S4, forming a first dielectric layer on the barrier layer at the bottom of the groove;

S5. Removing the barrier layer and retaining the barrier layer under the first dielectric layer;

S6, forming an erase gate structure on the remaining barrier layer.

Correspondingly, according to another aspect of the present invention, the present invention also provides an embedded flash memory structure, including:

a base;

a floating gate structure, the floating gate structure is located on the substrate;

a groove in the floating gate structure;

an erase gate structure on the substrate and in the groove; and

A blocking layer is located between the erasing gate structure and the substrate, and the blocking layer prevents the substrate and the erasing gate structure from being oxidized.

In the present invention, a barrier layer is deposited in the groove in the floating gate structure, and then a first dielectric layer is formed on the barrier layer at the bottom of the groove, the barrier layer is removed, and the first dielectric layer is retained the lower barrier layer, and finally, an erasing gate structure is formed on the remaining barrier layer. The embedded flash memory structure formed in this way is isolated between EG and FG through the barrier layer, which can reduce the coupling ratio between EG and FG and improve the erasing efficiency of the embedded flash memory structure; moreover, in the A barrier layer is included between the erasing gate structure and the base, the barrier layer can prevent the base and the erasing gate structure from being oxidized, and can improve the "smile effect" in the device and improve the performance of the device.

An embedded flash memory structure of the present invention and its manufacturing method will be described in more detail below in conjunction with flowcharts and schematic diagrams, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein , while still realizing the advantageous effects of the present invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The following exemplifies the embodiment of the embedded flash memory structure and its manufacturing method, and introduces the content of a kind of embedded flash memory structure and its manufacturing method of the present invention in detail. It should be clear that the content of the present invention is not limited to the following embodiments , and other improvements through conventional technical means by those of ordinary skill in the art are also within the scope of the present invention.

Please refer to FIG. 1 to FIG. 10, wherein FIG. 1 is a flow chart of the manufacturing method of the embedded flash memory structure described in this embodiment, and FIG. 2 to FIG. 10 illustrate the structural diagrams corresponding to each step in the manufacturing method . As shown in Figure 1, the concrete steps of described preparation method comprise:

In step S1 , a substrate 10 is provided, and a floating gate structure 11 is formed on the substrate 10 . Specifically, as shown in FIG. 2 , a first tunnel oxide layer 110 , a floating gate polysilicon layer 111 , an intergate dielectric layer 112 and a control gate polysilicon layer 113 are sequentially deposited on the substrate 10 from bottom to top. In this embodiment, the base 10 is a silicon substrate, of course, in other embodiments, the base 10 can also be a Ge substrate, a SiGe substrate, a SiC substrate, SOI (silicon on insulator, Silicon On Insulator) substrate or GOI (germanium on insulator, Germanium On Insulator) substrate etc., also can be the substrate that comprises other element semiconductor or compound semiconductor, for example glass substrate or III-V group compound substrate (such as gallium nitride substrate or gallium arsenide substrate, etc.), can also be a stacked structure, such as Si/SiGe, etc., or other epitaxial structures, such as SGOI (silicon germanium on insulator) and the like. The inter-gate dielectric layer 112 may be an ONO (Oxide-Nitride-Oxide) layer 112 .

Step S2 , etching the floating gate structure 11 to form a groove in the floating gate structure 11 . In detail, after step S1, first, a hard mask layer 12 is deposited on the control gate polysilicon layer 113, as shown in FIG. film layer 12, the control gate polysilicon layer 113, the inter-gate dielectric layer 112 to the upper surface of the floating gate polysilicon layer 111 to form an opening A1, as shown in FIG. 3; Next, continue to etch the first The bottom of the opening A1 penetrates through the floating gate polysilicon layer 111 (that is, the upper surface of the first tunnel oxide layer 110) to form the second opening A2, and the cross-sectional width of the second opening A2 is smaller than the The cross-sectional width of the first opening A1, the first opening A1 and the second opening A2 constitute the groove, as shown in FIG. 4 . The formation of the first opening A1 and the second opening A2 in this step is realized by photolithography and etching processes well known to those of ordinary skill in the art, which will not be repeated here.

Step S3, depositing a barrier layer 14, the barrier layer 14 covers the sidewall and bottom of the groove. Preferably, as shown in Figure 5, a second dielectric layer 13 is deposited first, and the second dielectric layer 13 covers the sidewall and bottom of the groove, of course, the deposited second dielectric layer 13 also covers The hard mask layer 12 ; then, depositing the barrier layer 14 on the second dielectric layer 13 . Preferably, in this embodiment, the material of the second dielectric layer 13 may be silicon dioxide, and the barrier layer 14 is a silicon nitride layer 14 .

Step S4, forming a first dielectric layer 15' on the barrier layer at the bottom of the groove. Please refer to Fig. 6 and Fig. 7, preferably, the material of the first dielectric layer 15' is oxide, specifically, the steps of forming the first dielectric layer 15' are as follows: first, an oxide 15 is deposited, and the The oxide 15 covers the barrier layer 14 and fills the groove; then, the oxide 15 is etched back to the required thickness, that is, a certain thickness of the oxide is reserved at the bottom of the groove. material to form the first dielectric layer 15'. In addition, the upper surface of the first dielectric layer 15' does not exceed the upper surface of the floating gate polysilicon layer 111, and the oxide may be silicon dioxide.

Step S5, removing the barrier layer 14, and retaining the barrier layer 14' under the first dielectric layer 15'. Preferably, in this embodiment, the material of the barrier layer 14 is silicon nitride, therefore, the barrier layer 14 can be etched by wet method, further, the barrier layer 14 can be removed by hot phosphoric acid. Because the barrier layer at the bottom of the groove is protected by the first dielectric layer 15', the barrier layer 14' under the first dielectric layer 15' will remain after the above process. (that is, the remaining upper surface of the barrier layer 14 ′ is lower than the upper surface of the floating gate polysilicon layer 111 ), as shown in FIG. 8 .

Next, continue to remove the second dielectric layer 13 by wet etching, preferably, remove the second dielectric layer 13 by using hydrofluoric acid. Similarly, the second dielectric layer 13' under the remaining barrier layer 14' will also be preserved. At the same time, because the first dielectric layer 15' and the second dielectric layer 13 are both oxide layers, when the second dielectric layer 13 is removed, the first dielectric layer 15' will also be removed. , forming the structure shown in Figure 9.

Step S6, forming an erasing gate structure 16 on the remaining barrier layer 14'. Generally, the steps of forming the erasing gate structure 16 are as follows: depositing a second tunneling oxide layer 160 on the remaining barrier layer 14' and on the sidewalls of the groove, and then depositing a second tunneling oxide layer 160 on the remaining An erasing gate polysilicon layer 161 is formed on the second tunneling oxide layer 160 to form a final device structure, as shown in FIG. 10 . Of course, this step also involves a corresponding etching process, and it is necessary to obtain the erasing gate polysilicon layer 161 with a certain thickness, which is not the focus of the present invention, and is understandable by those skilled in the art, so it is not convenient to repeat it here.

Therefore, as shown in FIG. 10, the embedded flash memory structure formed in this embodiment includes: a substrate 10; a floating gate structure 11 on the substrate 10, wherein the floating gate structure 11 includes a self- A first tunnel oxide layer 110, a floating gate polysilicon layer 111, an inter-gate dielectric layer 112 and a control gate polysilicon layer 113 stacked in sequence from bottom to top; a groove, the groove is located in the floating gate structure 11; a The erasing gate structure 16, the erasing gate structure 16 is located on the substrate 10 and in the groove; a silicon nitride layer 14', located between the erasing gate structure 16 and the substrate 10 In between, the silicon nitride layer 14' is not only used to isolate the floating gate structure 11 from the erasing gate structure 16, but also prevents the substrate 10 and the erasing gate structure 16 from being oxidized in the subsequent heat treatment. The phenomenon. The erase gate structure 16 includes a second tunnel oxide layer 160 on the silicon nitride 14 ′ and an erase gate polysilicon layer 161 on the second tunnel oxide layer 160 .

In this embodiment, by depositing a silicon nitride layer 14 in the groove in the floating gate structure 11, and then forming the first dielectric layer 15' on the silicon nitride layer at the bottom of the groove, removing In the silicon nitride layer 14 , the silicon nitride layer 14 ′ under the first dielectric layer 15 ′ is retained, and finally, an erasing gate structure 16 is formed on the remaining silicon nitride layer 14 ′. The embedded flash memory structure formed in this way is isolated between EG and FG through the silicon nitride layer 14', which can reduce the coupling ratio between EG and FG and improve the erasing efficiency of the embedded flash memory structure; and, The silicon nitride layer 14' is included between the erasing gate structure 16 and the substrate 10, and the silicon nitride layer 14' can prevent the substrate 10 and the erasing gate structure 16 from being oxidized, It can improve the "smile effect" in the device and improve the performance of the device.

To sum up, the present invention deposits a barrier layer in the groove in the floating gate structure, and then forms a first dielectric layer on the barrier layer at the bottom of the groove, removes the barrier layer, and retains the first dielectric layer. The blocking layer under a dielectric layer, and finally, an erasing gate structure is formed on the remaining blocking layer. The embedded flash memory structure formed in this way is isolated between EG and FG through the barrier layer, which can reduce the coupling ratio between EG and FG and improve the erasing efficiency of the embedded flash memory structure; moreover, in the A barrier layer is included between the erasing gate structure and the base, the barrier layer can prevent the base and the erasing gate structure from being oxidized, and can improve the "smile effect" in the device and improve the performance of the device.

Further, the barrier layer is made of silicon nitride, and silicon nitride is used to isolate EG and FG, which can reduce the coupling ratio between EG and FG and improve the erasing efficiency of the embedded flash memory structure.

In addition, it should be noted that, unless otherwise specified or pointed out, the terms “first” and “second” in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent each Logical or sequential relationships among components, elements, and steps, etc.

It can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (14)

1. a kind of preparation method of embedded flash memory structure, it is characterized in that, described preparation method comprises: providing a substrate on which a floating gate structure is formed; etching the floating gate structure to form a groove in the floating gate structure; depositing a barrier layer covering the sidewalls and bottom of the groove; forming a first dielectric layer on the barrier layer at the bottom of the groove; removing the barrier layer, retaining the barrier layer under the first dielectric layer; forming an erasing gate structure on the remaining barrier layer; Except for the remaining barrier layer, the embedded flash memory structure does not include other barrier layers; the barrier layer is a silicon nitride layer; Wherein, in the step of depositing a barrier layer, the barrier layer covering the side wall and the bottom of the groove, including depositing a second dielectric layer, the second dielectric layer covers the side wall and the bottom of the groove ; depositing the barrier layer on the second dielectric layer; After removing the barrier layer, before depositing the erasing gate structure, it also includes removing the second dielectric layer; when removing the second dielectric layer, it also includes removing the first dielectric layer; The step of forming a first dielectric layer on the barrier layer at the bottom of the groove includes: depositing an oxide, the oxide covers the barrier layer and fills the groove; etch the oxide, leaving the oxide on the barrier layer at the bottom of the groove to form the first dielectric layer. 2. The manufacturing method of the embedded flash memory structure according to claim 1, wherein the forming step of the floating gate structure comprises: sequentially depositing a floating gate polysilicon layer and an intergate dielectric layer on the substrate from bottom to top and control gate polysilicon layer. 3. The manufacturing method of the embedded flash memory structure according to claim 2, wherein, in the step of etching the floating gate structure and forming a groove in the floating gate structure, comprising: sequentially etching the control gate polysilicon layer, the inter-gate dielectric layer to the upper surface of the floating gate polysilicon layer to form a first opening; Continue etching the bottom of the first opening until penetrating through the floating gate polysilicon layer to form a second opening, the cross-sectional width of the second opening is smaller than the cross-sectional width of the first opening, the first opening and The second opening forms the groove. 4. The method for fabricating an embedded flash memory structure according to claim 2, wherein a first tunnel oxide layer is further deposited between the floating gate polysilicon layer and the substrate. 5. The manufacturing method of the embedded flash memory structure according to claim 2, wherein the upper surface of the first dielectric layer is lower than the upper surface of the floating gate polysilicon layer. 6. The method for manufacturing an embedded flash memory structure according to claim 1, wherein the barrier layer and the second dielectric layer are removed by wet etching. 7. The method for fabricating an embedded flash memory structure according to claim 6, wherein the second dielectric layer is removed by using hydrofluoric acid. 8. The method for fabricating an embedded flash memory structure according to claim 1, wherein both the first dielectric layer and the second dielectric layer are oxide layers. 9. The method for fabricating an embedded flash memory structure according to any one of claims 1 to 8, characterized in that, in the step of depositing an erasing gate structure on the remaining barrier layer, including A second tunneling oxide layer is deposited on the barrier layer and on the sidewall of the groove, and an erasing gate polysilicon layer is formed on the second tunneling oxide layer. 10. The manufacturing method of the embedded flash memory structure according to claim 1, wherein the silicon nitride layer is removed by phosphoric acid wet etching. 11. A kind of embedded flash memory structure that utilizes the manufacturing method of the embedded flash memory structure described in claim 1 to make, it is characterized in that, comprising: a base; a floating gate structure, the floating gate structure is located on the substrate; A groove, the groove is located in the floating gate structure, the groove includes a first opening and a second opening below the first opening, the cross-sectional width of the second opening is smaller than the first opening the cross-sectional width of an opening; an erase gate structure on the substrate and in the groove; and a barrier layer located only at the bottom of the erase gate and between the erase gate structure and the substrate, the barrier layer prevents the substrate and the erase gate structure from being oxidized; wherein the The erasing gate structure includes a second tunneling oxide layer on the barrier layer and the sidewall of the groove, and an erasing gate polysilicon layer on the second tunneling oxide layer, except Except for the barrier layer, the embedded flash memory structure does not include other barrier layers; the material of the barrier layer is silicon nitride. 12 . The embedded flash memory structure according to claim 11 , wherein the floating gate structure comprises a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer stacked sequentially from bottom to top on the substrate. 13. The embedded flash memory structure according to claim 12, further comprising a first tunnel oxide layer between the substrate and the floating gate polysilicon layer. 14. The embedded flash memory structure according to claim 12, wherein the upper surface of the barrier layer is lower than the upper surface of the floating gate polysilicon layer.